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1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Blackfin
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *  adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
12 *                     and Antonio Giovanini <antonio@atos.com.br>
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  $Id$
19 */
20
21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#include <rtems/score/bfin.h>            /* pick up machine definitions */
29#ifndef ASM
30#include <rtems/score/types.h>
31#endif
32
33/* conditional compilation parameters */
34
35/**
36 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
37 *
38 *  If TRUE, then they are inlined.
39 *  If FALSE, then a subroutine call is made.
40 *
41 *  This conditional is an example of the classic trade-off of size
42 *  versus speed.  Inlining the call (TRUE) typically increases the
43 *  size of RTEMS while speeding up the enabling of dispatching.
44 *
45 *  @note In general, the @ref _Thread_Dispatch_disable_level will
46 *  only be 0 or 1 unless you are in an interrupt handler and that
47 *  interrupt handler invokes the executive.]  When not inlined
48 *  something calls @ref _Thread_Enable_dispatch which in turns calls
49 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
50 *  one subroutine call is avoided entirely.
51 *
52 *  Port Specific Information:
53 *
54 *  XXX document implementation including references if appropriate
55 */
56#define CPU_INLINE_ENABLE_DISPATCH       FALSE
57
58/**
59 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
60 *  be unrolled one time?  In unrolled each iteration of the loop examines
61 *  two "nodes" on the chain being searched.  Otherwise, only one node
62 *  is examined per iteration.
63 *
64 *  If TRUE, then the loops are unrolled.
65 *  If FALSE, then the loops are not unrolled.
66 *
67 *  The primary factor in making this decision is the cost of disabling
68 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
69 *  body of the loop.  On some CPUs, the flash is more expensive than
70 *  one iteration of the loop body.  In this case, it might be desirable
71 *  to unroll the loop.  It is important to note that on some CPUs, this
72 *  code is the longest interrupt disable period in RTEMS.  So it is
73 *  necessary to strike a balance when setting this parameter.
74 *
75 *  Port Specific Information:
76 *
77 *  XXX document implementation including references if appropriate
78 */
79#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
80
81/**
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 *
104 *  Port Specific Information:
105 *
106 *  XXX document implementation including references if appropriate
107 */
108#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
109
110/**
111 *  Does this CPU have hardware support for a dedicated interrupt stack?
112 *
113 *  If TRUE, then it must be installed during initialization.
114 *  If FALSE, then no installation is performed.
115 *
116 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
117 *
118 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
119 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
120 *  possible that both are FALSE for a particular CPU.  Although it
121 *  is unclear what that would imply about the interrupt processing
122 *  procedure on that CPU.
123 *
124 *  Port Specific Information:
125 *
126 *  XXX document implementation including references if appropriate
127 */
128#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
129
130/**
131 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
132 *
133 *  If TRUE, then the memory is allocated during initialization.
134 *  If FALSE, then the memory is allocated during initialization.
135 *
136 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
137 *
138 *  Port Specific Information:
139 *
140 *  XXX document implementation including references if appropriate
141 */
142#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
143
144/**
145 *  Does the RTEMS invoke the user's ISR with the vector number and
146 *  a pointer to the saved interrupt frame (1) or just the vector
147 *  number (0)?
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_ISR_PASSES_FRAME_POINTER 1
154
155/**
156 *  @def CPU_HARDWARE_FP
157 *
158 *  Does the CPU have hardware floating point?
159 *
160 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
161 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
162 *
163 *  If there is a FP coprocessor such as the i387 or mc68881, then
164 *  the answer is TRUE.
165 *
166 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
167 *  It indicates whether or not this CPU model has FP support.  For
168 *  example, it would be possible to have an i386_nofp CPU model
169 *  which set this to false to indicate that you have an i386 without
170 *  an i387 and wish to leave floating point support out of RTEMS.
171 */
172
173/**
174 *  @def CPU_SOFTWARE_FP
175 *
176 *  Does the CPU have no hardware floating point and GCC provides a
177 *  software floating point implementation which must be context
178 *  switched?
179 *
180 *  This feature conditional is used to indicate whether or not there
181 *  is software implemented floating point that must be context
182 *  switched.  The determination of whether or not this applies
183 *  is very tool specific and the state saved/restored is also
184 *  compiler specific.
185 *
186 *  Port Specific Information:
187 *
188 *  XXX document implementation including references if appropriate
189 */
190#if ( BLACKFIN_CPU_HAS_FPU == 1 )
191#define CPU_HARDWARE_FP     TRUE
192#else
193#define CPU_HARDWARE_FP     FALSE
194#endif
195#define CPU_SOFTWARE_FP     FALSE
196
197/**
198 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
199 *
200 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
201 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
202 *
203 *  So far, the only CPUs in which this option has been used are the
204 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
205 *  gcc both implicitly used the floating point registers to perform
206 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
207 *  seen to allocate floating point local variables and touch the FPU
208 *  even when the flow through a subroutine (like vfprintf()) might
209 *  not use floating point formats.
210 *
211 *  If a function which you would not think utilize the FP unit DOES,
212 *  then one can not easily predict which tasks will use the FP hardware.
213 *  In this case, this option should be TRUE.
214 *
215 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
216 *
217 *  Port Specific Information:
218 *
219 *  XXX document implementation including references if appropriate
220 */
221#define CPU_ALL_TASKS_ARE_FP     FALSE
222
223/**
224 *  Should the IDLE task have a floating point context?
225 *
226 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
227 *  and it has a floating point context which is switched in and out.
228 *  If FALSE, then the IDLE task does not have a floating point context.
229 *
230 *  Setting this to TRUE negatively impacts the time required to preempt
231 *  the IDLE task from an interrupt because the floating point context
232 *  must be saved as part of the preemption.
233 *
234 *  Port Specific Information:
235 *
236 *  XXX document implementation including references if appropriate
237 */
238#define CPU_IDLE_TASK_IS_FP      FALSE
239
240/**
241 *  Should the saving of the floating point registers be deferred
242 *  until a context switch is made to another different floating point
243 *  task?
244 *
245 *  If TRUE, then the floating point context will not be stored until
246 *  necessary.  It will remain in the floating point registers and not
247 *  disturned until another floating point task is switched to.
248 *
249 *  If FALSE, then the floating point context is saved when a floating
250 *  point task is switched out and restored when the next floating point
251 *  task is restored.  The state of the floating point registers between
252 *  those two operations is not specified.
253 *
254 *  If the floating point context does NOT have to be saved as part of
255 *  interrupt dispatching, then it should be safe to set this to TRUE.
256 *
257 *  Setting this flag to TRUE results in using a different algorithm
258 *  for deciding when to save and restore the floating point context.
259 *  The deferred FP switch algorithm minimizes the number of times
260 *  the FP context is saved and restored.  The FP context is not saved
261 *  until a context switch is made to another, different FP task.
262 *  Thus in a system with only one FP task, the FP context will never
263 *  be saved or restored.
264 *
265 *  Port Specific Information:
266 *
267 *  XXX document implementation including references if appropriate
268 */
269#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
270
271/**
272 *  Does this port provide a CPU dependent IDLE task implementation?
273 *
274 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
275 *  must be provided and is the default IDLE thread body instead of
276 *  @ref _CPU_Thread_Idle_body.
277 *
278 *  If FALSE, then use the generic IDLE thread body if the BSP does
279 *  not provide one.
280 *
281 *  This is intended to allow for supporting processors which have
282 *  a low power or idle mode.  When the IDLE thread is executed, then
283 *  the CPU can be powered down.
284 *
285 *  The order of precedence for selecting the IDLE thread body is:
286 *
287 *    -#  BSP provided
288 *    -#  CPU dependent (if provided)
289 *    -#  generic (if no BSP and no CPU dependent)
290 *
291 *  Port Specific Information:
292 *
293 *  XXX document implementation including references if appropriate
294 */
295#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
296
297/**
298 *  Does the stack grow up (toward higher addresses) or down
299 *  (toward lower addresses)?
300 *
301 *  If TRUE, then the grows upward.
302 *  If FALSE, then the grows toward smaller addresses.
303 *
304 *  Port Specific Information:
305 *
306 *  XXX document implementation including references if appropriate
307 */
308#define CPU_STACK_GROWS_UP               FALSE
309
310/**
311 *  The following is the variable attribute used to force alignment
312 *  of critical RTEMS structures.  On some processors it may make
313 *  sense to have these aligned on tighter boundaries than
314 *  the minimum requirements of the compiler in order to have as
315 *  much of the critical data area as possible in a cache line.
316 *
317 *  The placement of this macro in the declaration of the variables
318 *  is based on the syntactically requirements of the GNU C
319 *  "__attribute__" extension.  For example with GNU C, use
320 *  the following to force a structures to a 32 byte boundary.
321 *
322 *      __attribute__ ((aligned (32)))
323 *
324 *  @note Currently only the Priority Bit Map table uses this feature.
325 *        To benefit from using this, the data must be heavily
326 *        used so it will stay in the cache and used frequently enough
327 *        in the executive to justify turning this on.
328 *
329 *  Port Specific Information:
330 *
331 *  XXX document implementation including references if appropriate
332 */
333#define CPU_STRUCTURE_ALIGNMENT
334
335/**
336 *  @defgroup CPUEndian Processor Dependent Endianness Support
337 *
338 *  This group assists in issues related to processor endianness.
339 */
340
341/**
342 *  @ingroup CPUEndian
343 *  Define what is required to specify how the network to host conversion
344 *  routines are handled.
345 *
346 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
347 *  same values.
348 *
349 *  @see CPU_LITTLE_ENDIAN
350 *
351 *  Port Specific Information:
352 *
353 *  XXX document implementation including references if appropriate
354 */
355#define CPU_BIG_ENDIAN                           FALSE
356
357/**
358 *  @ingroup CPUEndian
359 *  Define what is required to specify how the network to host conversion
360 *  routines are handled.
361 *
362 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
363 *  same values.
364 *
365 *  @see CPU_BIG_ENDIAN
366 *
367 *  Port Specific Information:
368 *
369 *  XXX document implementation including references if appropriate
370 */
371#define CPU_LITTLE_ENDIAN                        TRUE
372
373/**
374 *  @ingroup CPUInterrupt
375 *  The following defines the number of bits actually used in the
376 *  interrupt field of the task mode.  How those bits map to the
377 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
378 *
379 *  Port Specific Information:
380 *
381 *  XXX document implementation including references if appropriate
382 */
383#define CPU_MODES_INTERRUPT_MASK   0x00000002
384
385/*
386 *  Processor defined structures required for cpukit/score.
387 *
388 *  Port Specific Information:
389 *
390 *  XXX document implementation including references if appropriate
391 */
392
393/* may need to put some structures here.  */
394
395/**
396 * @defgroup CPUContext Processor Dependent Context Management
397 *
398 *  From the highest level viewpoint, there are 2 types of context to save.
399 *
400 *     -# Interrupt registers to save
401 *     -# Task level registers to save
402 *
403 *  Since RTEMS handles integer and floating point contexts separately, this
404 *  means we have the following 3 context items:
405 *
406 *     -# task level context stuff::  Context_Control
407 *     -# floating point task stuff:: Context_Control_fp
408 *     -# special interrupt level context :: CPU_Interrupt_frame
409 *
410 *  On some processors, it is cost-effective to save only the callee
411 *  preserved registers during a task context switch.  This means
412 *  that the ISR code needs to save those registers which do not
413 *  persist across function calls.  It is not mandatory to make this
414 *  distinctions between the caller/callee saves registers for the
415 *  purpose of minimizing context saved during task switch and on interrupts.
416 *  If the cost of saving extra registers is minimal, simplicity is the
417 *  choice.  Save the same context on interrupt entry as for tasks in
418 *  this case.
419 *
420 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
421 *  care should be used in designing the context area.
422 *
423 *  On some CPUs with hardware floating point support, the Context_Control_fp
424 *  structure will not be used or it simply consist of an array of a
425 *  fixed number of bytes.   This is done when the floating point context
426 *  is dumped by a "FP save context" type instruction and the format
427 *  is not really defined by the CPU.  In this case, there is no need
428 *  to figure out the exact format -- only the size.  Of course, although
429 *  this is enough information for RTEMS, it is probably not enough for
430 *  a debugger such as gdb.  But that is another problem.
431 *
432 *  Port Specific Information:
433 *
434 *  XXX document implementation including references if appropriate
435 */
436
437/**
438 *  @ingroup CPUContext Management
439 *  This defines the minimal set of integer and processor state registers
440 *  that must be saved during a voluntary context switch from one thread
441 *  to another.
442 */
443typedef struct {
444    /* we are saving all registers, maybe we should not */
445   
446    uint32_t   register_r0;
447    uint32_t   register_r1;
448    uint32_t   register_r2;
449    uint32_t   register_r3;
450    uint32_t   register_r4;
451    uint32_t   register_r5;
452    uint32_t   register_r6;
453    uint32_t   register_r7;
454    uint32_t   register_p0;
455    uint32_t   register_p1;
456    uint32_t   register_p2;
457    uint32_t   register_p3;
458    uint32_t   register_p4;
459    uint32_t   register_p5;                         
460    uint32_t   register_fp;
461    uint32_t   register_sp;
462   
463    uint32_t   register_i0;                         
464    uint32_t   register_i1;
465    uint32_t   register_i2;
466    uint32_t   register_i3;
467   
468    uint32_t   register_m0;
469    uint32_t   register_m1;
470    uint32_t   register_m2;
471    uint32_t   register_m3;
472
473    uint32_t   register_b0;
474    uint32_t   register_b1;
475    uint32_t   register_b2;
476    uint32_t   register_b3;
477
478    uint32_t   register_l0;
479    uint32_t   register_l1;
480    uint32_t   register_l2;
481    uint32_t   register_l3;   
482   
483    uint32_t   register_a0dotx;
484    uint32_t   register_a0dotw;
485    uint32_t   register_a1dotx;
486    uint32_t   register_a1dotw;
487    uint32_t   register_astat;
488    uint32_t   register_rets;
489    uint32_t   register_lc0;
490    uint32_t   register_lt0;
491    uint32_t   register_lb0;
492    uint32_t   register_lc1;
493    uint32_t   register_lt1;
494    uint32_t   register_lb1;
495 
496  /*BFIN_CYCLES_REGNUM,
497  BFIN_CYCLES2_REGNUM, */
498 
499    uint32_t   register_usp;
500    uint32_t   register_seqstat;
501    uint32_t   register_syscfg;
502    uint32_t   register_reti;
503    uint32_t   register_retx;
504    uint32_t   register_retn;
505    uint32_t   register_rete;
506
507    uint32_t   register_pc;
508
509  /*
510  Pseudo Registers
511  BFIN_PC_REGNUM,
512  BFIN_CC_REGNUM,
513  BFIN_EXTRA1,       Address of .text section.
514  BFIN_EXTRA2,       Address of .data section.
515  BFIN_EXTRA3,       Address of .bss section. 
516
517  BFIN_FDPIC_EXEC_REGNUM,
518  BFIN_FDPIC_INTERP_REGNUM,
519
520  MMRs
521  BFIN_IPEND_REGNUM,
522
523  LAST ENTRY SHOULD NOT BE CHANGED.
524  BFIN_NUM_REGS      The number of all registers.
525  */ 
526} Context_Control;
527
528/**
529 *  @ingroup CPUContext Management
530 *  This defines the complete set of floating point registers that must
531 *  be saved during any context switch from one thread to another.
532 */
533typedef struct {
534    /* FPU registers are listed here */
535    /* Blackfin has no Floating Point */
536} Context_Control_fp;
537
538/**
539 *  @ingroup CPUContext Management
540 *  This defines the set of integer and processor state registers that must
541 *  be saved during an interrupt.  This set does not include any which are
542 *  in @ref Context_Control.
543 */
544typedef struct {
545    /** This field is a hint that a port will have a number of integer
546     *  registers that need to be saved when an interrupt occurs or
547     *  when a context switch occurs at the end of an ISR.
548     */
549    /*uint32_t   special_interrupt_register;*/
550} CPU_Interrupt_frame;
551
552
553/**
554 *  The following table contains the information required to configure
555 *  the XXX processor specific parameters.
556 *
557 *  Port Specific Information:
558 *
559 *  XXX document implementation including references if appropriate
560 */
561
562typedef struct {
563  /** This element points to the BSP's pretasking hook. */
564  void       (*pretasking_hook)( void );
565  /** This element points to the BSP's predriver hook. */
566  void       (*predriver_hook)( void );
567  /** This element points to the BSP's postdriver hook. */
568  void       (*postdriver_hook)( void );
569  /** This element points to the BSP's optional idle task which may override
570   *  the default one provided with RTEMS.
571   */
572  void       (*idle_task)( void );
573  /** If this element is TRUE, then RTEMS will zero the Executive Workspace.
574   *  When this element is FALSE, it is assumed that the BSP or invoking
575   *  environment has ensured that memory was cleared before RTEMS was
576   *  invoked.
577   */
578  boolean      do_zero_of_workspace;
579  /** This field specifies the size of the IDLE task's stack.  If less than or
580   *  equal to the minimum stack size, then the IDLE task will have the minimum
581   *  stack size.
582   */
583  uint32_t     idle_task_stack_size;
584  /** This field specifies the size of the interrupt stack.  If less than or
585   *  equal to the minimum stack size, then the interrupt stack will be of
586   *  minimum stack size.
587   */
588  uint32_t     interrupt_stack_size;
589  /** The MPCI Receive server is assumed to have a stack of at least
590   *  minimum stack size.  This field specifies the amount of extra
591   *  stack this task will be given in bytes.
592   */
593  uint32_t     extra_mpci_receive_server_stack;
594  /** The BSP may want to provide it's own stack allocation routines.
595   *  In this case, the BSP will provide this stack allocation hook.
596   */
597  void *     (*stack_allocate_hook)( uint32_t   );
598  /** The BSP may want to provide it's own stack free routines.
599   *  In this case, the BSP will provide this stack free hook.
600   */
601  void       (*stack_free_hook)( void *);
602  /* end of fields required on all CPUs */
603}   rtems_cpu_table;
604
605/*
606 *  Macros to access required entires in the CPU Table are in
607 *  the file rtems/system.h.
608 *
609 *  Port Specific Information:
610 *
611 *  XXX document implementation including references if appropriate
612 */
613
614/*
615 *  Macros to access Blackfin specific additions to the CPU Table
616 *
617 *  Port Specific Information:
618 *
619 *  XXX document implementation including references if appropriate
620 */
621
622/* There are no CPU specific additions to the CPU Table for this port. */
623
624/**
625 *  This variable is optional.  It is used on CPUs on which it is difficult
626 *  to generate an "uninitialized" FP context.  It is filled in by
627 *  @ref _CPU_Initialize and copied into the task's FP context area during
628 *  @ref _CPU_Context_Initialize.
629 *
630 *  Port Specific Information:
631 *
632 *  XXX document implementation including references if appropriate
633 */
634SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
635
636/**
637 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
638 *
639 *  On some CPUs, RTEMS supports a software managed interrupt stack.
640 *  This stack is allocated by the Interrupt Manager and the switch
641 *  is performed in @ref _ISR_Handler.  These variables contain pointers
642 *  to the lowest and highest addresses in the chunk of memory allocated
643 *  for the interrupt stack.  Since it is unknown whether the stack
644 *  grows up or down (in general), this give the CPU dependent
645 *  code the option of picking the version it wants to use.
646 *
647 *  @note These two variables are required if the macro
648 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
649 *
650 *  Port Specific Information:
651 *
652 *  XXX document implementation including references if appropriate
653 */
654
655/**
656 *  @ingroup CPUInterrupt
657 *  This variable points to the lowest physical address of the interrupt
658 *  stack.
659 */
660SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
661
662/**
663 *  @ingroup CPUInterrupt
664 *  This variable points to the lowest physical address of the interrupt
665 *  stack.
666 */
667SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
668
669/**
670 *  @ingroup CPUInterrupt
671 *  With some compilation systems, it is difficult if not impossible to
672 *  call a high-level language routine from assembly language.  This
673 *  is especially true of commercial Ada compilers and name mangling
674 *  C++ ones.  This variable can be optionally defined by the CPU porter
675 *  and contains the address of the routine @ref _Thread_Dispatch.  This
676 *  can make it easier to invoke that routine at the end of the interrupt
677 *  sequence (if a dispatch is necessary).
678 *
679 *  Port Specific Information:
680 *
681 *  XXX document implementation including references if appropriate
682 */
683SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
684
685/*
686 *  Nothing prevents the porter from declaring more CPU specific variables.
687 *
688 *  Port Specific Information:
689 *
690 *  XXX document implementation including references if appropriate
691 */
692
693/* XXX: if needed, put more variables here */
694
695/**
696 *  @ingroup CPUContext
697 *  The size of the floating point context area.  On some CPUs this
698 *  will not be a "sizeof" because the format of the floating point
699 *  area is not defined -- only the size is.  This is usually on
700 *  CPUs with a "floating point save context" instruction.
701 *
702 *  Port Specific Information:
703 *
704 *  XXX document implementation including references if appropriate
705 */
706#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
707
708/**
709 *  Amount of extra stack (above minimum stack size) required by
710 *  MPCI receive server thread.  Remember that in a multiprocessor
711 *  system this thread must exist and be able to process all directives.
712 *
713 *  Port Specific Information:
714 *
715 *  XXX document implementation including references if appropriate
716 */
717#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
718
719/**
720 *  @ingroup CPUInterrupt
721 *  This defines the number of entries in the @ref _ISR_Vector_table managed
722 *  by RTEMS.
723 *
724 *  Port Specific Information:
725 *
726 *  XXX document implementation including references if appropriate
727 */
728#define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
729
730/**
731 *  @ingroup CPUInterrupt
732 *  This defines the highest interrupt vector number for this port.
733 */
734#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
735
736/**
737 *  @ingroup CPUInterrupt
738 *  This is defined if the port has a special way to report the ISR nesting
739 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
740 */
741#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
742
743/**
744 *  @ingroup CPUContext
745 *  Should be large enough to run all RTEMS tests.  This ensures
746 *  that a "reasonable" small application should not have any problems.
747 *
748 *  Port Specific Information:
749 *
750 *  XXX document implementation including references if appropriate
751 */
752#define CPU_STACK_MINIMUM_SIZE          (1024*4)
753
754/**
755 *  CPU's worst alignment requirement for data types on a byte boundary.  This
756 *  alignment does not take into account the requirements for the stack.
757 *
758 *  Port Specific Information:
759 *
760 *  XXX document implementation including references if appropriate
761 */
762#define CPU_ALIGNMENT              8
763
764/**
765 *  This number corresponds to the byte alignment requirement for the
766 *  heap handler.  This alignment requirement may be stricter than that
767 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
768 *  common for the heap to follow the same alignment requirement as
769 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
770 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
771 *
772 *  @note  This does not have to be a power of 2 although it should be
773 *         a multiple of 2 greater than or equal to 2.  The requirement
774 *         to be a multiple of 2 is because the heap uses the least
775 *         significant field of the front and back flags to indicate
776 *         that a block is in use or free.  So you do not want any odd
777 *         length blocks really putting length data in that bit.
778 *
779 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
780 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
781 *         elements allocated from the heap meet all restrictions.
782 *
783 *  Port Specific Information:
784 *
785 *  XXX document implementation including references if appropriate
786 */
787#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
788
789/**
790 *  This number corresponds to the byte alignment requirement for memory
791 *  buffers allocated by the partition manager.  This alignment requirement
792 *  may be stricter than that for the data types alignment specified by
793 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
794 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
795 *  strict enough for the partition, then this should be set to
796 *  @ref CPU_ALIGNMENT.
797 *
798 *  @note  This does not have to be a power of 2.  It does have to
799 *         be greater or equal to than @ref CPU_ALIGNMENT.
800 *
801 *  Port Specific Information:
802 *
803 *  XXX document implementation including references if appropriate
804 */
805#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
806
807/**
808 *  This number corresponds to the byte alignment requirement for the
809 *  stack.  This alignment requirement may be stricter than that for the
810 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
811 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
812 *  set to 0.
813 *
814 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
815 *
816 *  Port Specific Information:
817 *
818 *  XXX document implementation including references if appropriate
819 */
820#define CPU_STACK_ALIGNMENT        0
821
822/*
823 *  ISR handler macros
824 */
825
826/**
827 *  @ingroup CPUInterrupt
828 *  Support routine to initialize the RTEMS vector table after it is allocated.
829 *
830 *  Port Specific Information:
831 *
832 *  XXX document implementation including references if appropriate
833 */
834#define _CPU_Initialize_vectors()
835
836/**
837 *  @ingroup CPUInterrupt
838 *  Disable all interrupts for an RTEMS critical section.  The previous
839 *  level is returned in @a _isr_cookie.
840 *
841 *  @param[out] _isr_cookie will contain the previous level cookie
842 *
843 *  Port Specific Information:
844 *
845 *  XXX document implementation including references if appropriate
846 */
847#define _CPU_ISR_Disable( _level ) \
848  {                                     \
849    asm volatile ("cli %0 \n"           \
850                   : "=r" (_level) );   \
851                                        \
852  }
853 
854
855/**
856 *  @ingroup CPUInterrupt
857 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
858 *  This indicates the end of an RTEMS critical section.  The parameter
859 *  @a _isr_cookie is not modified.
860 *
861 *  @param[in] _isr_cookie contain the previous level cookie
862 *
863 *  Port Specific Information:
864 *
865 *  XXX document implementation including references if appropriate
866 */
867#define _CPU_ISR_Enable( _level )  \
868  {                                   \
869    asm volatile ("STI %0"            \
870                   : : "r" (_level) );  \
871  }
872
873/**
874 *  @ingroup CPUInterrupt
875 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
876 *  disabling them again.  This is used to divide long RTEMS critical
877 *  sections into two or more parts.  The parameter @a _isr_cookie is not
878 *  modified.
879 *
880 *  @param[in] _isr_cookie contain the previous level cookie
881 *
882 *  Port Specific Information:
883 *
884 *  XXX document implementation including references if appropriate
885 */
886#define _CPU_ISR_Flash( _level )
887/*  { \
888    asm volatile ("cli %0;\n"          \
889                  "ssync; \n"           \
890                  "sti %1; \n"          \
891                   : "=r" (_level) : "0"(_level) );  \
892  }*/
893
894/**
895 *  @ingroup CPUInterrupt
896 *
897 *  This routine and @ref _CPU_ISR_Get_level
898 *  Map the interrupt level in task mode onto the hardware that the CPU
899 *  actually provides.  Currently, interrupt levels which do not
900 *  map onto the CPU in a generic fashion are undefined.  Someday,
901 *  it would be nice if these were "mapped" by the application
902 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
903 *  8 - 255 would be available for bsp/application specific meaning.
904 *  This could be used to manage a programmable interrupt controller
905 *  via the rtems_task_mode directive.
906 *
907 *  Port Specific Information:
908 *
909 *  XXX document implementation including references if appropriate
910 */
911#define _CPU_ISR_Set_level( _new_level ) \
912  { \
913    if ( _new_level ) asm volatile ( "cli R0;" : : : "R0" ); \
914    else              asm volatile ( "R0.l = 0xFFFF;\n"\
915                                     "sti R0;" : : : "R0" ); \
916  }
917
918
919/**
920 *  @ingroup CPUInterrupt
921 *  Return the current interrupt disable level for this task in
922 *  the format used by the interrupt level portion of the task mode.
923 *
924 *  @note This routine usually must be implemented as a subroutine.
925 *
926 *  Port Specific Information:
927 *
928 *  XXX document implementation including references if appropriate
929 */
930uint32_t   _CPU_ISR_Get_level( void );
931
932/* end of ISR handler macros */
933
934/* Context handler macros */
935
936/**
937 *  @ingroup CPUContext
938 *  Initialize the context to a state suitable for starting a
939 *  task after a context restore operation.  Generally, this
940 *  involves:
941 *
942 *     - setting a starting address
943 *     - preparing the stack
944 *     - preparing the stack and frame pointers
945 *     - setting the proper interrupt level in the context
946 *     - initializing the floating point context
947 *
948 *  This routine generally does not set any unnecessary register
949 *  in the context.  The state of the "general data" registers is
950 *  undefined at task start time.
951 *
952 *  @param[in] _the_context is the context structure to be initialized
953 *  @param[in] _stack_base is the lowest physical address of this task's stack
954 *  @param[in] _size is the size of this task's stack
955 *  @param[in] _isr is the interrupt disable level
956 *  @param[in] _entry_point is the thread's entry point.  This is
957 *         always @a _Thread_Handler
958 *  @param[in] _is_fp is TRUE if the thread is to be a floating
959 *        point thread.  This is typically only used on CPUs where the
960 *        FPU may be easily disabled by software such as on the SPARC
961 *        where the PSR contains an enable FPU bit.
962 *
963 *  Port Specific Information:
964 *
965 *  See implementation in cpu.c
966 */
967void _CPU_Context_Initialize(
968  Context_Control  *the_context,
969  uint32_t         *stack_base,
970  uint32_t          size,
971  uint32_t          new_level,
972  void             *entry_point,
973  boolean           is_fp
974);
975
976/**
977 *  This routine is responsible for somehow restarting the currently
978 *  executing task.  If you are lucky, then all that is necessary
979 *  is restoring the context.  Otherwise, there will need to be
980 *  a special assembly routine which does something special in this
981 *  case.  For many ports, simply adding a label to the restore path
982 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
983 *  possibly to load a few arguments and jump to the restore path. It will
984 *  not work if restarting self conflicts with the stack frame
985 *  assumptions of restoring a context.
986 *
987 *  Port Specific Information:
988 *
989 *  XXX document implementation including references if appropriate
990 */
991#define _CPU_Context_Restart_self( _the_context ) \
992   _CPU_Context_restore( (_the_context) );
993
994/**
995 *  @ingroup CPUContext
996 *  The purpose of this macro is to allow the initial pointer into
997 *  a floating point context area (used to save the floating point
998 *  context) to be at an arbitrary place in the floating point
999 *  context area.
1000 *
1001 *  This is necessary because some FP units are designed to have
1002 *  their context saved as a stack which grows into lower addresses.
1003 *  Other FP units can be saved by simply moving registers into offsets
1004 *  from the base of the context area.  Finally some FP units provide
1005 *  a "dump context" instruction which could fill in from high to low
1006 *  or low to high based on the whim of the CPU designers.
1007 *
1008 *  @param[in] _base is the lowest physical address of the floating point
1009 *         context area
1010 *  @param[in] _offset is the offset into the floating point area
1011 *
1012 *  Port Specific Information:
1013 *
1014 *  XXX document implementation including references if appropriate
1015 */
1016#define _CPU_Context_Fp_start( _base, _offset ) \
1017   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
1018
1019/**
1020 *  This routine initializes the FP context area passed to it to.
1021 *  There are a few standard ways in which to initialize the
1022 *  floating point context.  The code included for this macro assumes
1023 *  that this is a CPU in which a "initial" FP context was saved into
1024 *  @a _CPU_Null_fp_context and it simply copies it to the destination
1025 *  context passed to it.
1026 *
1027 *  Other floating point context save/restore models include:
1028 *    -# not doing anything, and
1029 *    -# putting a "null FP status word" in the correct place in the FP context.
1030 *
1031 *  @param[in] _destination is the floating point context area
1032 *
1033 *  Port Specific Information:
1034 *
1035 *  XXX document implementation including references if appropriate
1036 */
1037#define _CPU_Context_Initialize_fp( _destination ) \
1038  { \
1039   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
1040  }
1041
1042/* end of Context handler macros */
1043
1044/* Fatal Error manager macros */
1045
1046/**
1047 *  This routine copies _error into a known place -- typically a stack
1048 *  location or a register, optionally disables interrupts, and
1049 *  halts/stops the CPU.
1050 *
1051 *  Port Specific Information:
1052 *
1053 *  XXX document implementation including references if appropriate
1054 */
1055#define _CPU_Fatal_halt( _error ) \
1056  { \
1057    asm volatile ( "cli R1; \
1058                    R1 = %0; \
1059                    _halt: \
1060                    jump _halt;"\
1061                    : "=r" (_error) ); \
1062  }
1063
1064/* end of Fatal Error manager macros */
1065
1066/* Bitfield handler macros */
1067
1068/**
1069 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1070 *
1071 *  This set of routines are used to implement fast searches for
1072 *  the most important ready task.
1073 */
1074
1075/**
1076 *  @ingroup CPUBitfield
1077 *  This definition is set to TRUE if the port uses the generic bitfield
1078 *  manipulation implementation.
1079 */
1080#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1081
1082/**
1083 *  @ingroup CPUBitfield
1084 *  This definition is set to TRUE if the port uses the data tables provided
1085 *  by the generic bitfield manipulation implementation.
1086 *  This can occur when actually using the generic bitfield manipulation
1087 *  implementation or when implementing the same algorithm in assembly
1088 *  language for improved performance.  It is unlikely that a port will use
1089 *  the data if it has a bitfield scan instruction.
1090 */
1091#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1092
1093/**
1094 *  @ingroup CPUBitfield
1095 *  This routine sets @a _output to the bit number of the first bit
1096 *  set in @a _value.  @a _value is of CPU dependent type
1097 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
1098 *  wide although only the 16 least significant bits will be used.
1099 *
1100 *  There are a number of variables in using a "find first bit" type
1101 *  instruction.
1102 *
1103 *    -# What happens when run on a value of zero?
1104 *    -# Bits may be numbered from MSB to LSB or vice-versa.
1105 *    -# The numbering may be zero or one based.
1106 *    -# The "find first bit" instruction may search from MSB or LSB.
1107 *
1108 *  RTEMS guarantees that (1) will never happen so it is not a concern.
1109 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1110 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
1111 *  which must logically operate together.  Bits in the _value are
1112 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
1113 *  The basic major and minor values calculated by @ref _Priority_Major
1114 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1115 *  to properly range between the values returned by the "find first bit"
1116 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
1117 *  calculate the major and directly index into the minor table.
1118 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1119 *  is the first bit found.
1120 *
1121 *  This entire "find first bit" and mapping process depends heavily
1122 *  on the manner in which a priority is broken into a major and minor
1123 *  components with the major being the 4 MSB of a priority and minor
1124 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1125 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1126 *  to the lowest priority.
1127 *
1128 *  If your CPU does not have a "find first bit" instruction, then
1129 *  there are ways to make do without it.  Here are a handful of ways
1130 *  to implement this in software:
1131 *
1132@verbatim
1133      - a series of 16 bit test instructions
1134      - a "binary search using if's"
1135      - _number = 0
1136        if _value > 0x00ff
1137          _value >>=8
1138          _number = 8;
1139 
1140        if _value > 0x0000f
1141          _value >=8
1142          _number += 4
1143 
1144        _number += bit_set_table[ _value ]
1145@endverbatim
1146 
1147 *    where bit_set_table[ 16 ] has values which indicate the first
1148 *      bit set
1149 *
1150 *  @param[in] _value is the value to be scanned
1151 *  @param[in] _output is the first bit set
1152 *
1153 *  Port Specific Information:
1154 *
1155 *  XXX document implementation including references if appropriate
1156 */
1157
1158#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1159#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1160  { \
1161    asm ("bit(1);"):
1162    (_output) = 0;   /* do something to prevent warnings */ \
1163  }
1164#endif
1165
1166/* end of Bitfield handler macros */
1167
1168/**
1169 *  This routine builds the mask which corresponds to the bit fields
1170 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1171 *  for that routine.
1172 *
1173 *  Port Specific Information:
1174 *
1175 *  XXX document implementation including references if appropriate
1176 */
1177#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1178
1179#define _CPU_Priority_Mask( _bit_number ) \
1180  ( 1 << (_bit_number) )
1181
1182#endif
1183
1184/**
1185 *  @ingroup CPUBitfield
1186 *  This routine translates the bit numbers returned by
1187 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1188 *  a major or minor component of a priority.  See the discussion
1189 *  for that routine.
1190 *
1191 *  @param[in] _priority is the major or minor number to translate
1192 *
1193 *  Port Specific Information:
1194 *
1195 *  XXX document implementation including references if appropriate
1196 */
1197#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1198
1199#define _CPU_Priority_bits_index( _priority ) \
1200  (_priority)
1201
1202#endif
1203
1204/* end of Priority handler macros */
1205
1206/* functions */
1207
1208/**
1209 *  This routine performs CPU dependent initialization.
1210 *
1211 *  @param[in] cpu_table is the CPU Dependent Configuration Table
1212 *  @param[in] thread_dispatch is the address of @ref _Thread_Dispatch
1213 *
1214 *  Port Specific Information:
1215 *
1216 *  XXX document implementation including references if appropriate
1217 */
1218void _CPU_Initialize(
1219  rtems_cpu_table  *cpu_table,
1220  void      (*thread_dispatch)
1221);
1222
1223/**
1224 *  @ingroup CPUInterrupt
1225 *  This routine installs a "raw" interrupt handler directly into the
1226 *  processor's vector table.
1227 *
1228 *  @param[in] vector is the vector number
1229 *  @param[in] new_handler is the raw ISR handler to install
1230 *  @param[in] old_handler is the previously installed ISR Handler
1231 *
1232 *  Port Specific Information:
1233 *
1234 *  XXX document implementation including references if appropriate
1235 */
1236void _CPU_ISR_install_raw_handler(
1237  uint32_t    vector,
1238  proc_ptr    new_handler,
1239  proc_ptr   *old_handler
1240);
1241
1242/**
1243 *  @ingroup CPUInterrupt
1244 *  This routine installs an interrupt vector.
1245 *
1246 *  @param[in] vector is the vector number
1247 *  @param[in] new_handler is the RTEMS ISR handler to install
1248 *  @param[in] old_handler is the previously installed ISR Handler
1249 *
1250 *  Port Specific Information:
1251 *
1252 *  XXX document implementation including references if appropriate
1253 */
1254void _CPU_ISR_install_vector(
1255  uint32_t    vector,
1256  proc_ptr    new_handler,
1257  proc_ptr   *old_handler
1258);
1259
1260/**
1261 *  @ingroup CPUInterrupt
1262 *  This routine installs the hardware interrupt stack pointer.
1263 *
1264 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1265 *         is TRUE.
1266 *
1267 *  Port Specific Information:
1268 *
1269 *  XXX document implementation including references if appropriate
1270 */
1271void _CPU_Install_interrupt_stack( void );
1272
1273/**
1274 *  This routine is the CPU dependent IDLE thread body.
1275 *
1276 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1277 *         is TRUE.
1278 *
1279 *  Port Specific Information:
1280 *
1281 *  XXX document implementation including references if appropriate
1282 */
1283void _CPU_Thread_Idle_body( void );
1284
1285/**
1286 *  @ingroup CPUContext
1287 *  This routine switches from the run context to the heir context.
1288 *
1289 *  @param[in] run points to the context of the currently executing task
1290 *  @param[in] heir points to the context of the heir task
1291 *
1292 *  Port Specific Information:
1293 *
1294 *  XXX document implementation including references if appropriate
1295 */
1296void _CPU_Context_switch(
1297  Context_Control  *run,
1298  Context_Control  *heir
1299);
1300
1301/**
1302 *  @ingroup CPUContext
1303 *  This routine is generally used only to restart self in an
1304 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1305 *
1306 *  @param[in] new_context points to the context to be restored.
1307 *
1308 *  @note May be unnecessary to reload some registers.
1309 *
1310 *  Port Specific Information:
1311 *
1312 *  XXX document implementation including references if appropriate
1313 */
1314void _CPU_Context_restore(
1315  Context_Control *new_context
1316);
1317
1318/**
1319 *  @ingroup CPUContext
1320 *  This routine saves the floating point context passed to it.
1321 *
1322 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1323 *  point context area
1324 *
1325 *  @return on output @a *fp_context_ptr will contain the address that
1326 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1327 *
1328 *  Port Specific Information:
1329 *
1330 *  XXX document implementation including references if appropriate
1331 */
1332void _CPU_Context_save_fp(
1333  void **fp_context_ptr
1334);
1335
1336/**
1337 *  @ingroup CPUContext
1338 *  This routine restores the floating point context passed to it.
1339 *
1340 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1341 *  point context area to restore
1342 *
1343 *  @return on output @a *fp_context_ptr will contain the address that
1344 *  should be used with @ref _CPU_Context_save_fp to save this context.
1345 *
1346 *  Port Specific Information:
1347 *
1348 *  XXX document implementation including references if appropriate
1349 */
1350void _CPU_Context_restore_fp(
1351  void **fp_context_ptr
1352);
1353
1354/**
1355 *  @ingroup CPUEndian
1356 *  The following routine swaps the endian format of an unsigned int.
1357 *  It must be static because it is referenced indirectly.
1358 *
1359 *  This version will work on any processor, but if there is a better
1360 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1361 *
1362 *     swap least significant two bytes with 16-bit rotate
1363 *     swap upper and lower 16-bits
1364 *     swap most significant two bytes with 16-bit rotate
1365 *
1366 *  Some CPUs have special instructions which swap a 32-bit quantity in
1367 *  a single instruction (e.g. i486).  It is probably best to avoid
1368 *  an "endian swapping control bit" in the CPU.  One good reason is
1369 *  that interrupts would probably have to be disabled to ensure that
1370 *  an interrupt does not try to access the same "chunk" with the wrong
1371 *  endian.  Another good reason is that on some CPUs, the endian bit
1372 *  endianness for ALL fetches -- both code and data -- so the code
1373 *  will be fetched incorrectly.
1374 *
1375 *  @param[in] value is the value to be swapped
1376 *  @return the value after being endian swapped
1377 *
1378 *  Port Specific Information:
1379 *
1380 *  XXX document implementation including references if appropriate
1381 */
1382static inline uint32_t CPU_swap_u32(
1383  uint32_t value
1384)
1385{
1386  uint32_t   byte1, byte2, byte3, byte4, swapped;
1387 
1388  byte4 = (value >> 24) & 0xff;
1389  byte3 = (value >> 16) & 0xff;
1390  byte2 = (value >> 8)  & 0xff;
1391  byte1 =  value        & 0xff;
1392 
1393  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1394  return( swapped );
1395}
1396
1397/**
1398 *  @ingroup CPUEndian
1399 *  This routine swaps a 16 bir quantity.
1400 *
1401 *  @param[in] value is the value to be swapped
1402 *  @return the value after being endian swapped
1403 */
1404#define CPU_swap_u16( value ) \
1405  (((value&0xff) << 8) | ((value >> 8)&0xff))
1406
1407#ifdef __cplusplus
1408}
1409#endif
1410
1411#endif
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