1 | /* bfin.h |
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2 | * |
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3 | * This file defines Macros for MMR register common to all Blackfin |
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4 | * Processors. |
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5 | * |
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6 | * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. |
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7 | * modified by Alain Schaefer <alain.schaefer@easc.ch> |
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8 | * and Antonio Giovanini <antonio@atos.com.br> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * $Id$ |
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15 | * |
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16 | */ |
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17 | |
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18 | #ifndef _RTEMS_BFIN_BFIN_H |
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19 | #define _RTEMS_BFIN_BFIN_H |
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20 | |
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21 | #ifdef __cplusplus |
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22 | extern "C" { |
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23 | #endif |
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24 | |
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25 | /* Scratchpad SRAM */ |
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26 | |
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27 | #define SCRATCH 0xFFB00000 |
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28 | #define SCRATCH_SIZE 0x1000 |
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29 | #define SCRATCH_TOP 0xFFB00ffc |
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30 | |
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31 | |
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32 | /* System Interrupt Controller Chapter 4*/ |
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33 | #define SIC_RVECT 0xFFC00108 |
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34 | #define SIC_IMASK 0xFFC0010C |
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35 | #define SIC_IAR0 0xFFC00110 |
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36 | #define SIC_IAR1 0xFFC00114 |
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37 | #define SIC_IAR2 0xFFC00118 |
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38 | #define SIC_ISR 0xFFC00120 |
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39 | #define SIC_IWR 0xFFC00124 |
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40 | |
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41 | /* Event Vector Table Chapter 4 */ |
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42 | |
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43 | #define EVT0 0xFFE02000 |
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44 | #define EVT1 0xFFE02004 |
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45 | #define EVT2 0xFFE02008 |
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46 | #define EVT3 0xFFE0200C |
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47 | #define EVT4 0xFFE02010 |
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48 | #define EVT5 0xFFE02014 |
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49 | #define EVT6 0xFFE02018 |
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50 | #define EVT7 0xFFE0201C |
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51 | #define EVT8 0xFFE02020 |
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52 | #define EVT9 0xFFE02024 |
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53 | #define EVT10 0xFFE02028 |
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54 | #define EVT11 0xFFE0202C |
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55 | #define EVT12 0xFFE02030 |
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56 | #define EVT13 0xFFE02034 |
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57 | #define EVT14 0xFFE02038 |
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58 | #define EVT15 0xFFE0203C |
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59 | #define IMASK 0xFFE02104 |
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60 | #define IPEND 0xFFE02108 |
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61 | #define ILAT 0xFFE0210C |
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62 | #define IPRIO 0xFFE02110 |
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63 | |
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64 | |
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65 | #define TCNTL 0xFFE03000 |
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66 | #define TPERIOD 0xFFE03004 |
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67 | #define TSCALE 0xFFE03008 |
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68 | #define TCOUNT 0xFFE0300C |
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69 | |
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70 | /* Masks for Timer Control */ |
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71 | #define TMPWR 0x00000001 |
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72 | #define TMREN 0x00000002 |
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73 | #define TAUTORLD 0x00000004 |
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74 | #define TINT 0x00000008 |
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75 | |
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76 | /* Event Bit Positions */ |
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77 | #define EVT_IVTMR_P 0x00000006 |
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78 | |
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79 | #define EVT_IVTMR (1 << EVT_IVTMR_P) |
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80 | |
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81 | #ifdef __cplusplus |
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82 | } |
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83 | #endif |
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84 | |
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85 | #endif /* _RTEMS_SCORE_BFIN_H */ |
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