source: rtems/cpukit/score/cpu/bfin/rtems/bfin/bfin.h @ 9b4422a2

4.115
Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.
  • Property mode set to 100644
File size: 2.4 KB
Line 
1/*  bfin.h
2 *
3 *  This file defines Macros for MMR register common to all Blackfin
4 *  Processors.
5 *
6 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
7 *             modified by Alain Schaefer <alain.schaefer@easc.ch>
8 *                     and Antonio Giovanini <antonio@atos.com.br>
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.rtems.com/license/LICENSE.
13 *
14 */
15
16#ifndef _RTEMS_BFIN_BFIN_H
17#define _RTEMS_BFIN_BFIN_H
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/* Scratchpad SRAM */
24
25#define SCRATCH                0xFFB00000
26#define SCRATCH_SIZE           0x1000
27#define SCRATCH_TOP            0xFFB00ffc
28
29
30/* System Interrupt Controller Chapter 4*/
31#define SIC_RVECT              0xFFC00108
32#define SIC_IMASK              0xFFC0010C
33#define SIC_IAR0               0xFFC00110
34#define SIC_IAR1               0xFFC00114
35#define SIC_IAR2               0xFFC00118
36#define SIC_ISR                0xFFC00120
37#define SIC_IWR                0xFFC00124
38
39/* Event Vector Table        Chapter 4 */
40
41#define EVT0                   0xFFE02000
42#define EVT1                   0xFFE02004
43#define EVT2                   0xFFE02008
44#define EVT3                   0xFFE0200C
45#define EVT4                   0xFFE02010
46#define EVT5                   0xFFE02014
47#define EVT6                   0xFFE02018
48#define EVT7                   0xFFE0201C
49#define EVT8                   0xFFE02020
50#define EVT9                   0xFFE02024
51#define EVT10                  0xFFE02028
52#define EVT11                  0xFFE0202C
53#define EVT12                  0xFFE02030
54#define EVT13                  0xFFE02034
55#define EVT14                  0xFFE02038
56#define EVT15                  0xFFE0203C
57#define IMASK                  0xFFE02104
58#define IPEND                  0xFFE02108
59#define ILAT                   0xFFE0210C
60#define IPRIO                  0xFFE02110
61
62
63#define TCNTL                  0xFFE03000
64#define TPERIOD                0xFFE03004
65#define TSCALE                 0xFFE03008
66#define TCOUNT                 0xFFE0300C
67
68/* Masks for Timer Control */
69#define TMPWR                  0x00000001
70#define TMREN                  0x00000002
71#define TAUTORLD               0x00000004
72#define TINT                   0x00000008
73
74/* Event Bit Positions */
75#define EVT_IVTMR_P            0x00000006
76
77#define EVT_IVTMR              (1 << EVT_IVTMR_P)
78
79#ifdef __cplusplus
80}
81#endif
82
83#endif /* _RTEMS_SCORE_BFIN_H */
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