source: rtems/cpukit/score/cpu/bfin/irq.c @ 899b4f62

4.104.114.95
Last change on this file since 899b4f62 was fe834391, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 17, 2007 at 4:12:37 PM

2007-12-17 Joel Sherrill <joel.sherrill@…>

  • cpu.c, irq.c, rtems/score/cpu_asm.h: Sweep to make sure grep for COPYRIGHT passes.
  • Property mode set to 100644
File size: 2.3 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13 
14 
15#include <rtems/system.h>
16#include <rtems/score/cpu.h>
17#include <rtems/score/isr.h>
18#include <rtems/score/thread.h>
19
20/*
21 *  This routine provides the RTEMS interrupt management.
22 */
23
24#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
25  unsigned long    *_old_stack_ptr;
26#endif
27
28register unsigned long  *stack_ptr asm("SP");
29
30void ISR_Handler2(uint32_t   vector, void *isr_sp)
31{
32  register uint32_t   level;
33
34  _CPU_ISR_Disable( level );
35
36  _Thread_Dispatch_disable_level++;
37
38#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
39  if ( _ISR_Nest_level == 0 ) {
40    /* Install irq stack */
41    _old_stack_ptr = stack_ptr;
42    stack_ptr = _CPU_Interrupt_stack_high;
43  }
44#endif
45
46  _ISR_Nest_level++;
47
48  /* leave it to the ISR to decide if they get reenabled */
49  _CPU_ISR_Enable( level );
50
51  /* call isp */
52  if ( _ISR_Vector_table[ vector] )
53    (*_ISR_Vector_table[ vector ])(
54       vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 );
55
56  _CPU_ISR_Disable( level );
57
58  _ISR_Nest_level--;
59
60#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
61  if ( _ISR_Nest_level == 0 )       /* restore old stack pointer */
62    stack_ptr = _old_stack_ptr;
63#endif
64
65  _Thread_Dispatch_disable_level--;
66
67  _CPU_ISR_Enable( level );
68
69  if ( _ISR_Nest_level )
70    return;
71
72  if ( _Thread_Dispatch_disable_level ) {
73    _ISR_Signals_to_thread_executing = FALSE;
74    return;
75  }
76
77  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
78    _ISR_Signals_to_thread_executing = FALSE;
79    _ISR_Thread_Dispatch();
80    /*_Thread_Running->Registers.register_rets = current_thread_pc;*/
81  }
82}
83
84uint32_t SIC_IAR_Value ( uint8_t Vector )
85{
86  switch ( Vector ){
87    case 7:
88      return 0x00000000;
89    case 8:
90      return 0x11111111;
91    case 9:
92      return 0x22222222;
93    case 10:
94      return 0x33333333;
95    case 11:
96      return 0x44444444;
97    case 12:
98      return 0x55555555;
99    case 13:
100      return 0x66666666;
101    case 14:
102      return 0x77777777;
103    case 15:
104      return 0x88888888;
105  }
106}
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