1 | /* Blackfin CPU Dependent Source |
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2 | * |
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3 | * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. |
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4 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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5 | * and Antonio Giovanini <antonio@atos.com.br> |
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6 | * |
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7 | * The license and distribution terms for this file may be |
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8 | * found in the file LICENSE in this distribution or at |
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9 | * http://www.rtems.com/license/LICENSE. |
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10 | * |
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11 | * $Id$ |
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12 | */ |
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13 | |
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14 | |
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15 | #if 0 /* this file no longer used */ |
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16 | |
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17 | #include <rtems/system.h> |
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18 | #include <rtems/score/cpu.h> |
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19 | #include <rtems/score/isr.h> |
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20 | #include <rtems/score/thread.h> |
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21 | |
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22 | /* |
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23 | * This routine provides the RTEMS interrupt management. |
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24 | */ |
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25 | |
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26 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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27 | unsigned long *_old_stack_ptr; |
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28 | #endif |
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29 | |
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30 | register unsigned long *stack_ptr asm("SP"); |
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31 | |
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32 | void ISR_Handler2(uint32_t vector, void *isr_sp) |
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33 | { |
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34 | register uint32_t level; |
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35 | |
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36 | _CPU_ISR_Disable( level ); |
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37 | |
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38 | _Thread_Dispatch_disable_level++; |
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39 | |
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40 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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41 | if ( _ISR_Nest_level == 0 ) { |
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42 | /* Install irq stack */ |
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43 | _old_stack_ptr = stack_ptr; |
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44 | stack_ptr = _CPU_Interrupt_stack_high; |
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45 | } |
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46 | #endif |
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47 | |
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48 | _ISR_Nest_level++; |
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49 | |
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50 | /* leave it to the ISR to decide if they get reenabled */ |
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51 | _CPU_ISR_Enable( level ); |
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52 | |
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53 | /* call isp */ |
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54 | if ( _ISR_Vector_table[ vector] ) |
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55 | (*_ISR_Vector_table[ vector ])( |
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56 | vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 ); |
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57 | |
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58 | _CPU_ISR_Disable( level ); |
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59 | |
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60 | _ISR_Nest_level--; |
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61 | |
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62 | #if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) |
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63 | if ( _ISR_Nest_level == 0 ) /* restore old stack pointer */ |
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64 | stack_ptr = _old_stack_ptr; |
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65 | #endif |
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66 | |
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67 | _Thread_Dispatch_disable_level--; |
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68 | |
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69 | _CPU_ISR_Enable( level ); |
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70 | |
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71 | if ( _ISR_Nest_level ) |
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72 | return; |
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73 | |
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74 | if ( _Thread_Dispatch_disable_level ) { |
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75 | _ISR_Signals_to_thread_executing = FALSE; |
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76 | return; |
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77 | } |
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78 | |
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79 | if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) { |
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80 | _ISR_Signals_to_thread_executing = FALSE; |
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81 | _ISR_Thread_Dispatch(); |
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82 | /*_Thread_Running->Registers.register_rets = current_thread_pc;*/ |
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83 | } |
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84 | } |
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85 | |
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86 | uint32_t SIC_IAR_Value ( uint8_t Vector ) |
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87 | { |
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88 | switch ( Vector ){ |
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89 | case 7: |
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90 | return 0x00000000; |
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91 | case 8: |
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92 | return 0x11111111; |
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93 | case 9: |
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94 | return 0x22222222; |
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95 | case 10: |
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96 | return 0x33333333; |
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97 | case 11: |
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98 | return 0x44444444; |
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99 | case 12: |
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100 | return 0x55555555; |
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101 | case 13: |
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102 | return 0x66666666; |
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103 | case 14: |
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104 | return 0x77777777; |
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105 | case 15: |
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106 | return 0x88888888; |
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107 | } |
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108 | } |
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109 | |
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110 | #endif /* 0 */ |
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111 | |
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