source: rtems/cpukit/score/cpu/bfin/include/rtems/score/cpu.h @ 27bbc05

Last change on this file since 27bbc05 was 27bbc05, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2018 at 12:49:01 PM

score: Remove CPU_PARTITION_ALIGNMENT

Use the CPU_SIZEOF_POINTER alignment instead. The internal alignment
requirement is defined by the use of Chain_Node (consisting of two
pointers) to manage the free chain of partitions.

It seems that previously the condition

CPU_PARTITION_ALIGNMENT >= sizeof(Chain_Node)

was true on all CPU ports. Now, we need an additional check.

Update #3482.

  • Property mode set to 100644
File size: 26.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief Blackfin CPU Department Source
5 *
6 * This include file contains information pertaining to the Blackfin
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *  adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
14 *                     and Antonio Giovanini <antonio@atos.com.br>
15 *
16 *  The license and distribution terms for this file may be
17 *  found in the file LICENSE in this distribution or at
18 *  http://www.rtems.org/license/LICENSE.
19 */
20
21#ifndef _RTEMS_SCORE_CPU_H
22#define _RTEMS_SCORE_CPU_H
23
24#ifdef __cplusplus
25extern "C" {
26#endif
27
28#include <rtems/score/basedefs.h>
29#include <rtems/score/bfin.h>
30
31/* conditional compilation parameters */
32
33/*
34 *  Does the CPU follow the simple vectored interrupt model?
35 *
36 *  If TRUE, then RTEMS allocates the vector table it internally manages.
37 *  If FALSE, then the BSP is assumed to allocate and manage the vector
38 *  table
39 *
40 *  BFIN Specific Information:
41 *
42 *  XXX document implementation including references if appropriate
43 */
44#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
45
46/**
47 * Does the RTEMS invoke the user's ISR with the vector number and
48 * a pointer to the saved interrupt frame (1) or just the vector
49 * number (0)?
50 *
51 * Port Specific Information:
52 *
53 * XXX document implementation including references if appropriate
54 */
55#define CPU_ISR_PASSES_FRAME_POINTER TRUE
56
57/**
58 * @def CPU_HARDWARE_FP
59 *
60 * Does the CPU have hardware floating point?
61 *
62 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
63 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
64 *
65 * If there is a FP coprocessor such as the i387 or mc68881, then
66 * the answer is TRUE.
67 *
68 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
69 * It indicates whether or not this CPU model has FP support.  For
70 * example, it would be possible to have an i386_nofp CPU model
71 * which set this to false to indicate that you have an i386 without
72 * an i387 and wish to leave floating point support out of RTEMS.
73 */
74
75/**
76 * @def CPU_SOFTWARE_FP
77 *
78 * Does the CPU have no hardware floating point and GCC provides a
79 * software floating point implementation which must be context
80 * switched?
81 *
82 * This feature conditional is used to indicate whether or not there
83 * is software implemented floating point that must be context
84 * switched.  The determination of whether or not this applies
85 * is very tool specific and the state saved/restored is also
86 * compiler specific.
87 *
88 * Port Specific Information:
89 *
90 * XXX document implementation including references if appropriate
91 */
92#if ( BLACKFIN_CPU_HAS_FPU == 1 )
93#define CPU_HARDWARE_FP     TRUE
94#else
95#define CPU_HARDWARE_FP     FALSE
96#endif
97#define CPU_SOFTWARE_FP     FALSE
98
99/**
100 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
101 *
102 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
103 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
104 *
105 * So far, the only CPUs in which this option has been used are the
106 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
107 * gcc both implicitly used the floating point registers to perform
108 * integer multiplies.  Similarly, the PowerPC port of gcc has been
109 * seen to allocate floating point local variables and touch the FPU
110 * even when the flow through a subroutine (like vfprintf()) might
111 * not use floating point formats.
112 *
113 * If a function which you would not think utilize the FP unit DOES,
114 * then one can not easily predict which tasks will use the FP hardware.
115 * In this case, this option should be TRUE.
116 *
117 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
118 *
119 * Port Specific Information:
120 *
121 * XXX document implementation including references if appropriate
122 */
123#define CPU_ALL_TASKS_ARE_FP     FALSE
124
125/**
126 * Should the IDLE task have a floating point context?
127 *
128 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
129 * and it has a floating point context which is switched in and out.
130 * If FALSE, then the IDLE task does not have a floating point context.
131 *
132 * Setting this to TRUE negatively impacts the time required to preempt
133 * the IDLE task from an interrupt because the floating point context
134 * must be saved as part of the preemption.
135 *
136 * Port Specific Information:
137 *
138 * XXX document implementation including references if appropriate
139 */
140#define CPU_IDLE_TASK_IS_FP      FALSE
141
142/**
143 * Should the saving of the floating point registers be deferred
144 * until a context switch is made to another different floating point
145 * task?
146 *
147 * If TRUE, then the floating point context will not be stored until
148 * necessary.  It will remain in the floating point registers and not
149 * disturned until another floating point task is switched to.
150 *
151 * If FALSE, then the floating point context is saved when a floating
152 * point task is switched out and restored when the next floating point
153 * task is restored.  The state of the floating point registers between
154 * those two operations is not specified.
155 *
156 * If the floating point context does NOT have to be saved as part of
157 * interrupt dispatching, then it should be safe to set this to TRUE.
158 *
159 * Setting this flag to TRUE results in using a different algorithm
160 * for deciding when to save and restore the floating point context.
161 * The deferred FP switch algorithm minimizes the number of times
162 * the FP context is saved and restored.  The FP context is not saved
163 * until a context switch is made to another, different FP task.
164 * Thus in a system with only one FP task, the FP context will never
165 * be saved or restored.
166 *
167 * Port Specific Information:
168 *
169 * XXX document implementation including references if appropriate
170 */
171#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
172
173#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
174
175/**
176 * Does this port provide a CPU dependent IDLE task implementation?
177 *
178 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
179 * must be provided and is the default IDLE thread body instead of
180 * @ref _CPU_Thread_Idle_body.
181 *
182 * If FALSE, then use the generic IDLE thread body if the BSP does
183 * not provide one.
184 *
185 * This is intended to allow for supporting processors which have
186 * a low power or idle mode.  When the IDLE thread is executed, then
187 * the CPU can be powered down.
188 *
189 * The order of precedence for selecting the IDLE thread body is:
190 *
191 *   -#  BSP provided
192 *   -#  CPU dependent (if provided)
193 *   -#  generic (if no BSP and no CPU dependent)
194 *
195 * Port Specific Information:
196 *
197 * XXX document implementation including references if appropriate
198 */
199#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
200
201/**
202 * Does the stack grow up (toward higher addresses) or down
203 * (toward lower addresses)?
204 *
205 * If TRUE, then the grows upward.
206 * If FALSE, then the grows toward smaller addresses.
207 *
208 * Port Specific Information:
209 *
210 * XXX document implementation including references if appropriate
211 */
212#define CPU_STACK_GROWS_UP               FALSE
213
214/* FIXME: Is this the right value? */
215#define CPU_CACHE_LINE_BYTES 32
216
217#define CPU_STRUCTURE_ALIGNMENT
218
219/**
220 * @ingroup CPUInterrupt
221 * The following defines the number of bits actually used in the
222 * interrupt field of the task mode.  How those bits map to the
223 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
224 *
225 * Port Specific Information:
226 *
227 * XXX document implementation including references if appropriate
228 */
229#define CPU_MODES_INTERRUPT_MASK   0x00000001
230
231#define CPU_MAXIMUM_PROCESSORS 32
232
233/*
234 *  Processor defined structures required for cpukit/score.
235 *
236 *  Port Specific Information:
237 *
238 *  XXX document implementation including references if appropriate
239 */
240
241/* may need to put some structures here.  */
242
243#ifndef ASM
244
245/**
246 * @defgroup CPUContext Processor Dependent Context Management
247 *
248 * From the highest level viewpoint, there are 2 types of context to save.
249 *
250 *    -# Interrupt registers to save
251 *    -# Task level registers to save
252 *
253 * Since RTEMS handles integer and floating point contexts separately, this
254 * means we have the following 3 context items:
255 *
256 *    -# task level context stuff::  Context_Control
257 *    -# floating point task stuff:: Context_Control_fp
258 *    -# special interrupt level context :: CPU_Interrupt_frame
259 *
260 * On some processors, it is cost-effective to save only the callee
261 * preserved registers during a task context switch.  This means
262 * that the ISR code needs to save those registers which do not
263 * persist across function calls.  It is not mandatory to make this
264 * distinctions between the caller/callee saves registers for the
265 * purpose of minimizing context saved during task switch and on interrupts.
266 * If the cost of saving extra registers is minimal, simplicity is the
267 * choice.  Save the same context on interrupt entry as for tasks in
268 * this case.
269 *
270 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
271 * care should be used in designing the context area.
272 *
273 * On some CPUs with hardware floating point support, the Context_Control_fp
274 * structure will not be used or it simply consist of an array of a
275 * fixed number of bytes.   This is done when the floating point context
276 * is dumped by a "FP save context" type instruction and the format
277 * is not really defined by the CPU.  In this case, there is no need
278 * to figure out the exact format -- only the size.  Of course, although
279 * this is enough information for RTEMS, it is probably not enough for
280 * a debugger such as gdb.  But that is another problem.
281 *
282 * Port Specific Information:
283 *
284 * XXX document implementation including references if appropriate
285 */
286/**@{**/
287
288/**
289 * This defines the minimal set of integer and processor state registers
290 * that must be saved during a voluntary context switch from one thread
291 * to another.
292 */
293
294/* make sure this stays in sync with the assembly function
295   __CPU_Context_switch in cpu_asm.S  */
296typedef struct {
297    uint32_t   register_r4;
298    uint32_t   register_r5;
299    uint32_t   register_r6;
300    uint32_t   register_r7;
301
302    uint32_t   register_p3;
303    uint32_t   register_p4;
304    uint32_t   register_p5;
305    uint32_t   register_fp;
306    uint32_t   register_sp;
307
308    uint32_t   register_rets;
309
310    uint32_t   imask;
311} Context_Control;
312
313#define _CPU_Context_Get_SP( _context ) \
314  (_context)->register_sp
315
316/**
317 * This defines the complete set of floating point registers that must
318 * be saved during any context switch from one thread to another.
319 */
320typedef struct {
321    /* FPU registers are listed here */
322    /* Blackfin has no Floating Point */
323} Context_Control_fp;
324
325/**
326 * This defines the set of integer and processor state registers that must
327 * be saved during an interrupt.  This set does not include any which are
328 * in @ref Context_Control.
329 */
330typedef struct {
331    /** This field is a hint that a port will have a number of integer
332     * registers that need to be saved when an interrupt occurs or
333     * when a context switch occurs at the end of an ISR.
334     */
335    /*uint32_t   special_interrupt_register;*/
336} CPU_Interrupt_frame;
337
338/** @} */
339
340/**
341 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
342 */
343/**@{**/
344
345/*
346 *  Nothing prevents the porter from declaring more CPU specific variables.
347 *
348 *  Port Specific Information:
349 *
350 *  XXX document implementation including references if appropriate
351 */
352
353/* XXX: if needed, put more variables here */
354
355/**
356 * @ingroup CPUContext
357 * The size of the floating point context area.  On some CPUs this
358 * will not be a "sizeof" because the format of the floating point
359 * area is not defined -- only the size is.  This is usually on
360 * CPUs with a "floating point save context" instruction.
361 *
362 * Port Specific Information:
363 *
364 * XXX document implementation including references if appropriate
365 */
366#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
367
368#endif /* ASM */
369
370/**
371 * Amount of extra stack (above minimum stack size) required by
372 * MPCI receive server thread.  Remember that in a multiprocessor
373 * system this thread must exist and be able to process all directives.
374 *
375 * Port Specific Information:
376 *
377 * XXX document implementation including references if appropriate
378 */
379#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
380
381/**
382 * @ingroup CPUInterrupt
383 * This defines the number of entries in the @ref _ISR_Vector_table managed
384 * by RTEMS.
385 *
386 * Port Specific Information:
387 *
388 * XXX document implementation including references if appropriate
389 */
390#define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
391
392/**
393 * @ingroup CPUInterrupt
394 * This defines the highest interrupt vector number for this port.
395 */
396#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
397
398/**
399 * @ingroup CPUInterrupt
400 * This is defined if the port has a special way to report the ISR nesting
401 * level.  Most ports maintain the variable @a _ISR_Nest_level.
402 */
403#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
404
405/** @} */
406
407/**
408 * @ingroup CPUContext
409 * Should be large enough to run all RTEMS tests.  This ensures
410 * that a "reasonable" small application should not have any problems.
411 *
412 * Port Specific Information:
413 *
414 * XXX document implementation including references if appropriate
415 */
416#define CPU_STACK_MINIMUM_SIZE          (1024*8)
417
418#define CPU_SIZEOF_POINTER 4
419
420/**
421 * CPU's worst alignment requirement for data types on a byte boundary.  This
422 * alignment does not take into account the requirements for the stack.
423 *
424 * Port Specific Information:
425 *
426 * XXX document implementation including references if appropriate
427 */
428#define CPU_ALIGNMENT              8
429
430/**
431 * This number corresponds to the byte alignment requirement for the
432 * heap handler.  This alignment requirement may be stricter than that
433 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
434 * common for the heap to follow the same alignment requirement as
435 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
436 * the heap, then this should be set to @ref CPU_ALIGNMENT.
437 *
438 * @note  This does not have to be a power of 2 although it should be
439 *        a multiple of 2 greater than or equal to 2.  The requirement
440 *        to be a multiple of 2 is because the heap uses the least
441 *        significant field of the front and back flags to indicate
442 *        that a block is in use or free.  So you do not want any odd
443 *        length blocks really putting length data in that bit.
444 *
445 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
446 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
447 *        elements allocated from the heap meet all restrictions.
448 *
449 * Port Specific Information:
450 *
451 * XXX document implementation including references if appropriate
452 */
453#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
454
455/**
456 * This number corresponds to the byte alignment requirement for the
457 * stack.  This alignment requirement may be stricter than that for the
458 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
459 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
460 * set to 0.
461 *
462 * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
463 *
464 * Port Specific Information:
465 *
466 * XXX document implementation including references if appropriate
467 */
468#define CPU_STACK_ALIGNMENT        8
469
470#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
471
472#ifndef ASM
473
474/*
475 *  ISR handler macros
476 */
477
478/**
479 * @addtogroup CPUInterrupt
480 */
481/**@{**/
482
483/**
484 * Support routine to initialize the RTEMS vector table after it is allocated.
485 *
486 * Port Specific Information:
487 *
488 * XXX document implementation including references if appropriate
489 */
490#define _CPU_Initialize_vectors()
491
492/**
493 * Disable all interrupts for an RTEMS critical section.  The previous
494 * level is returned in @a _isr_cookie.
495 *
496 * @param[out] _isr_cookie will contain the previous level cookie
497 *
498 * Port Specific Information:
499 *
500 * XXX document implementation including references if appropriate
501 */
502#define _CPU_ISR_Disable( _level ) \
503  {                                     \
504       __asm__ volatile ("cli %0; csync \n" : "=d" (_level) );     \
505  }
506
507
508/**
509 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
510 * This indicates the end of an RTEMS critical section.  The parameter
511 * @a _isr_cookie is not modified.
512 *
513 * @param[in] _isr_cookie contain the previous level cookie
514 *
515 * Port Specific Information:
516 *
517 * XXX document implementation including references if appropriate
518 */
519#define _CPU_ISR_Enable( _level ) { \
520    __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) );   \
521  }
522
523/**
524 * This temporarily restores the interrupt to @a _isr_cookie before immediately
525 * disabling them again.  This is used to divide long RTEMS critical
526 * sections into two or more parts.  The parameter @a _isr_cookie is not
527 * modified.
528 *
529 * @param[in] _isr_cookie contain the previous level cookie
530 *
531 * Port Specific Information:
532 *
533 * XXX document implementation including references if appropriate
534 */
535#define _CPU_ISR_Flash( _level ) { \
536    __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
537                          : : "d"(_level) : "R0" ); \
538  }
539
540RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
541{
542  return level != 0;
543}
544
545/**
546 * This routine and @ref _CPU_ISR_Get_level
547 * Map the interrupt level in task mode onto the hardware that the CPU
548 * actually provides.  Currently, interrupt levels which do not
549 * map onto the CPU in a generic fashion are undefined.  Someday,
550 * it would be nice if these were "mapped" by the application
551 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
552 * 8 - 255 would be available for bsp/application specific meaning.
553 * This could be used to manage a programmable interrupt controller
554 * via the rtems_task_mode directive.
555 *
556 * Port Specific Information:
557 *
558 * XXX document implementation including references if appropriate
559 */
560#define _CPU_ISR_Set_level( _new_level ) \
561  { \
562    __asm__ __volatile__ ( "sti %0; csync" : : "d"(_new_level ? 0 : 0xffff) ); \
563  }
564
565/**
566 * Return the current interrupt disable level for this task in
567 * the format used by the interrupt level portion of the task mode.
568 *
569 * @note This routine usually must be implemented as a subroutine.
570 *
571 * Port Specific Information:
572 *
573 * XXX document implementation including references if appropriate
574 */
575uint32_t   _CPU_ISR_Get_level( void );
576
577/* end of ISR handler macros */
578
579/** @} */
580
581/* Context handler macros */
582
583/**
584 * @ingroup CPUContext
585 * Initialize the context to a state suitable for starting a
586 * task after a context restore operation.  Generally, this
587 * involves:
588 *
589 *    - setting a starting address
590 *    - preparing the stack
591 *    - preparing the stack and frame pointers
592 *    - setting the proper interrupt level in the context
593 *    - initializing the floating point context
594 *
595 * This routine generally does not set any unnecessary register
596 * in the context.  The state of the "general data" registers is
597 * undefined at task start time.
598 *
599 * @param[in] _the_context is the context structure to be initialized
600 * @param[in] _stack_base is the lowest physical address of this task's stack
601 * @param[in] _size is the size of this task's stack
602 * @param[in] _isr is the interrupt disable level
603 * @param[in] _entry_point is the thread's entry point.  This is
604 *        always @a _Thread_Handler
605 * @param[in] _is_fp is TRUE if the thread is to be a floating
606 *       point thread.  This is typically only used on CPUs where the
607 *       FPU may be easily disabled by software such as on the SPARC
608 *       where the PSR contains an enable FPU bit.
609 * @param[in] tls_area is the thread-local storage (TLS) area
610 *
611 * Port Specific Information:
612 *
613 * See implementation in cpu.c
614 */
615void _CPU_Context_Initialize(
616  Context_Control  *the_context,
617  uint32_t         *stack_base,
618  uint32_t          size,
619  uint32_t          new_level,
620  void             *entry_point,
621  bool              is_fp,
622  void             *tls_area
623);
624
625/**
626 * This routine is responsible for somehow restarting the currently
627 * executing task.  If you are lucky, then all that is necessary
628 * is restoring the context.  Otherwise, there will need to be
629 * a special assembly routine which does something special in this
630 * case.  For many ports, simply adding a label to the restore path
631 * of @ref _CPU_Context_switch will work.  On other ports, it may be
632 * possibly to load a few arguments and jump to the restore path. It will
633 * not work if restarting self conflicts with the stack frame
634 * assumptions of restoring a context.
635 *
636 * Port Specific Information:
637 *
638 * XXX document implementation including references if appropriate
639 */
640#define _CPU_Context_Restart_self( _the_context ) \
641   _CPU_Context_restore( (_the_context) );
642
643#define _CPU_Context_Initialize_fp( _destination ) \
644  memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE );
645
646/* end of Context handler macros */
647
648/* Fatal Error manager macros */
649
650/**
651 * This routine copies _error into a known place -- typically a stack
652 * location or a register, optionally disables interrupts, and
653 * halts/stops the CPU.
654 *
655 * Port Specific Information:
656 *
657 * XXX document implementation including references if appropriate
658 */
659#define _CPU_Fatal_halt( _source, _error ) \
660  { \
661    __asm__ volatile ( "cli R1; \
662                    R1 = %0; \
663                    _halt: \
664                    idle; \
665                    jump _halt;"\
666                    : : "r" (_error) ); \
667  }
668
669/* end of Fatal Error manager macros */
670
671#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
672
673/* functions */
674
675/**
676 * @brief CPU initialize.
677 * This routine performs CPU dependent initialization.
678 *
679 * Port Specific Information:
680 *
681 * XXX document implementation including references if appropriate
682 */
683void _CPU_Initialize(void);
684
685/**
686 * @ingroup CPUInterrupt
687 * This routine installs a "raw" interrupt handler directly into the
688 * processor's vector table.
689 *
690 * @param[in] vector is the vector number
691 * @param[in] new_handler is the raw ISR handler to install
692 * @param[in] old_handler is the previously installed ISR Handler
693 *
694 * Port Specific Information:
695 *
696 * XXX document implementation including references if appropriate
697 */
698void _CPU_ISR_install_raw_handler(
699  uint32_t    vector,
700  proc_ptr    new_handler,
701  proc_ptr   *old_handler
702);
703
704/**
705 * @ingroup CPUInterrupt
706 * This routine installs an interrupt vector.
707 *
708 * @param[in] vector is the vector number
709 * @param[in] new_handler is the RTEMS ISR handler to install
710 * @param[in] old_handler is the previously installed ISR Handler
711 *
712 * Port Specific Information:
713 *
714 * XXX document implementation including references if appropriate
715 */
716void _CPU_ISR_install_vector(
717  uint32_t    vector,
718  proc_ptr    new_handler,
719  proc_ptr   *old_handler
720);
721
722/**
723 * This routine is the CPU dependent IDLE thread body.
724 *
725 * @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
726 *        is TRUE.
727 *
728 * Port Specific Information:
729 *
730 * XXX document implementation including references if appropriate
731 */
732void *_CPU_Thread_Idle_body( uintptr_t ignored );
733
734/**
735 * @addtogroup CPUContext
736 */
737/**@{**/
738
739/**
740 * This routine switches from the run context to the heir context.
741 *
742 * @param[in] run points to the context of the currently executing task
743 * @param[in] heir points to the context of the heir task
744 *
745 * Port Specific Information:
746 *
747 * XXX document implementation including references if appropriate
748 */
749void _CPU_Context_switch(
750  Context_Control  *run,
751  Context_Control  *heir
752);
753
754/**
755 * This routine is generally used only to restart self in an
756 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
757 *
758 * @param[in] new_context points to the context to be restored.
759 *
760 * @note May be unnecessary to reload some registers.
761 *
762 * Port Specific Information:
763 *
764 * XXX document implementation including references if appropriate
765 */
766void _CPU_Context_restore(
767  Context_Control *new_context
768) RTEMS_NO_RETURN;
769
770/**
771 * This routine saves the floating point context passed to it.
772 *
773 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
774 * point context area
775 *
776 * @return on output @a *fp_context_ptr will contain the address that
777 * should be used with @ref _CPU_Context_restore_fp to restore this context.
778 *
779 * Port Specific Information:
780 *
781 * XXX document implementation including references if appropriate
782 */
783void _CPU_Context_save_fp(
784  Context_Control_fp **fp_context_ptr
785);
786
787/**
788 * This routine restores the floating point context passed to it.
789 *
790 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
791 * point context area to restore
792 *
793 * @return on output @a *fp_context_ptr will contain the address that
794 * should be used with @ref _CPU_Context_save_fp to save this context.
795 *
796 * Port Specific Information:
797 *
798 * XXX document implementation including references if appropriate
799 */
800void _CPU_Context_restore_fp(
801  Context_Control_fp **fp_context_ptr
802);
803
804/** @} */
805
806/* FIXME */
807typedef CPU_Interrupt_frame CPU_Exception_frame;
808
809void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
810
811/**
812 * @ingroup CPUEndian
813 * The following routine swaps the endian format of an unsigned int.
814 * It must be static because it is referenced indirectly.
815 *
816 * This version will work on any processor, but if there is a better
817 * way for your CPU PLEASE use it.  The most common way to do this is to:
818 *
819 *    swap least significant two bytes with 16-bit rotate
820 *    swap upper and lower 16-bits
821 *    swap most significant two bytes with 16-bit rotate
822 *
823 * Some CPUs have special instructions which swap a 32-bit quantity in
824 * a single instruction (e.g. i486).  It is probably best to avoid
825 * an "endian swapping control bit" in the CPU.  One good reason is
826 * that interrupts would probably have to be disabled to ensure that
827 * an interrupt does not try to access the same "chunk" with the wrong
828 * endian.  Another good reason is that on some CPUs, the endian bit
829 * endianness for ALL fetches -- both code and data -- so the code
830 * will be fetched incorrectly.
831 *
832 * @param[in] value is the value to be swapped
833 * @return the value after being endian swapped
834 *
835 * Port Specific Information:
836 *
837 * XXX document implementation including references if appropriate
838 */
839static inline uint32_t CPU_swap_u32(
840  uint32_t value
841)
842{
843  uint32_t   byte1, byte2, byte3, byte4, swapped;
844
845  byte4 = (value >> 24) & 0xff;
846  byte3 = (value >> 16) & 0xff;
847  byte2 = (value >> 8)  & 0xff;
848  byte1 =  value        & 0xff;
849
850  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
851  return( swapped );
852}
853
854/**
855 * @ingroup CPUEndian
856 * This routine swaps a 16 bir quantity.
857 *
858 * @param[in] value is the value to be swapped
859 * @return the value after being endian swapped
860 */
861#define CPU_swap_u16( value ) \
862  (((value&0xff) << 8) | ((value >> 8)&0xff))
863
864typedef uint32_t CPU_Counter_ticks;
865
866uint32_t _CPU_Counter_frequency( void );
867
868CPU_Counter_ticks _CPU_Counter_read( void );
869
870static inline CPU_Counter_ticks _CPU_Counter_difference(
871  CPU_Counter_ticks second,
872  CPU_Counter_ticks first
873)
874{
875  return second - first;
876}
877
878/** Type that can store a 32-bit integer or a pointer. */
879typedef uintptr_t CPU_Uint32ptr;
880
881#endif /* ASM */
882
883#ifdef __cplusplus
884}
885#endif
886
887#endif
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