| 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief Basic MMR for the Blackfin 531/532/533 CPU |
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| 5 | * |
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| 6 | * This file defines basic MMR for the Blackfin 531/532/533 CPU. |
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| 7 | * The MMR have been taken from the ADSP-BF533 Blackfin Processor |
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| 8 | * Hardware Reference from Analog Devices. Mentioned Chapters |
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| 9 | * refer to this Documentation. |
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| 10 | * |
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| 11 | * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000â0xFFFF FFFF) |
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| 12 | * and System MMRs (0xFFC0 0000â0xFFE0 0000). The core MMRs are defined |
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| 13 | * in bfin.h which is included. |
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| 14 | */ |
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| 15 | /* |
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| 16 | * COPYRIGHT (c) 2006. |
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| 17 | * Atos Automacao Industrial LTDA. |
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| 18 | * modified by Alain Schaefer <alain.schaefer@easc.ch> |
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| 19 | * and Antonio Giovanini <antonio@atos.com.br> |
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| 20 | * |
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| 21 | * The license and distribution terms for this file may be |
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| 22 | * found in the file LICENSE in this distribution or at |
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| 23 | * http://www.rtems.org/license/LICENSE. |
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| 24 | * |
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| 25 | */ |
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| 26 | |
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| 27 | #ifndef _RTEMS_BFIN_533_H |
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| 28 | #define _RTEMS_BFIN_533_H |
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| 29 | |
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| 30 | #include <rtems/bfin/bfin.h> |
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| 31 | |
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| 32 | #ifdef __cplusplus |
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| 33 | extern "C" { |
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| 34 | #endif |
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| 35 | |
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| 36 | |
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| 37 | /* Clock and System Control Chapter 8 */ |
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| 38 | #define PLL_CTL 0xFFC00000L |
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| 39 | #define PLL_DIV 0xFFC00004L |
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| 40 | #define VR_CTL 0xFFC00008L |
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| 41 | #define PLL_STAT 0xFFC0000CL |
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| 42 | #define PLL_LOCKCNT 0xFFC00010L |
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| 43 | #define SWRST 0xFFC00100L |
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| 44 | #define SYSCR 0xFFC00104L |
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| 45 | |
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| 46 | /* SPI Controller Chapter 10 */ |
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| 47 | #define SPI_CTL 0xFFC00500L |
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| 48 | #define SPI_FLG 0xFFC00504L |
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| 49 | #define SPI_STAT 0xFFC00508L |
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| 50 | #define SPI_TDBR 0xFFC0050CL |
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| 51 | #define SPI_RDBR 0xFFC00510L |
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| 52 | #define SPI_BAUD 0xFFC00514L |
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| 53 | #define SPI_SHADOW 0xFFC00518L |
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| 54 | |
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| 55 | /* SPORT0 Controller */ |
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| 56 | #define SPORT0_TCR1 0xFFC00800L |
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| 57 | #define SPORT0_TCR2 0xFFC00804L |
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| 58 | #define SPORT0_TCLKDIV 0xFFC00808L |
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| 59 | #define SPORT0_TFSDIV 0xFFC0080CL |
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| 60 | #define SPORT0_TX 0xFFC00810L |
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| 61 | #define SPORT0_RX 0xFFC00818L |
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| 62 | #define SPORT0_RCR1 0xFFC00820L |
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| 63 | #define SPORT0_RCR2 0xFFC00824L |
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| 64 | #define SPORT0_RCLKDIV 0xFFC00828L |
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| 65 | #define SPORT0_RFSDIV 0xFFC0082CL |
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| 66 | #define SPORT0_STAT 0xFFC00830L |
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| 67 | #define SPORT0_CHNL 0xFFC00834L |
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| 68 | #define SPORT0_MCMC1 0xFFC00838L |
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| 69 | #define SPORT0_MCMC2 0xFFC0083CL |
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| 70 | #define SPORT0_MTCS0 0xFFC00840L |
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| 71 | #define SPORT0_MTCS1 0xFFC00844L |
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| 72 | #define SPORT0_MTCS2 0xFFC00848L |
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| 73 | #define SPORT0_MTCS3 0xFFC0084CL |
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| 74 | #define SPORT0_MRCS0 0xFFC00850L |
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| 75 | #define SPORT0_MRCS1 0xFFC00854L |
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| 76 | #define SPORT0_MRCS2 0xFFC00858L |
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| 77 | #define SPORT0_MRCS3 0xFFC0085CL |
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| 78 | |
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| 79 | /* Parallel Peripheral Interface (PPI) Chapter 11 */ |
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| 80 | |
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| 81 | #define PPI_CONTROL 0xFFC01000L |
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| 82 | #define PPI_STATUS 0xFFC01004L |
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| 83 | #define PPI_COUNT 0xFFC01008L |
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| 84 | #define PPI_DELAY 0xFFC0100CL |
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| 85 | #define PPI_FRAME 0xFFC01010L |
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| 86 | |
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| 87 | /********* PPI MASKS ***********/ |
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| 88 | /* PPI_CONTROL Masks */ |
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| 89 | #define PORT_EN 0x00000001 |
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| 90 | #define PORT_DIR 0x00000002 |
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| 91 | #define XFR_TYPE 0x0000000C |
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| 92 | #define PORT_CFG 0x00000030 |
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| 93 | #define FLD_SEL 0x00000040 |
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| 94 | #define PACK_EN 0x00000080 |
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| 95 | #define DMA32 0x00000100 |
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| 96 | #define SKIP_EN 0x00000200 |
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| 97 | #define SKIP_EO 0x00000400 |
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| 98 | #define DLENGTH 0x00003800 |
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| 99 | #define DLEN_8 0x0 |
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| 100 | #define DLEN(x) (((x-9) & 0x07) << 11) |
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| 101 | #define POL 0x0000C000 |
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| 102 | |
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| 103 | /* PPI_STATUS Masks */ |
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| 104 | #define FLD 0x00000400 |
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| 105 | #define FT_ERR 0x00000800 |
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| 106 | #define OVR 0x00001000 |
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| 107 | #define UNDR 0x00002000 |
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| 108 | #define ERR_DET 0x00004000 |
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| 109 | #define ERR_NCOR 0x00008000 |
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| 110 | |
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| 111 | /* SPORT1 Controller Chapter 12 */ |
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| 112 | #define SPORT1_TCR1 0xFFC00900L |
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| 113 | #define SPORT1_TCR2 0xFFC00904L |
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| 114 | #define SPORT1_TCLKDIV 0xFFC00908L |
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| 115 | #define SPORT1_TFSDIV 0xFFC0090CL |
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| 116 | #define SPORT1_TX 0xFFC00910L |
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| 117 | #define SPORT1_RX 0xFFC00918L |
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| 118 | #define SPORT1_RCR1 0xFFC00920L |
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| 119 | #define SPORT1_RCR2 0xFFC00924L |
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| 120 | #define SPORT1_RCLKDIV 0xFFC00928L |
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| 121 | #define SPORT1_RFSDIV 0xFFC0092CL |
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| 122 | #define SPORT1_STAT 0xFFC00930L |
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| 123 | #define SPORT1_CHNL 0xFFC00934L |
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| 124 | #define SPORT1_MCMC1 0xFFC00938L |
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| 125 | #define SPORT1_MCMC2 0xFFC0093CL |
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| 126 | #define SPORT1_MTCS0 0xFFC00940L |
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| 127 | #define SPORT1_MTCS1 0xFFC00944L |
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| 128 | #define SPORT1_MTCS2 0xFFC00948L |
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| 129 | #define SPORT1_MTCS3 0xFFC0094CL |
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| 130 | #define SPORT1_MRCS0 0xFFC00950L |
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| 131 | #define SPORT1_MRCS1 0xFFC00954L |
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| 132 | #define SPORT1_MRCS2 0xFFC00958L |
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| 133 | #define SPORT1_MRCS3 0xFFC0095CL |
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| 134 | |
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| 135 | /* SPORTx_TCR1 Masks */ |
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| 136 | #define TSPEN 0x0001 |
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| 137 | #define ITCLK 0x0002 |
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| 138 | #define TDTYPE 0x000C |
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| 139 | #define TLSBIT 0x0010 |
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| 140 | #define ITFS 0x0200 |
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| 141 | #define TFSR 0x0400 |
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| 142 | #define DITFS 0x0800 |
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| 143 | #define LTFS 0x1000 |
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| 144 | #define LATFS 0x2000 |
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| 145 | #define TCKFE 0x4000 |
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| 146 | |
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| 147 | /* SPORTx_TCR2 Masks */ |
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| 148 | #define SLEN 0x001F |
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| 149 | #define TXSE 0x0100 |
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| 150 | #define TSFSE 0x0200 |
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| 151 | #define TRFST 0x0400 |
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| 152 | |
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| 153 | /* SPORTx_RCR1 Masks */ |
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| 154 | #define RSPEN 0x0001 |
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| 155 | #define IRCLK 0x0002 |
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| 156 | #define RDTYPE 0x000C |
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| 157 | #define RULAW 0x0008 |
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| 158 | #define RALAW 0x000C |
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| 159 | #define RLSBIT 0x0010 |
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| 160 | #define IRFS 0x0200 |
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| 161 | #define RFSR 0x0400 |
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| 162 | #define LRFS 0x1000 |
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| 163 | #define LARFS 0x2000 |
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| 164 | #define RCKFE 0x4000 |
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| 165 | |
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| 166 | /* SPORTx_RCR2 Masks */ |
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| 167 | #define SLEN 0x001F |
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| 168 | #define RXSE 0x0100 |
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| 169 | #define RSFSE 0x0200 |
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| 170 | #define RRFST 0x0400 |
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| 171 | |
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| 172 | /* SPORTx_STAT Masks */ |
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| 173 | #define RXNE 0x0001 |
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| 174 | #define RUVF 0x0002 |
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| 175 | #define ROVF 0x0004 |
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| 176 | #define TXF 0x0008 |
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| 177 | #define TUVF 0x0010 |
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| 178 | #define TOVF 0x0020 |
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| 179 | #define TXHRE 0x0040 |
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| 180 | |
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| 181 | /* SPORTx_MCMC1 Masks */ |
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| 182 | #define WSIZE 0x0000F000 |
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| 183 | #define WOFF 0x000003FF |
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| 184 | |
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| 185 | /* SPORTx_MCMC2 Masks */ |
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| 186 | #define MCCRM 0x00000003 |
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| 187 | #define MCDTXPE 0x00000004 |
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| 188 | #define MCDRXPE 0x00000008 |
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| 189 | #define MCMEN 0x00000010 |
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| 190 | #define FSDR 0x00000080 |
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| 191 | #define MFD 0x0000F000 |
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| 192 | |
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| 193 | /* UART Controller Chapter 13 */ |
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| 194 | #define UART_THR 0xFFC00400L |
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| 195 | #define UART_RBR 0xFFC00400L |
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| 196 | #define UART_DLL 0xFFC00400L |
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| 197 | #define UART_IER 0xFFC00404L |
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| 198 | #define UART_DLH 0xFFC00404L |
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| 199 | #define UART_IIR 0xFFC00408L |
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| 200 | #define UART_LCR 0xFFC0040CL |
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| 201 | #define UART_MCR 0xFFC00410L |
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| 202 | #define UART_LSR 0xFFC00414L |
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| 203 | #define UART_SCR 0xFFC0041CL |
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| 204 | #define UART_GCTL 0xFFC00424L |
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| 205 | |
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| 206 | /* |
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| 207 | * UART CONTROLLER MASKS |
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| 208 | */ |
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| 209 | |
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| 210 | /* UART_LCR */ |
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| 211 | #define DLAB 0x80 |
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| 212 | #define SB 0x40 |
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| 213 | #define STP 0x20 |
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| 214 | #define EPS 0x10 |
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| 215 | #define PEN 0x08 |
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| 216 | #define STB 0x04 |
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| 217 | #define WLS(x) ((x-5) & 0x03) |
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| 218 | |
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| 219 | #define DLAB_P 0x07 |
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| 220 | #define SB_P 0x06 |
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| 221 | #define STP_P 0x05 |
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| 222 | #define EPS_P 0x04 |
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| 223 | #define PEN_P 0x03 |
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| 224 | #define STB_P 0x02 |
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| 225 | #define WLS_P1 0x01 |
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| 226 | #define WLS_P0 0x00 |
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| 227 | |
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| 228 | /* UART_MCR */ |
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| 229 | #define LOOP_ENA 0x10 |
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| 230 | #define LOOP_ENA_P 0x04 |
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| 231 | |
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| 232 | /* UART_LSR */ |
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| 233 | #define TEMT 0x40 |
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| 234 | #define THRE 0x20 |
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| 235 | #define BI 0x10 |
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| 236 | #define FE 0x08 |
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| 237 | #define PE 0x04 |
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| 238 | #define OE 0x02 |
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| 239 | #define DR 0x01 |
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| 240 | |
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| 241 | #define TEMP_P 0x06 |
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| 242 | #define THRE_P 0x05 |
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| 243 | #define BI_P 0x04 |
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| 244 | #define FE_P 0x03 |
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| 245 | #define PE_P 0x02 |
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| 246 | #define OE_P 0x01 |
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| 247 | #define DR_P 0x00 |
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| 248 | |
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| 249 | /* UART_IER */ |
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| 250 | #define ELSI 0x04 |
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| 251 | #define ETBEI 0x02 |
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| 252 | #define ERBFI 0x01 |
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| 253 | |
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| 254 | #define ELSI_P 0x02 |
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| 255 | #define ETBEI_P 0x01 |
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| 256 | #define ERBFI_P 0x00 |
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| 257 | |
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| 258 | /* UART_IIR */ |
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| 259 | #define STATUS(x) ((x << 1) & 0x06) |
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| 260 | #define NINT 0x01 |
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| 261 | #define STATUS_P1 0x02 |
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| 262 | #define STATUS_P0 0x01 |
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| 263 | #define NINT_P 0x00 |
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| 264 | |
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| 265 | /* UART_GCTL */ |
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| 266 | #define FFE 0x20 |
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| 267 | #define FPE 0x10 |
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| 268 | #define RPOLC 0x08 |
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| 269 | #define TPOLC 0x04 |
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| 270 | #define IREN 0x02 |
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| 271 | #define UCEN 0x01 |
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| 272 | |
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| 273 | #define FFE_P 0x05 |
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| 274 | #define FPE_P 0x04 |
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| 275 | #define RPOLC_P 0x03 |
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| 276 | #define TPOLC_P 0x02 |
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| 277 | #define IREN_P 0x01 |
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| 278 | #define UCEN_P 0x00 |
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| 279 | |
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| 280 | /* General Purpose IO Chapter 14*/ |
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| 281 | #define FIO_FLAG_D 0xFFC00700L |
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| 282 | #define FIO_FLAG_C 0xFFC00704L |
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| 283 | #define FIO_FLAG_S 0xFFC00708L |
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| 284 | #define FIO_FLAG_T 0xFFC0070CL |
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| 285 | #define FIO_MASKA_D 0xFFC00710L |
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| 286 | #define FIO_MASKA_C 0xFFC00714L |
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| 287 | #define FIO_MASKA_S 0xFFC00718L |
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| 288 | #define FIO_MASKA_T 0xFFC0071CL |
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| 289 | #define FIO_MASKB_D 0xFFC00720L |
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| 290 | #define FIO_MASKB_C 0xFFC00724L |
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| 291 | #define FIO_MASKB_S 0xFFC00728L |
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| 292 | #define FIO_MASKB_T 0xFFC0072CL |
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| 293 | #define FIO_DIR 0xFFC00730L |
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| 294 | #define FIO_POLAR 0xFFC00734L |
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| 295 | #define FIO_EDGE 0xFFC00738L |
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| 296 | #define FIO_BOTH 0xFFC0073CL |
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| 297 | #define FIO_INEN 0xFFC00740L |
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| 298 | |
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| 299 | /* General Purpose IO Masks */ |
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| 300 | #define PF0 0x0001 |
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| 301 | #define PF1 0x0002 |
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| 302 | #define PF2 0x0004 |
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| 303 | #define PF3 0x0008 |
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| 304 | #define PF4 0x0010 |
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| 305 | #define PF5 0x0020 |
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| 306 | #define PF6 0x0040 |
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| 307 | #define PF7 0x0080 |
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| 308 | #define PF8 0x0100 |
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| 309 | #define PF9 0x0200 |
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| 310 | #define PF10 0x0400 |
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| 311 | #define PF11 0x0800 |
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| 312 | #define PF12 0x1000 |
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| 313 | #define PF13 0x2000 |
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| 314 | #define PF14 0x4000 |
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| 315 | #define PF15 0x8000 |
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| 316 | |
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| 317 | |
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| 318 | /* TIMER 0, 1, 2 Chapter 15 */ |
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| 319 | #define TIMER0_CONFIG 0xFFC00600L |
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| 320 | #define TIMER0_COUNTER 0xFFC00604L |
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| 321 | #define TIMER0_PERIOD 0xFFC00608L |
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| 322 | #define TIMER0_WIDTH 0xFFC0060CL |
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| 323 | |
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| 324 | #define TIMER1_CONFIG 0xFFC00610L |
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| 325 | #define TIMER1_COUNTER 0xFFC00614L |
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| 326 | #define TIMER1_PERIOD 0xFFC00618L |
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| 327 | #define TIMER1_WIDTH 0xFFC0061CL |
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| 328 | |
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| 329 | #define TIMER2_CONFIG 0xFFC00620L |
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| 330 | #define TIMER2_COUNTER 0xFFC00624L |
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| 331 | #define TIMER2_PERIOD 0xFFC00628L |
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| 332 | #define TIMER2_WIDTH 0xFFC0062CL |
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| 333 | |
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| 334 | /* |
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| 335 | * These are defined in bsps/bfin/include/bf52x.h. Ensure those definitions |
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| 336 | * are consistent with our expectations. |
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| 337 | #define TIMER_ENABLE 0xFFC00640L |
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| 338 | #define TIMER_DISABLE 0xFFC00644L |
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| 339 | #define TIMER_STATUS 0xFFC00648L |
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| 340 | */ |
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| 341 | #if ((TIMER_ENABLE != 0xFFC00640L) || \ |
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| 342 | (TIMER_DISABLE != 0xFFC00644L) || \ |
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| 343 | (TIMER_STATUS != 0xFFC00648L)) |
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| 344 | #error "Timer register addresses are inconsistent" |
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| 345 | #endif |
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| 346 | |
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| 347 | /* Real Time Clock Chapter 16 */ |
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| 348 | #define RTC_STAT 0xFFC00300L |
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| 349 | #define RTC_ICTL 0xFFC00304L |
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| 350 | #define RTC_ISTAT 0xFFC00308L |
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| 351 | #define RTC_SWCNT 0xFFC0030CL |
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| 352 | #define RTC_ALARM 0xFFC00310L |
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| 353 | #define RTC_FAST 0xFFC00314L |
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| 354 | #define RTC_PREN 0xFFC00314L |
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| 355 | |
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| 356 | /* RTC_FAST Mask (RTC_PREN Mask) */ |
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| 357 | #define ENABLE_PRESCALE 0x00000001 |
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| 358 | #define PREN 0x00000001 |
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| 359 | |
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| 360 | /* Asynchronous Memory Controller EBUI, Chapter 17*/ |
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| 361 | #define EBIU_AMGCTL 0xFFC00A00L |
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| 362 | #define EBIU_AMBCTL0 0xFFC00A04L |
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| 363 | #define EBIU_AMBCTL1 0xFFC00A08L |
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| 364 | |
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| 365 | /* SDRAM Controller External Bus Interface Unit */ |
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| 366 | |
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| 367 | #define EBIU_SDGCTL 0xFFC00A10L |
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| 368 | #define EBIU_SDBCTL 0xFFC00A14L |
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| 369 | #define EBIU_SDRRC 0xFFC00A18L |
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| 370 | #define EBIU_SDSTAT 0xFFC00A1CL |
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| 371 | |
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| 372 | |
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| 373 | |
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| 374 | |
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| 375 | /* DCPLB_DATA and ICPLB_DATA Registers */ |
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| 376 | /*** Bit Positions */ |
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| 377 | #define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */ |
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| 378 | #define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */ |
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| 379 | #define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */ |
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| 380 | /*** Masks */ |
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| 381 | #define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */ |
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| 382 | #define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */ |
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| 383 | #define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */ |
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| 384 | #define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */ |
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| 385 | #define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ |
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| 386 | #define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ |
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| 387 | #define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ |
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| 388 | #define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */ |
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| 389 | #define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */ |
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| 390 | /*** ICPLB_DATA only */ |
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| 391 | #define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */ |
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| 392 | /*** DCPLB_DATA only */ |
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| 393 | #define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */ |
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| 394 | #define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */ |
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| 395 | #define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */ |
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| 396 | #define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes, */ |
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| 397 | /* 1= allocate cache lines on write-through writes. */ |
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| 398 | #define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */ |
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| 399 | |
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| 400 | |
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| 401 | #ifdef __cplusplus |
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| 402 | } |
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| 403 | #endif |
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| 404 | |
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| 405 | #endif /* _RTEMS_SCORE_BFIN_H */ |
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