1 | /* cpu_asm.S |
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2 | * |
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3 | * This file contains the basic algorithms for all assembly code used |
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4 | * in the Blackfin port of RTEMS. These algorithms must be implemented |
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5 | * in assembly language |
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6 | * |
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7 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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8 | * written by Allan Hessenflow <allanh@kallisti.com> |
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9 | * |
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10 | * Based on earlier version: |
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11 | * |
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12 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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13 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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14 | * and Antonio Giovanini <antonio@atos.com.br> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.org/license/LICENSE. |
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19 | */ |
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20 | |
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21 | #ifdef HAVE_CONFIG_H |
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22 | #include "config.h" |
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23 | #endif |
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24 | |
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25 | #include <rtems/asm.h> |
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26 | #include <rtems/score/cpu_asm.h> |
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27 | #include <rtems/score/bfin.h> |
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28 | #include <rtems/bfin/bfin.h> |
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29 | #include <rtems/score/percpu.h> |
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30 | |
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31 | #define LO(con32) ((con32) & 0xFFFF) |
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32 | #define HI(con32) (((con32) >> 16) & 0xFFFF) |
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33 | |
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34 | |
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35 | #if 0 |
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36 | /* some debug routines */ |
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37 | .globl SYM(_CPU_write_char); |
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38 | SYM(_CPU_write_char): |
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39 | p0.h = 0xffc0; |
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40 | p0.l = 0x0400; |
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41 | txWaitLoop: |
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42 | r1 = w[p0 + 0x14]; |
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43 | cc = bittst(r1, 5); |
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44 | if !cc jump txWaitLoop; |
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45 | w[p0 + 0x00] = r0; |
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46 | rts; |
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47 | |
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48 | .globl SYM(_CPU_write_crlf); |
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49 | SYM(_CPU_write_crlf): |
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50 | r0 = '\r'; |
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51 | [--sp] = rets; |
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52 | call SYM(_CPU_write_char); |
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53 | rets = [sp++]; |
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54 | r0 = '\n'; |
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55 | jump SYM(_CPU_write_char); |
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56 | |
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57 | SYM(_CPU_write_space): |
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58 | r0 = ' '; |
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59 | jump SYM(_CPU_write_char); |
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60 | |
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61 | .globl SYM(_CPU_write_nybble); |
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62 | SYM(_CPU_write_nybble:) |
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63 | r1 = 0x0f; |
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64 | r0 = r0 & r1; |
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65 | r0 += '0'; |
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66 | r1 = '9'; |
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67 | cc = r0 <= r1; |
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68 | if cc jump SYM(_CPU_write_char); |
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69 | r0 += 'a' - '0' - 10; |
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70 | jump SYM(_CPU_write_char); |
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71 | |
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72 | .globl SYM(_CPU_write_byte); |
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73 | SYM(_CPU_write_byte): |
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74 | [--sp] = r0; |
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75 | [--sp] = rets; |
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76 | r0 >>= 4; |
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77 | call SYM(_CPU_write_nybble); |
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78 | rets = [sp++]; |
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79 | r0 = [sp++]; |
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80 | jump SYM(_CPU_write_nybble); |
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81 | |
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82 | SYM(_CPU_write_chawmp): |
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83 | [--sp] = r0; |
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84 | [--sp] = rets; |
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85 | r0 >>= 8; |
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86 | call SYM(_CPU_write_byte); |
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87 | rets = [sp++]; |
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88 | r0 = [sp++]; |
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89 | jump SYM(_CPU_write_byte); |
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90 | |
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91 | SYM(_CPU_write_gawble): |
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92 | [--sp] = r0; |
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93 | [--sp] = rets; |
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94 | r0 >>= 16; |
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95 | call SYM(_CPU_write_chawmp); |
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96 | rets = [sp++]; |
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97 | r0 = [sp++]; |
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98 | jump SYM(_CPU_write_chawmp); |
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99 | |
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100 | SYM(_CPU_dump_registers): |
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101 | [--sp] = rets; |
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102 | [--sp] = r0; |
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103 | [--sp] = r1; |
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104 | [--sp] = p0; |
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105 | r0 = [sp + 8]; |
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106 | call SYM(_CPU_write_gawble); |
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107 | call SYM(_CPU_write_space); |
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108 | r0 = [sp + 4]; |
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109 | call SYM(_CPU_write_gawble); |
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110 | call SYM(_CPU_write_space); |
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111 | r0 = r2; |
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112 | call SYM(_CPU_write_gawble); |
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113 | call SYM(_CPU_write_space); |
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114 | r0 = r3; |
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115 | call SYM(_CPU_write_gawble); |
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116 | call SYM(_CPU_write_space); |
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117 | r0 = r4; |
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118 | call SYM(_CPU_write_gawble); |
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119 | call SYM(_CPU_write_space); |
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120 | r0 = r5; |
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121 | call SYM(_CPU_write_gawble); |
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122 | call SYM(_CPU_write_space); |
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123 | r0 = r6; |
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124 | call SYM(_CPU_write_gawble); |
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125 | call SYM(_CPU_write_space); |
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126 | r0 = r7; |
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127 | call SYM(_CPU_write_gawble); |
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128 | call SYM(_CPU_write_crlf); |
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129 | r0 = [sp]; |
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130 | call SYM(_CPU_write_gawble); |
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131 | call SYM(_CPU_write_space); |
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132 | r0 = p1; |
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133 | call SYM(_CPU_write_gawble); |
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134 | call SYM(_CPU_write_space); |
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135 | r0 = p2; |
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136 | call SYM(_CPU_write_gawble); |
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137 | call SYM(_CPU_write_space); |
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138 | r0 = p3; |
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139 | call SYM(_CPU_write_gawble); |
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140 | call SYM(_CPU_write_space); |
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141 | r0 = p4; |
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142 | call SYM(_CPU_write_gawble); |
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143 | call SYM(_CPU_write_space); |
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144 | r0 = p5; |
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145 | call SYM(_CPU_write_gawble); |
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146 | call SYM(_CPU_write_space); |
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147 | r0 = fp; |
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148 | call SYM(_CPU_write_gawble); |
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149 | call SYM(_CPU_write_space); |
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150 | r0 = sp; |
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151 | r0 += 16; |
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152 | call SYM(_CPU_write_gawble); |
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153 | call SYM(_CPU_write_crlf); |
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154 | |
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155 | p0 = [sp++]; |
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156 | r1 = [sp++]; |
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157 | r0 = [sp++]; |
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158 | rets = [sp++]; |
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159 | rts; |
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160 | |
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161 | .globl SYM(_CPU_Exception_handler); |
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162 | SYM(_CPU_Exception_handler): |
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163 | usp = sp; |
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164 | sp.h = 0xffb0; |
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165 | sp.l = 0x1000; |
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166 | [--sp] = (r7:0,p5:0); |
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167 | |
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168 | r0 = 'x'; |
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169 | call SYM(_CPU_write_char); |
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170 | jump hcf; |
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171 | |
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172 | |
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173 | .globl SYM(_CPU_Emulation_handler); |
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174 | SYM(_CPU_Emulation_handler): |
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175 | usp = sp; |
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176 | sp.h = 0xffb0; |
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177 | sp.l = 0x1000; |
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178 | [--sp] = (r7:0,p5:0); |
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179 | |
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180 | r0 = 'e'; |
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181 | call SYM(_CPU_write_char); |
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182 | jump hcf; |
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183 | |
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184 | .globl SYM(_CPU_Reset_handler); |
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185 | SYM(_CPU_Reset_handler): |
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186 | usp = sp; |
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187 | sp.h = 0xffb0; |
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188 | sp.l = 0x1000; |
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189 | [--sp] = (r7:0,p5:0); |
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190 | |
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191 | r0 = 'r'; |
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192 | call SYM(_CPU_write_char); |
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193 | jump hcf; |
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194 | |
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195 | .globl SYM(_CPU_NMI_handler); |
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196 | SYM(_CPU_NMI_handler): |
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197 | usp = sp; |
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198 | sp.h = 0xffb0; |
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199 | sp.l = 0x1000; |
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200 | [--sp] = (r7:0,p5:0); |
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201 | |
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202 | r0 = 'n'; |
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203 | call SYM(_CPU_write_char); |
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204 | jump hcf; |
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205 | |
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206 | .globl SYM(_CPU_Unhandled_Interrupt_handler); |
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207 | SYM(_CPU_Unhandled_Interrupt_handler): |
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208 | usp = sp; |
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209 | sp.h = 0xffb0; |
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210 | sp.l = 0x1000; |
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211 | [--sp] = (r7:0,p5:0); |
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212 | |
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213 | call SYM(_CPU_write_crlf); |
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214 | r0 = 'i'; |
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215 | call SYM(_CPU_write_char); |
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216 | p0.h = HI(IPEND); |
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217 | p0.l = LO(IPEND); |
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218 | r0 = [p0]; |
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219 | call SYM(_CPU_write_chawmp); |
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220 | jump hcf; |
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221 | |
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222 | hcf: |
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223 | idle; |
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224 | jump hcf; |
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225 | |
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226 | #endif |
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227 | |
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228 | |
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229 | /* _CPU_Context_switch |
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230 | * |
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231 | * This routine performs a normal non-FP context switch. |
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232 | * |
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233 | * bfin Specific Information: |
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234 | * |
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235 | * For now we simply save all registers. |
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236 | * |
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237 | */ |
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238 | |
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239 | /* make sure this sequence stays in sync with the definition for |
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240 | Context_Control in rtems/score/cpu.h */ |
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241 | .globl SYM(_CPU_Context_switch) |
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242 | SYM(_CPU_Context_switch): |
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243 | /* Start saving context R0 = current, R1=heir */ |
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244 | p0 = r0; |
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245 | [p0++] = r4; |
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246 | [p0++] = r5; |
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247 | [p0++] = r6; |
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248 | [p0++] = r7; |
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249 | |
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250 | /* save pointer registers */ |
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251 | [p0++] = p3; |
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252 | [p0++] = p4; |
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253 | [p0++] = p5; |
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254 | [p0++] = fp; |
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255 | [p0++] = sp; |
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256 | |
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257 | /* save rets */ |
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258 | r0 = rets; |
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259 | [p0++] = r0; |
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260 | |
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261 | /* save IMASK */ |
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262 | p1.h = HI(IMASK); |
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263 | p1.l = LO(IMASK); |
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264 | r0 = [p1]; |
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265 | [p0++] = r0; |
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266 | |
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267 | p0 = r1; |
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268 | restore: |
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269 | /* restore data registers */ |
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270 | r4 = [p0++]; |
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271 | r5 = [p0++]; |
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272 | r6 = [p0++]; |
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273 | r7 = [p0++]; |
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274 | |
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275 | /* restore pointer registers */ |
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276 | p3 = [p0++]; |
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277 | p4 = [p0++]; |
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278 | p5 = [p0++]; |
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279 | fp = [p0++]; |
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280 | sp = [p0++]; |
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281 | |
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282 | /* restore rets */ |
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283 | r0 = [p0++]; |
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284 | rets = r0; |
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285 | |
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286 | /* restore IMASK */ |
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287 | r0 = [p0++]; |
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288 | p1.h = HI(IMASK); |
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289 | p1.l = LO(IMASK); |
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290 | [p1] = r0; |
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291 | |
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292 | rts; |
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293 | |
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294 | |
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295 | /* |
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296 | * _CPU_Context_restore |
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297 | * |
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298 | * This routine is generally used only to restart self in an |
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299 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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300 | * |
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301 | * NOTE: May be unnecessary to reload some registers. |
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302 | * |
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303 | * Blackfin Specific Information: |
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304 | * |
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305 | * none |
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306 | * |
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307 | */ |
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308 | .globl SYM(_CPU_Context_restore) |
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309 | SYM(_CPU_Context_restore): |
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310 | p0 = r0; |
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311 | jump restore; |
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312 | |
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313 | |
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314 | .globl SYM(_ISR_Handler) |
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315 | SYM(_ISR_Handler): |
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316 | /* all interrupts are disabled at this point */ |
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317 | /* the following few items are pushed onto the task stack for at |
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318 | most one interrupt; nested interrupts will be using the interrupt |
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319 | stack for everything. */ |
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320 | [--sp] = astat; |
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321 | [--sp] = p1; |
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322 | [--sp] = p0; |
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323 | [--sp] = r1; |
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324 | [--sp] = r0; |
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325 | p0.h = ISR_NEST_LEVEL; |
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326 | p0.l = ISR_NEST_LEVEL; |
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327 | r0 = [p0]; |
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328 | r0 += 1; |
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329 | [p0] = r0; |
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330 | cc = r0 <= 1 (iu); |
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331 | if !cc jump noStackSwitch; |
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332 | /* setup interrupt stack */ |
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333 | r0 = sp; |
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334 | p0.h = INTERRUPT_STACK_HIGH; |
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335 | p0.l = INTERRUPT_STACK_HIGH; |
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336 | sp = [p0]; |
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337 | [--sp] = r0; |
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338 | noStackSwitch: |
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339 | /* disable thread dispatch */ |
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340 | p0.h = THREAD_DISPATCH_DISABLE_LEVEL; |
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341 | p0.l = THREAD_DISPATCH_DISABLE_LEVEL; |
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342 | r0 = [p0]; |
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343 | r0 += 1; |
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344 | [p0] = r0; |
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345 | |
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346 | [--sp] = reti; /* interrupts are now enabled */ |
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347 | |
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348 | /* figure out what vector we are */ |
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349 | p0.h = HI(IPEND); |
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350 | p0.l = LO(IPEND); |
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351 | r1 = [p0]; |
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352 | /* we should only get here for events that require RTI to return */ |
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353 | r1 = r1 >> 5; |
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354 | r0 = 4; |
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355 | /* at least one bit must be set, so this loop will exit */ |
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356 | vectorIDLoop: |
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357 | r0 += 1; |
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358 | r1 = rot r1 by -1; |
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359 | if !cc jump vectorIDLoop; |
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360 | |
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361 | [--sp] = r2; |
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362 | p0.h = SYM(_ISR_Vector_table); |
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363 | p0.l = SYM(_ISR_Vector_table); |
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364 | r2 = [p0]; |
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365 | r1 = r0 << 2; |
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366 | r1 = r1 + r2; |
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367 | p0 = r1; |
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368 | p0 = [p0]; |
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369 | cc = p0 == 0; |
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370 | if cc jump noHandler; |
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371 | |
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372 | /* r2, r0, r1, p0, p1, astat are already saved */ |
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373 | [--sp] = a1.x; |
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374 | [--sp] = a1.w; |
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375 | [--sp] = a0.x; |
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376 | [--sp] = a0.w; |
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377 | [--sp] = r3; |
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378 | [--sp] = p3; |
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379 | [--sp] = p2; |
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380 | [--sp] = lc1; |
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381 | [--sp] = lc0; |
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382 | [--sp] = lt1; |
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383 | [--sp] = lt0; |
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384 | [--sp] = lb1; |
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385 | [--sp] = lb0; |
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386 | [--sp] = i3; |
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387 | [--sp] = i2; |
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388 | [--sp] = i1; |
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389 | [--sp] = i0; |
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390 | [--sp] = m3; |
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391 | [--sp] = m2; |
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392 | [--sp] = m1; |
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393 | [--sp] = m0; |
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394 | [--sp] = l3; |
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395 | [--sp] = l2; |
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396 | [--sp] = l1; |
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397 | [--sp] = l0; |
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398 | [--sp] = b3; |
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399 | [--sp] = b2; |
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400 | [--sp] = b1; |
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401 | [--sp] = b0; |
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402 | [--sp] = rets; |
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403 | /* call user isr; r0 = vector number, r1 = frame pointer */ |
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404 | r1 = fp; /* is this really what should be passed here? */ |
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405 | r2 = 0; |
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406 | l0 = r2; |
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407 | l1 = r2; |
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408 | l2 = r2; |
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409 | l3 = r2; |
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410 | sp += -12; /* bizarre abi... */ |
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411 | call (p0); |
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412 | sp += 12; |
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413 | rets = [sp++]; |
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414 | b0 = [sp++]; |
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415 | b1 = [sp++]; |
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416 | b2 = [sp++]; |
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417 | b3 = [sp++]; |
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418 | l0 = [sp++]; |
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419 | l1 = [sp++]; |
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420 | l2 = [sp++]; |
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421 | l3 = [sp++]; |
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422 | m0 = [sp++]; |
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423 | m1 = [sp++]; |
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424 | m2 = [sp++]; |
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425 | m3 = [sp++]; |
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426 | i0 = [sp++]; |
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427 | i1 = [sp++]; |
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428 | i2 = [sp++]; |
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429 | i3 = [sp++]; |
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430 | lb0 = [sp++]; |
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431 | lb1 = [sp++]; |
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432 | lt0 = [sp++]; |
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433 | lt1 = [sp++]; |
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434 | lc0 = [sp++]; |
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435 | lc1 = [sp++]; |
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436 | p2 = [sp++]; |
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437 | p3 = [sp++]; |
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438 | r3 = [sp++]; |
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439 | a0.w = [sp++]; |
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440 | a0.x = [sp++]; |
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441 | a1.w = [sp++]; |
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442 | a1.x = [sp++]; |
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443 | |
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444 | noHandler: |
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445 | r2 = [sp++]; |
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446 | /* this disables interrupts again */ |
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447 | reti = [sp++]; |
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448 | |
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449 | p0.h = ISR_NEST_LEVEL; |
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450 | p0.l = ISR_NEST_LEVEL; |
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451 | r0 = [p0]; |
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452 | r0 += -1; |
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453 | [p0] = r0; |
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454 | cc = r0 == 0; |
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455 | if !cc jump noStackRestore; |
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456 | sp = [sp]; |
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457 | noStackRestore: |
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458 | |
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459 | /* check this stuff to ensure context_switch_necessary and |
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460 | isr_signals_to_thread_executing are being handled appropriately. */ |
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461 | p0.h = THREAD_DISPATCH_DISABLE_LEVEL; |
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462 | p0.l = THREAD_DISPATCH_DISABLE_LEVEL; |
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463 | r0 = [p0]; |
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464 | r0 += -1; |
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465 | [p0] = r0; |
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466 | cc = r0 == 0; |
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467 | if !cc jump noDispatch |
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468 | |
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469 | /* do thread dispatch if necessary */ |
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470 | p0.h = DISPATCH_NEEDED; |
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471 | p0.l = DISPATCH_NEEDED; |
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472 | r0 = B[p0] (Z); |
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473 | cc = r0 == 0; |
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474 | if cc jump noDispatch |
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475 | doDispatch: |
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476 | r0 = 0; |
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477 | B[p0] = r0; |
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478 | raise 15; |
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479 | noDispatch: |
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480 | r0 = [sp++]; |
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481 | r1 = [sp++]; |
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482 | p0 = [sp++]; |
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483 | p1 = [sp++]; |
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484 | astat = [sp++]; |
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485 | rti |
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486 | |
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487 | |
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488 | /* the approach here is for the main interrupt handler, when a dispatch is |
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489 | wanted, to do a "raise 15". when the main interrupt handler does its |
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490 | "rti", the "raise 15" takes effect and we end up here. we can now |
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491 | safely call _Thread_Dispatch, and do an "rti" to get back to the |
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492 | original interrupted function. this does require self-nesting to be |
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493 | enabled; the maximum nest depth is the number of tasks. */ |
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494 | .global SYM(_ISR15_Handler) |
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495 | SYM(_ISR15_Handler): |
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496 | [--sp] = reti; |
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497 | [--sp] = rets; |
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498 | [--sp] = astat; |
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499 | [--sp] = a1.x; |
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500 | [--sp] = a1.w; |
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501 | [--sp] = a0.x; |
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502 | [--sp] = a0.w; |
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503 | [--sp] = r3; |
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504 | [--sp] = r2; |
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505 | [--sp] = r1; |
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506 | [--sp] = r0; |
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507 | [--sp] = p3; |
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508 | [--sp] = p2; |
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509 | [--sp] = p1; |
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510 | [--sp] = p0; |
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511 | [--sp] = lc1; |
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512 | [--sp] = lc0; |
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513 | [--sp] = lt1; |
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514 | [--sp] = lt0; |
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515 | [--sp] = lb1; |
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516 | [--sp] = lb0; |
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517 | [--sp] = i3; |
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518 | [--sp] = i2; |
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519 | [--sp] = i1; |
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520 | [--sp] = i0; |
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521 | [--sp] = m3; |
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522 | [--sp] = m2; |
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523 | [--sp] = m1; |
---|
524 | [--sp] = m0; |
---|
525 | [--sp] = l3; |
---|
526 | [--sp] = l2; |
---|
527 | [--sp] = l1; |
---|
528 | [--sp] = l0; |
---|
529 | [--sp] = b3; |
---|
530 | [--sp] = b2; |
---|
531 | [--sp] = b1; |
---|
532 | [--sp] = b0; |
---|
533 | r2 = 0; |
---|
534 | l0 = r2; |
---|
535 | l1 = r2; |
---|
536 | l2 = r2; |
---|
537 | l3 = r2; |
---|
538 | sp += -12; /* bizarre abi... */ |
---|
539 | call SYM(_Thread_Dispatch); |
---|
540 | sp += 12; |
---|
541 | b0 = [sp++]; |
---|
542 | b1 = [sp++]; |
---|
543 | b2 = [sp++]; |
---|
544 | b3 = [sp++]; |
---|
545 | l0 = [sp++]; |
---|
546 | l1 = [sp++]; |
---|
547 | l2 = [sp++]; |
---|
548 | l3 = [sp++]; |
---|
549 | m0 = [sp++]; |
---|
550 | m1 = [sp++]; |
---|
551 | m2 = [sp++]; |
---|
552 | m3 = [sp++]; |
---|
553 | i0 = [sp++]; |
---|
554 | i1 = [sp++]; |
---|
555 | i2 = [sp++]; |
---|
556 | i3 = [sp++]; |
---|
557 | lb0 = [sp++]; |
---|
558 | lb1 = [sp++]; |
---|
559 | lt0 = [sp++]; |
---|
560 | lt1 = [sp++]; |
---|
561 | lc0 = [sp++]; |
---|
562 | lc1 = [sp++]; |
---|
563 | p0 = [sp++]; |
---|
564 | p1 = [sp++]; |
---|
565 | p2 = [sp++]; |
---|
566 | p3 = [sp++]; |
---|
567 | r0 = [sp++]; |
---|
568 | r1 = [sp++]; |
---|
569 | r2 = [sp++]; |
---|
570 | r3 = [sp++]; |
---|
571 | a0.w = [sp++]; |
---|
572 | a0.x = [sp++]; |
---|
573 | a1.w = [sp++]; |
---|
574 | a1.x = [sp++]; |
---|
575 | astat = [sp++]; |
---|
576 | rets = [sp++]; |
---|
577 | reti = [sp++]; |
---|
578 | rti; |
---|
579 | |
---|