1 | /* cpu_asm.S |
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2 | * |
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3 | * This file contains the basic algorithms for all assembly code used |
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4 | * in the Blackfin port of RTEMS. These algorithms must be implemented |
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5 | * in assembly language |
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6 | * |
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7 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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8 | * written by Allan Hessenflow <allanh@kallisti.com> |
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9 | * |
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10 | * Based on earlier version: |
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11 | * |
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12 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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13 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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14 | * and Antonio Giovanini <antonio@atos.com.br> |
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15 | * |
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16 | * The license and distribution terms for this file may be |
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17 | * found in the file LICENSE in this distribution or at |
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18 | * http://www.rtems.com/license/LICENSE. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #ifdef HAVE_CONFIG_H |
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24 | #include "config.h" |
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25 | #endif |
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26 | |
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27 | #include <rtems/asm.h> |
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28 | #include <rtems/score/cpu_asm.h> |
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29 | #include <rtems/score/bfin.h> |
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30 | #include <rtems/bfin/bfin.h> |
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31 | |
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32 | #define LO(con32) ((con32) & 0xFFFF) |
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33 | #define HI(con32) (((con32) >> 16) & 0xFFFF) |
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34 | |
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35 | |
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36 | #if 0 |
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37 | /* some debug routines */ |
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38 | .globl __CPU_write_char; |
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39 | __CPU_write_char: |
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40 | p0.h = 0xffc0; |
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41 | p0.l = 0x0400; |
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42 | txWaitLoop: |
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43 | r1 = w[p0 + 0x14]; |
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44 | cc = bittst(r1, 5); |
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45 | if !cc jump txWaitLoop; |
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46 | w[p0 + 0x00] = r0; |
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47 | rts; |
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48 | |
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49 | .globl __CPU_write_crlf; |
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50 | __CPU_write_crlf: |
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51 | r0 = '\r'; |
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52 | [--sp] = rets; |
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53 | call __CPU_write_char; |
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54 | rets = [sp++]; |
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55 | r0 = '\n'; |
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56 | jump __CPU_write_char; |
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57 | |
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58 | __CPU_write_space: |
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59 | r0 = ' '; |
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60 | jump __CPU_write_char; |
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61 | |
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62 | .globl __CPU_write_nybble; |
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63 | __CPU_write_nybble: |
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64 | r1 = 0x0f; |
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65 | r0 = r0 & r1; |
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66 | r0 += '0'; |
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67 | r1 = '9'; |
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68 | cc = r0 <= r1; |
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69 | if cc jump __CPU_write_char; |
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70 | r0 += 'a' - '0' - 10; |
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71 | jump __CPU_write_char; |
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72 | |
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73 | .globl __CPU_write_byte; |
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74 | __CPU_write_byte: |
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75 | [--sp] = r0; |
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76 | [--sp] = rets; |
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77 | r0 >>= 4; |
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78 | call __CPU_write_nybble; |
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79 | rets = [sp++]; |
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80 | r0 = [sp++]; |
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81 | jump __CPU_write_nybble; |
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82 | |
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83 | __CPU_write_chawmp: |
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84 | [--sp] = r0; |
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85 | [--sp] = rets; |
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86 | r0 >>= 8; |
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87 | call __CPU_write_byte; |
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88 | rets = [sp++]; |
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89 | r0 = [sp++]; |
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90 | jump __CPU_write_byte; |
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91 | |
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92 | __CPU_write_gawble: |
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93 | [--sp] = r0; |
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94 | [--sp] = rets; |
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95 | r0 >>= 16; |
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96 | call __CPU_write_chawmp; |
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97 | rets = [sp++]; |
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98 | r0 = [sp++]; |
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99 | jump __CPU_write_chawmp; |
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100 | |
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101 | __CPU_dump_registers: |
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102 | [--sp] = rets; |
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103 | [--sp] = r0; |
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104 | [--sp] = r1; |
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105 | [--sp] = p0; |
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106 | r0 = [sp + 8]; |
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107 | call __CPU_write_gawble; |
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108 | call __CPU_write_space; |
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109 | r0 = [sp + 4]; |
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110 | call __CPU_write_gawble; |
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111 | call __CPU_write_space; |
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112 | r0 = r2; |
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113 | call __CPU_write_gawble; |
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114 | call __CPU_write_space; |
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115 | r0 = r3; |
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116 | call __CPU_write_gawble; |
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117 | call __CPU_write_space; |
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118 | r0 = r4; |
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119 | call __CPU_write_gawble; |
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120 | call __CPU_write_space; |
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121 | r0 = r5; |
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122 | call __CPU_write_gawble; |
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123 | call __CPU_write_space; |
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124 | r0 = r6; |
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125 | call __CPU_write_gawble; |
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126 | call __CPU_write_space; |
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127 | r0 = r7; |
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128 | call __CPU_write_gawble; |
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129 | call __CPU_write_crlf; |
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130 | r0 = [sp]; |
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131 | call __CPU_write_gawble; |
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132 | call __CPU_write_space; |
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133 | r0 = p1; |
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134 | call __CPU_write_gawble; |
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135 | call __CPU_write_space; |
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136 | r0 = p2; |
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137 | call __CPU_write_gawble; |
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138 | call __CPU_write_space; |
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139 | r0 = p3; |
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140 | call __CPU_write_gawble; |
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141 | call __CPU_write_space; |
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142 | r0 = p4; |
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143 | call __CPU_write_gawble; |
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144 | call __CPU_write_space; |
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145 | r0 = p5; |
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146 | call __CPU_write_gawble; |
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147 | call __CPU_write_space; |
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148 | r0 = fp; |
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149 | call __CPU_write_gawble; |
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150 | call __CPU_write_space; |
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151 | r0 = sp; |
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152 | r0 += 16; |
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153 | call __CPU_write_gawble; |
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154 | call __CPU_write_crlf; |
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155 | |
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156 | p0 = [sp++]; |
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157 | r1 = [sp++]; |
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158 | r0 = [sp++]; |
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159 | rets = [sp++]; |
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160 | rts; |
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161 | |
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162 | .globl __CPU_Exception_handler; |
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163 | __CPU_Exception_handler: |
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164 | usp = sp; |
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165 | sp.h = 0xffb0; |
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166 | sp.l = 0x1000; |
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167 | [--sp] = (r7:0,p5:0); |
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168 | |
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169 | r0 = 'x'; |
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170 | call __CPU_write_char; |
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171 | jump hcf; |
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172 | |
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173 | |
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174 | .globl __CPU_Emulation_handler; |
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175 | __CPU_Emulation_handler: |
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176 | usp = sp; |
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177 | sp.h = 0xffb0; |
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178 | sp.l = 0x1000; |
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179 | [--sp] = (r7:0,p5:0); |
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180 | |
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181 | r0 = 'e'; |
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182 | call __CPU_write_char; |
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183 | jump hcf; |
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184 | |
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185 | .globl __CPU_Reset_handler; |
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186 | __CPU_Reset_handler: |
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187 | usp = sp; |
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188 | sp.h = 0xffb0; |
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189 | sp.l = 0x1000; |
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190 | [--sp] = (r7:0,p5:0); |
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191 | |
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192 | r0 = 'r'; |
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193 | call __CPU_write_char; |
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194 | jump hcf; |
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195 | |
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196 | .globl __CPU_NMI_handler; |
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197 | __CPU_NMI_handler: |
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198 | usp = sp; |
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199 | sp.h = 0xffb0; |
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200 | sp.l = 0x1000; |
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201 | [--sp] = (r7:0,p5:0); |
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202 | |
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203 | r0 = 'n'; |
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204 | call __CPU_write_char; |
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205 | jump hcf; |
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206 | |
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207 | .globl __CPU_Unhandled_Interrupt_handler; |
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208 | __CPU_Unhandled_Interrupt_handler: |
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209 | usp = sp; |
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210 | sp.h = 0xffb0; |
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211 | sp.l = 0x1000; |
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212 | [--sp] = (r7:0,p5:0); |
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213 | |
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214 | call __CPU_write_crlf; |
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215 | r0 = 'i'; |
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216 | call __CPU_write_char; |
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217 | p0.h = HI(IPEND); |
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218 | p0.l = LO(IPEND); |
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219 | r0 = [p0]; |
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220 | call __CPU_write_chawmp; |
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221 | jump hcf; |
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222 | |
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223 | hcf: |
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224 | idle; |
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225 | jump hcf; |
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226 | |
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227 | #endif |
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228 | |
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229 | |
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230 | /* _CPU_Context_switch |
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231 | * |
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232 | * This routine performs a normal non-FP context switch. |
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233 | * |
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234 | * bfin Specific Information: |
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235 | * |
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236 | * For now we simply save all registers. |
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237 | * |
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238 | */ |
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239 | |
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240 | /* make sure this sequence stays in sync with the definition for |
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241 | Context_Control in rtems/score/cpu.h */ |
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242 | .globl __CPU_Context_switch |
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243 | __CPU_Context_switch: |
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244 | /* Start saving context R0 = current, R1=heir */ |
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245 | p0 = r0; |
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246 | [p0++] = r4; |
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247 | [p0++] = r5; |
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248 | [p0++] = r6; |
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249 | [p0++] = r7; |
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250 | |
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251 | /* save pointer registers */ |
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252 | [p0++] = p3; |
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253 | [p0++] = p4; |
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254 | [p0++] = p5; |
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255 | [p0++] = fp; |
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256 | [p0++] = sp; |
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257 | |
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258 | /* save length registers */ |
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259 | r0 = l0; |
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260 | [p0++] = r0; |
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261 | r0 = l1; |
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262 | [p0++] = r0; |
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263 | r0 = l2; |
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264 | [p0++] = r0; |
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265 | r0 = l3; |
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266 | [p0++] = r0; |
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267 | |
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268 | /* save rets */ |
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269 | r0 = rets; |
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270 | [p0++] = r0; |
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271 | |
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272 | /* save IMASK */ |
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273 | p1.h = HI(IMASK); |
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274 | p1.l = LO(IMASK); |
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275 | r0 = [p1]; |
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276 | [p0++] = r0; |
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277 | |
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278 | p0 = r1; |
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279 | restore: |
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280 | /* restore data registers */ |
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281 | r4 = [p0++]; |
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282 | r5 = [p0++]; |
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283 | r6 = [p0++]; |
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284 | r7 = [p0++]; |
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285 | |
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286 | /* restore pointer registers */ |
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287 | p3 = [p0++]; |
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288 | p4 = [p0++]; |
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289 | p5 = [p0++]; |
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290 | fp = [p0++]; |
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291 | sp = [p0++]; |
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292 | |
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293 | /* restore length registers */ |
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294 | r0 = [p0++]; |
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295 | l0 = r0; |
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296 | r0 = [p0++]; |
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297 | l1 = r0; |
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298 | r0 = [p0++]; |
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299 | l2 = r0; |
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300 | r0 = [p0++]; |
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301 | l3 = r0; |
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302 | |
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303 | /* restore rets */ |
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304 | r0 = [p0++]; |
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305 | rets = r0; |
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306 | |
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307 | /* restore IMASK */ |
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308 | r0 = [p0++]; |
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309 | p1.h = HI(IMASK); |
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310 | p1.l = LO(IMASK); |
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311 | [p1] = r0; |
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312 | |
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313 | rts; |
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314 | |
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315 | |
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316 | /* |
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317 | * _CPU_Context_restore |
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318 | * |
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319 | * This routine is generally used only to restart self in an |
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320 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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321 | * |
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322 | * NOTE: May be unnecessary to reload some registers. |
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323 | * |
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324 | * Blackfin Specific Information: |
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325 | * |
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326 | * none |
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327 | * |
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328 | */ |
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329 | .globl __CPU_Context_restore |
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330 | __CPU_Context_restore: |
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331 | p0 = r0; |
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332 | jump restore; |
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333 | |
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334 | |
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335 | .globl __ISR_Handler |
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336 | .extern __CPU_Interrupt_stack_high; |
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337 | .extern __ISR_Nest_level |
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338 | .extern __Thread_Dispatch_disable_level |
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339 | .extern __Context_Switch_necessary |
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340 | .extern __ISR_Signals_to_thread_executing |
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341 | __ISR_Handler: |
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342 | /* all interrupts are disabled at this point */ |
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343 | /* the following few items are pushed onto the task stack for at |
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344 | most one interrupt; nested interrupts will be using the interrupt |
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345 | stack for everything. */ |
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346 | [--sp] = astat; |
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347 | [--sp] = p1; |
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348 | [--sp] = p0; |
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349 | [--sp] = r1; |
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350 | [--sp] = r0; |
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351 | p0.h = __ISR_Nest_level; |
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352 | p0.l = __ISR_Nest_level; |
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353 | r0 = [p0]; |
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354 | r0 += 1; |
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355 | [p0] = r0; |
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356 | cc = r0 <= 1 (iu); |
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357 | if !cc jump noStackSwitch; |
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358 | /* setup interrupt stack */ |
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359 | r0 = sp; |
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360 | p0.h = __CPU_Interrupt_stack_high; |
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361 | p0.l = __CPU_Interrupt_stack_high; |
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362 | sp = [p0]; |
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363 | [--sp] = r0; |
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364 | noStackSwitch: |
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365 | /* disable thread dispatch */ |
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366 | p0.h = __Thread_Dispatch_disable_level; |
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367 | p0.l = __Thread_Dispatch_disable_level; |
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368 | r0 = [p0]; |
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369 | r0 += 1; |
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370 | [p0] = r0; |
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371 | |
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372 | [--sp] = reti; /* interrupts are now enabled */ |
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373 | |
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374 | /* figure out what vector we are */ |
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375 | p0.h = HI(IPEND); |
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376 | p0.l = LO(IPEND); |
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377 | r1 = [p0]; |
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378 | /* we should only get here for events that require RTI to return */ |
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379 | r1 = r1 >> 5; |
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380 | r0 = 4; |
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381 | /* at least one bit must be set, so this loop will exit */ |
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382 | vectorIDLoop: |
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383 | r0 += 1; |
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384 | r1 = rot r1 by -1; |
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385 | if !cc jump vectorIDLoop; |
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386 | |
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387 | [--sp] = r2; |
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388 | p0.h = __ISR_Vector_table; |
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389 | p0.l = __ISR_Vector_table; |
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390 | r2 = [p0]; |
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391 | r1 = r0 << 2; |
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392 | r1 = r1 + r2; |
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393 | p0 = r1; |
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394 | p0 = [p0]; |
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395 | cc = p0 == 0; |
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396 | if cc jump noHandler; |
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397 | |
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398 | /* r2, r0, r1, p0, p1, astat are already saved */ |
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399 | [--sp] = a1.x; |
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400 | [--sp] = a1.w; |
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401 | [--sp] = a0.x; |
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402 | [--sp] = a0.w; |
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403 | [--sp] = r3; |
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404 | [--sp] = p3; |
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405 | [--sp] = p2; |
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406 | [--sp] = lt1; |
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407 | [--sp] = lt0; |
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408 | [--sp] = lc1; |
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409 | [--sp] = lc0; |
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410 | [--sp] = lb1; |
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411 | [--sp] = lb0; |
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412 | [--sp] = i3; |
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413 | [--sp] = i2; |
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414 | [--sp] = i1; |
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415 | [--sp] = i0; |
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416 | [--sp] = m3; |
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417 | [--sp] = m2; |
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418 | [--sp] = m1; |
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419 | [--sp] = m0; |
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420 | [--sp] = l3; |
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421 | [--sp] = l2; |
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422 | [--sp] = l1; |
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423 | [--sp] = l0; |
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424 | [--sp] = b3; |
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425 | [--sp] = b2; |
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426 | [--sp] = b1; |
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427 | [--sp] = b0; |
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428 | [--sp] = rets; |
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429 | r1 = fp; /* is this really what should be passed here? */ |
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430 | /* call user isr; r0 = vector number, r1 = frame pointer */ |
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431 | sp += -12; /* bizarre abi... */ |
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432 | call (p0); |
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433 | sp += 12; |
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434 | rets = [sp++]; |
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435 | b0 = [sp++]; |
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436 | b1 = [sp++]; |
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437 | b2 = [sp++]; |
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438 | b3 = [sp++]; |
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439 | l0 = [sp++]; |
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440 | l1 = [sp++]; |
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441 | l2 = [sp++]; |
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442 | l3 = [sp++]; |
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443 | m0 = [sp++]; |
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444 | m1 = [sp++]; |
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445 | m2 = [sp++]; |
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446 | m3 = [sp++]; |
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447 | i0 = [sp++]; |
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448 | i1 = [sp++]; |
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449 | i2 = [sp++]; |
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450 | i3 = [sp++]; |
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451 | lb0 = [sp++]; |
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452 | lb1 = [sp++]; |
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453 | lc0 = [sp++]; |
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454 | lc1 = [sp++]; |
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455 | lt0 = [sp++]; |
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456 | lt1 = [sp++]; |
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457 | p2 = [sp++]; |
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458 | p3 = [sp++]; |
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459 | r3 = [sp++]; |
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460 | a0.w = [sp++]; |
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461 | a0.x = [sp++]; |
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462 | a1.w = [sp++]; |
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463 | a1.x = [sp++]; |
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464 | |
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465 | noHandler: |
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466 | r2 = [sp++]; |
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467 | /* this disables interrupts again */ |
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468 | reti = [sp++]; |
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469 | |
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470 | p0.h = __ISR_Nest_level; |
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471 | p0.l = __ISR_Nest_level; |
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472 | r0 = [p0]; |
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473 | r0 += -1; |
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474 | [p0] = r0; |
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475 | cc = r0 == 0; |
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476 | if !cc jump noStackRestore; |
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477 | sp = [sp]; |
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478 | noStackRestore: |
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479 | |
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480 | /* check this stuff to ensure context_switch_necessary and |
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481 | isr_signals_to_thread_executing are being handled appropriately. */ |
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482 | p0.h = __Thread_Dispatch_disable_level; |
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483 | p0.l = __Thread_Dispatch_disable_level; |
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484 | r0 = [p0]; |
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485 | r0 += -1; |
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486 | [p0] = r0; |
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487 | cc = r0 == 0; |
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488 | if !cc jump noDispatch |
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489 | |
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490 | /* do thread dispatch if necessary */ |
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491 | p0.h = __Context_Switch_necessary; |
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492 | p0.l = __Context_Switch_necessary; |
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493 | r0 = B[p0] (Z); |
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494 | cc = r0 == 0; |
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495 | p0.h = __ISR_Signals_to_thread_executing; |
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496 | p0.l = __ISR_Signals_to_thread_executing; |
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497 | if !cc jump doDispatch |
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498 | r0 = B[p0] (Z); |
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499 | cc = r0 == 0; |
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500 | if cc jump noDispatch |
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501 | doDispatch: |
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502 | r0 = 0; |
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503 | B[p0] = r0; |
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504 | raise 15; |
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505 | noDispatch: |
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506 | r0 = [sp++]; |
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507 | r1 = [sp++]; |
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508 | p0 = [sp++]; |
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509 | p1 = [sp++]; |
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510 | astat = [sp++]; |
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511 | rti |
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512 | |
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513 | |
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514 | /* the approach here is for the main interrupt handler, when a dispatch is |
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515 | wanted, to do a "raise 15". when the main interrupt handler does its |
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516 | "rti", the "raise 15" takes effect and we end up here. we can now |
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517 | safely call _Thread_Dispatch, and do an "rti" to get back to the |
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518 | original interrupted function. this does require self-nesting to be |
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519 | enabled; the maximum nest depth is the number of tasks. */ |
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520 | .global __ISR15_Handler |
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521 | .extern __Thread_Dispatch |
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522 | __ISR15_Handler: |
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523 | [--sp] = reti; |
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524 | [--sp] = rets; |
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525 | [--sp] = astat; |
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526 | [--sp] = a1.x; |
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527 | [--sp] = a1.w; |
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528 | [--sp] = a0.x; |
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529 | [--sp] = a0.w; |
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530 | [--sp] = r3; |
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531 | [--sp] = r2; |
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532 | [--sp] = r1; |
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533 | [--sp] = r0; |
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534 | [--sp] = p3; |
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535 | [--sp] = p2; |
---|
536 | [--sp] = p1; |
---|
537 | [--sp] = p0; |
---|
538 | [--sp] = lt1; |
---|
539 | [--sp] = lt0; |
---|
540 | [--sp] = lc1; |
---|
541 | [--sp] = lc0; |
---|
542 | [--sp] = lb1; |
---|
543 | [--sp] = lb0; |
---|
544 | [--sp] = i3; |
---|
545 | [--sp] = i2; |
---|
546 | [--sp] = i1; |
---|
547 | [--sp] = i0; |
---|
548 | [--sp] = m3; |
---|
549 | [--sp] = m2; |
---|
550 | [--sp] = m1; |
---|
551 | [--sp] = m0; |
---|
552 | [--sp] = l3; |
---|
553 | [--sp] = l2; |
---|
554 | [--sp] = l1; |
---|
555 | [--sp] = l0; |
---|
556 | [--sp] = b3; |
---|
557 | [--sp] = b2; |
---|
558 | [--sp] = b1; |
---|
559 | [--sp] = b0; |
---|
560 | sp += -12; /* bizarre abi... */ |
---|
561 | call __Thread_Dispatch; |
---|
562 | sp += 12; |
---|
563 | b0 = [sp++]; |
---|
564 | b1 = [sp++]; |
---|
565 | b2 = [sp++]; |
---|
566 | b3 = [sp++]; |
---|
567 | l0 = [sp++]; |
---|
568 | l1 = [sp++]; |
---|
569 | l2 = [sp++]; |
---|
570 | l3 = [sp++]; |
---|
571 | m0 = [sp++]; |
---|
572 | m1 = [sp++]; |
---|
573 | m2 = [sp++]; |
---|
574 | m3 = [sp++]; |
---|
575 | i0 = [sp++]; |
---|
576 | i1 = [sp++]; |
---|
577 | i2 = [sp++]; |
---|
578 | i3 = [sp++]; |
---|
579 | lb0 = [sp++]; |
---|
580 | lb1 = [sp++]; |
---|
581 | lc0 = [sp++]; |
---|
582 | lc1 = [sp++]; |
---|
583 | lt0 = [sp++]; |
---|
584 | lt1 = [sp++]; |
---|
585 | p0 = [sp++]; |
---|
586 | p1 = [sp++]; |
---|
587 | p2 = [sp++]; |
---|
588 | p3 = [sp++]; |
---|
589 | r0 = [sp++]; |
---|
590 | r1 = [sp++]; |
---|
591 | r2 = [sp++]; |
---|
592 | r3 = [sp++]; |
---|
593 | a0.w = [sp++]; |
---|
594 | a0.x = [sp++]; |
---|
595 | a1.w = [sp++]; |
---|
596 | a1.x = [sp++]; |
---|
597 | astat = [sp++]; |
---|
598 | rets = [sp++]; |
---|
599 | reti = [sp++]; |
---|
600 | rti; |
---|
601 | |
---|