[d9a6ab3] | 1 | /* cpu_asm.S |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in the Blackfin port of RTEMS. These algorithms must be implemented |
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| 5 | * in assembly language |
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| 6 | * |
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[4daebbd] | 7 | * Copyright (c) 2008 Kallisti Labs, Los Gatos, CA, USA |
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| 8 | * written by Allan Hessenflow <allanh@kallisti.com> |
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| 9 | * |
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| 10 | * Based on earlier version: |
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| 11 | * |
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[d9a6ab3] | 12 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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[4daebbd] | 13 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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| 14 | * and Antonio Giovanini <antonio@atos.com.br> |
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[d9a6ab3] | 15 | * |
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| 16 | * The license and distribution terms for this file may be |
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| 17 | * found in the file LICENSE in this distribution or at |
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| 18 | * http://www.rtems.com/license/LICENSE. |
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| 19 | * |
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| 20 | * $Id$ |
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| 21 | */ |
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[4daebbd] | 22 | |
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| 23 | |
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[d9a6ab3] | 24 | #include <rtems/asm.h> |
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| 25 | #include <rtems/score/cpu_asm.h> |
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| 26 | #include <rtems/score/bfin.h> |
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[9dfd75e] | 27 | #include <rtems/bfin/bfin.h> |
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[d9a6ab3] | 28 | |
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[fbf8301] | 29 | #define LO(con32) ((con32) & 0xFFFF) |
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| 30 | #define HI(con32) (((con32) >> 16) & 0xFFFF) |
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[d9a6ab3] | 31 | |
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[4daebbd] | 32 | |
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| 33 | #if 0 |
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| 34 | /* some debug routines */ |
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| 35 | .globl __CPU_write_char; |
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| 36 | __CPU_write_char: |
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| 37 | p0.h = 0xffc0; |
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| 38 | p0.l = 0x0400; |
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| 39 | txWaitLoop: |
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| 40 | r1 = w[p0 + 0x14]; |
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| 41 | cc = bittst(r1, 5); |
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| 42 | if !cc jump txWaitLoop; |
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| 43 | w[p0 + 0x00] = r0; |
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| 44 | rts; |
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| 45 | |
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| 46 | .globl __CPU_write_crlf; |
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| 47 | __CPU_write_crlf: |
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| 48 | r0 = '\r'; |
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| 49 | [--sp] = rets; |
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| 50 | call __CPU_write_char; |
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| 51 | rets = [sp++]; |
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| 52 | r0 = '\n'; |
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| 53 | jump __CPU_write_char; |
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| 54 | |
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| 55 | __CPU_write_space: |
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| 56 | r0 = ' '; |
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| 57 | jump __CPU_write_char; |
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| 58 | |
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| 59 | .globl __CPU_write_nybble; |
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| 60 | __CPU_write_nybble: |
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| 61 | r1 = 0x0f; |
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| 62 | r0 = r0 & r1; |
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| 63 | r0 += '0'; |
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| 64 | r1 = '9'; |
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| 65 | cc = r0 <= r1; |
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| 66 | if cc jump __CPU_write_char; |
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| 67 | r0 += 'a' - '0' - 10; |
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| 68 | jump __CPU_write_char; |
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| 69 | |
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| 70 | .globl __CPU_write_byte; |
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| 71 | __CPU_write_byte: |
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| 72 | [--sp] = r0; |
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| 73 | [--sp] = rets; |
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| 74 | r0 >>= 4; |
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| 75 | call __CPU_write_nybble; |
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| 76 | rets = [sp++]; |
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| 77 | r0 = [sp++]; |
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| 78 | jump __CPU_write_nybble; |
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| 79 | |
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| 80 | __CPU_write_chawmp: |
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| 81 | [--sp] = r0; |
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| 82 | [--sp] = rets; |
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| 83 | r0 >>= 8; |
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| 84 | call __CPU_write_byte; |
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| 85 | rets = [sp++]; |
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| 86 | r0 = [sp++]; |
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| 87 | jump __CPU_write_byte; |
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| 88 | |
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| 89 | __CPU_write_gawble: |
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| 90 | [--sp] = r0; |
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| 91 | [--sp] = rets; |
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| 92 | r0 >>= 16; |
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| 93 | call __CPU_write_chawmp; |
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| 94 | rets = [sp++]; |
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| 95 | r0 = [sp++]; |
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| 96 | jump __CPU_write_chawmp; |
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| 97 | |
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| 98 | __CPU_dump_registers: |
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| 99 | [--sp] = rets; |
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| 100 | [--sp] = r0; |
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| 101 | [--sp] = r1; |
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| 102 | [--sp] = p0; |
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| 103 | r0 = [sp + 8]; |
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| 104 | call __CPU_write_gawble; |
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| 105 | call __CPU_write_space; |
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| 106 | r0 = [sp + 4]; |
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| 107 | call __CPU_write_gawble; |
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| 108 | call __CPU_write_space; |
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| 109 | r0 = r2; |
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| 110 | call __CPU_write_gawble; |
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| 111 | call __CPU_write_space; |
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| 112 | r0 = r3; |
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| 113 | call __CPU_write_gawble; |
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| 114 | call __CPU_write_space; |
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| 115 | r0 = r4; |
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| 116 | call __CPU_write_gawble; |
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| 117 | call __CPU_write_space; |
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| 118 | r0 = r5; |
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| 119 | call __CPU_write_gawble; |
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| 120 | call __CPU_write_space; |
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| 121 | r0 = r6; |
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| 122 | call __CPU_write_gawble; |
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| 123 | call __CPU_write_space; |
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| 124 | r0 = r7; |
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| 125 | call __CPU_write_gawble; |
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| 126 | call __CPU_write_crlf; |
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| 127 | r0 = [sp]; |
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| 128 | call __CPU_write_gawble; |
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| 129 | call __CPU_write_space; |
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| 130 | r0 = p1; |
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| 131 | call __CPU_write_gawble; |
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| 132 | call __CPU_write_space; |
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| 133 | r0 = p2; |
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| 134 | call __CPU_write_gawble; |
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| 135 | call __CPU_write_space; |
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| 136 | r0 = p3; |
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| 137 | call __CPU_write_gawble; |
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| 138 | call __CPU_write_space; |
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| 139 | r0 = p4; |
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| 140 | call __CPU_write_gawble; |
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| 141 | call __CPU_write_space; |
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| 142 | r0 = p5; |
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| 143 | call __CPU_write_gawble; |
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| 144 | call __CPU_write_space; |
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| 145 | r0 = fp; |
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| 146 | call __CPU_write_gawble; |
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| 147 | call __CPU_write_space; |
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| 148 | r0 = sp; |
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| 149 | r0 += 16; |
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| 150 | call __CPU_write_gawble; |
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| 151 | call __CPU_write_crlf; |
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| 152 | |
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| 153 | p0 = [sp++]; |
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| 154 | r1 = [sp++]; |
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| 155 | r0 = [sp++]; |
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| 156 | rets = [sp++]; |
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| 157 | rts; |
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| 158 | |
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| 159 | .globl __CPU_Exception_handler; |
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| 160 | __CPU_Exception_handler: |
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| 161 | usp = sp; |
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| 162 | sp.h = 0xffb0; |
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| 163 | sp.l = 0x1000; |
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| 164 | [--sp] = (r7:0,p5:0); |
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| 165 | |
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| 166 | r0 = 'x'; |
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| 167 | call __CPU_write_char; |
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| 168 | jump hcf; |
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| 169 | |
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| 170 | |
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| 171 | .globl __CPU_Emulation_handler; |
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| 172 | __CPU_Emulation_handler: |
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| 173 | usp = sp; |
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| 174 | sp.h = 0xffb0; |
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| 175 | sp.l = 0x1000; |
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| 176 | [--sp] = (r7:0,p5:0); |
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| 177 | |
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| 178 | r0 = 'e'; |
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| 179 | call __CPU_write_char; |
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| 180 | jump hcf; |
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| 181 | |
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| 182 | .globl __CPU_Reset_handler; |
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| 183 | __CPU_Reset_handler: |
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| 184 | usp = sp; |
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| 185 | sp.h = 0xffb0; |
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| 186 | sp.l = 0x1000; |
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| 187 | [--sp] = (r7:0,p5:0); |
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| 188 | |
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| 189 | r0 = 'r'; |
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| 190 | call __CPU_write_char; |
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| 191 | jump hcf; |
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| 192 | |
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| 193 | .globl __CPU_NMI_handler; |
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| 194 | __CPU_NMI_handler: |
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| 195 | usp = sp; |
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| 196 | sp.h = 0xffb0; |
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| 197 | sp.l = 0x1000; |
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| 198 | [--sp] = (r7:0,p5:0); |
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| 199 | |
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| 200 | r0 = 'n'; |
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| 201 | call __CPU_write_char; |
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| 202 | jump hcf; |
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| 203 | |
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| 204 | .globl __CPU_Unhandled_Interrupt_handler; |
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| 205 | __CPU_Unhandled_Interrupt_handler: |
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| 206 | usp = sp; |
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| 207 | sp.h = 0xffb0; |
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| 208 | sp.l = 0x1000; |
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| 209 | [--sp] = (r7:0,p5:0); |
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| 210 | |
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| 211 | call __CPU_write_crlf; |
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| 212 | r0 = 'i'; |
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| 213 | call __CPU_write_char; |
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| 214 | p0.h = HI(IPEND); |
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| 215 | p0.l = LO(IPEND); |
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| 216 | r0 = [p0]; |
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| 217 | call __CPU_write_chawmp; |
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| 218 | jump hcf; |
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| 219 | |
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| 220 | hcf: |
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| 221 | idle; |
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| 222 | jump hcf; |
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| 223 | |
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| 224 | #endif |
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| 225 | |
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| 226 | |
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[d9a6ab3] | 227 | /* _CPU_Context_switch |
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| 228 | * |
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| 229 | * This routine performs a normal non-FP context switch. |
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| 230 | * |
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| 231 | * bfin Specific Information: |
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| 232 | * |
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| 233 | * For now we simply save all registers. |
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[4daebbd] | 234 | * |
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[d9a6ab3] | 235 | */ |
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| 236 | |
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[4daebbd] | 237 | /* make sure this sequence stays in sync with the definition for |
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| 238 | Context_Control in rtems/score/cpu.h */ |
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| 239 | .globl __CPU_Context_switch |
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[d9a6ab3] | 240 | __CPU_Context_switch: |
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[4daebbd] | 241 | /* Start saving context R0 = current, R1=heir */ |
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| 242 | p0 = r0; |
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| 243 | [p0++] = r4; |
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| 244 | [p0++] = r5; |
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| 245 | [p0++] = r6; |
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| 246 | [p0++] = r7; |
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| 247 | |
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| 248 | /* save pointer registers */ |
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| 249 | [p0++] = p3; |
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| 250 | [p0++] = p4; |
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| 251 | [p0++] = p5; |
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| 252 | [p0++] = fp; |
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| 253 | [p0++] = sp; |
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| 254 | |
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| 255 | /* save length registers */ |
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| 256 | r0 = l0; |
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| 257 | [p0++] = r0; |
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| 258 | r0 = l1; |
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| 259 | [p0++] = r0; |
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| 260 | r0 = l2; |
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| 261 | [p0++] = r0; |
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| 262 | r0 = l3; |
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| 263 | [p0++] = r0; |
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| 264 | |
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| 265 | /* save rets */ |
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| 266 | r0 = rets; |
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| 267 | [p0++] = r0; |
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| 268 | |
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| 269 | /* save IMASK */ |
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| 270 | p1.h = HI(IMASK); |
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| 271 | p1.l = LO(IMASK); |
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| 272 | r0 = [p1]; |
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| 273 | [p0++] = r0; |
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[d9a6ab3] | 274 | |
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[4daebbd] | 275 | p0 = r1; |
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[d9a6ab3] | 276 | restore: |
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[4daebbd] | 277 | /* restore data registers */ |
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| 278 | r4 = [p0++]; |
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| 279 | r5 = [p0++]; |
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| 280 | r6 = [p0++]; |
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| 281 | r7 = [p0++]; |
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| 282 | |
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| 283 | /* restore pointer registers */ |
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| 284 | p3 = [p0++]; |
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| 285 | p4 = [p0++]; |
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| 286 | p5 = [p0++]; |
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| 287 | fp = [p0++]; |
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| 288 | sp = [p0++]; |
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| 289 | |
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| 290 | /* restore length registers */ |
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| 291 | r0 = [p0++]; |
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| 292 | l0 = r0; |
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| 293 | r0 = [p0++]; |
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| 294 | l1 = r0; |
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| 295 | r0 = [p0++]; |
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| 296 | l2 = r0; |
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| 297 | r0 = [p0++]; |
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| 298 | l3 = r0; |
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| 299 | |
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| 300 | /* restore rets */ |
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| 301 | r0 = [p0++]; |
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| 302 | rets = r0; |
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| 303 | |
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| 304 | /* restore IMASK */ |
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| 305 | r0 = [p0++]; |
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| 306 | p1.h = HI(IMASK); |
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| 307 | p1.l = LO(IMASK); |
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| 308 | [p1] = r0; |
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| 309 | |
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| 310 | rts; |
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| 311 | |
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[d9a6ab3] | 312 | |
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| 313 | /* |
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| 314 | * _CPU_Context_restore |
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| 315 | * |
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| 316 | * This routine is generally used only to restart self in an |
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| 317 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 318 | * |
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| 319 | * NOTE: May be unnecessary to reload some registers. |
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| 320 | * |
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| 321 | * Blackfin Specific Information: |
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| 322 | * |
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| 323 | * none |
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| 324 | * |
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| 325 | */ |
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[4daebbd] | 326 | .globl __CPU_Context_restore |
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[d9a6ab3] | 327 | __CPU_Context_restore: |
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[4daebbd] | 328 | p0 = r0; |
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| 329 | jump restore; |
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| 330 | |
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| 331 | |
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| 332 | .globl __ISR_Handler |
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| 333 | .extern __CPU_Interrupt_stack_high; |
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| 334 | .extern __ISR_Nest_level |
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| 335 | .extern __Thread_Dispatch_disable_level |
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| 336 | .extern __Context_Switch_necessary |
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| 337 | .extern __ISR_Signals_to_thread_executing |
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[d9a6ab3] | 338 | __ISR_Handler: |
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[4daebbd] | 339 | /* all interrupts are disabled at this point */ |
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| 340 | /* the following few items are pushed onto the task stack for at |
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| 341 | most one interrupt; nested interrupts will be using the interrupt |
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| 342 | stack for everything. */ |
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| 343 | [--sp] = astat; |
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| 344 | [--sp] = p1; |
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| 345 | [--sp] = p0; |
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| 346 | [--sp] = r1; |
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| 347 | [--sp] = r0; |
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| 348 | p0.h = __ISR_Nest_level; |
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| 349 | p0.l = __ISR_Nest_level; |
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| 350 | r0 = [p0]; |
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| 351 | r0 += 1; |
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| 352 | [p0] = r0; |
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| 353 | cc = r0 <= 1 (iu); |
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| 354 | if !cc jump noStackSwitch; |
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| 355 | /* setup interrupt stack */ |
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| 356 | r0 = sp; |
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| 357 | p0.h = __CPU_Interrupt_stack_high; |
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| 358 | p0.l = __CPU_Interrupt_stack_high; |
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| 359 | sp = [p0]; |
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| 360 | [--sp] = r0; |
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| 361 | noStackSwitch: |
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| 362 | /* disable thread dispatch */ |
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| 363 | p0.h = __Thread_Dispatch_disable_level; |
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| 364 | p0.l = __Thread_Dispatch_disable_level; |
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| 365 | r0 = [p0]; |
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| 366 | r0 += 1; |
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| 367 | [p0] = r0; |
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| 368 | |
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| 369 | [--sp] = reti; /* interrupts are now enabled */ |
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| 370 | |
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| 371 | /* figure out what vector we are */ |
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| 372 | p0.h = HI(IPEND); |
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| 373 | p0.l = LO(IPEND); |
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| 374 | r1 = [p0]; |
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| 375 | /* we should only get here for events that require RTI to return */ |
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| 376 | r1 = r1 >> 5; |
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| 377 | r0 = 4; |
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| 378 | /* at least one bit must be set, so this loop will exit */ |
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| 379 | vectorIDLoop: |
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| 380 | r0 += 1; |
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| 381 | r1 = rot r1 by -1; |
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| 382 | if !cc jump vectorIDLoop; |
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| 383 | |
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| 384 | [--sp] = r2; |
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| 385 | p0.h = __ISR_Vector_table; |
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| 386 | p0.l = __ISR_Vector_table; |
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| 387 | r2 = [p0]; |
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| 388 | r1 = r0 << 2; |
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| 389 | r1 = r1 + r2; |
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| 390 | p0 = r1; |
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| 391 | p0 = [p0]; |
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| 392 | cc = p0 == 0; |
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| 393 | if cc jump noHandler; |
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| 394 | |
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| 395 | /* r2, r0, r1, p0, p1, astat are already saved */ |
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| 396 | [--sp] = a1.x; |
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| 397 | [--sp] = a1.w; |
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| 398 | [--sp] = a0.x; |
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| 399 | [--sp] = a0.w; |
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| 400 | [--sp] = r3; |
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| 401 | [--sp] = p3; |
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| 402 | [--sp] = p2; |
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| 403 | [--sp] = lt1; |
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| 404 | [--sp] = lt0; |
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| 405 | [--sp] = lc1; |
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| 406 | [--sp] = lc0; |
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| 407 | [--sp] = lb1; |
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| 408 | [--sp] = lb0; |
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| 409 | [--sp] = i3; |
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| 410 | [--sp] = i2; |
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| 411 | [--sp] = i1; |
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| 412 | [--sp] = i0; |
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| 413 | [--sp] = m3; |
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| 414 | [--sp] = m2; |
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| 415 | [--sp] = m1; |
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| 416 | [--sp] = m0; |
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| 417 | [--sp] = l3; |
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| 418 | [--sp] = l2; |
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| 419 | [--sp] = l1; |
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| 420 | [--sp] = l0; |
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| 421 | [--sp] = b3; |
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| 422 | [--sp] = b2; |
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| 423 | [--sp] = b1; |
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| 424 | [--sp] = b0; |
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| 425 | [--sp] = rets; |
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| 426 | r1 = fp; /* is this really what should be passed here? */ |
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| 427 | /* call user isr; r0 = vector number, r1 = frame pointer */ |
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| 428 | sp += -12; /* bizarre abi... */ |
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| 429 | call (p0); |
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| 430 | sp += 12; |
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| 431 | rets = [sp++]; |
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| 432 | b0 = [sp++]; |
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| 433 | b1 = [sp++]; |
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| 434 | b2 = [sp++]; |
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| 435 | b3 = [sp++]; |
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| 436 | l0 = [sp++]; |
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| 437 | l1 = [sp++]; |
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| 438 | l2 = [sp++]; |
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| 439 | l3 = [sp++]; |
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| 440 | m0 = [sp++]; |
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| 441 | m1 = [sp++]; |
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| 442 | m2 = [sp++]; |
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| 443 | m3 = [sp++]; |
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| 444 | i0 = [sp++]; |
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| 445 | i1 = [sp++]; |
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| 446 | i2 = [sp++]; |
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| 447 | i3 = [sp++]; |
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| 448 | lb0 = [sp++]; |
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| 449 | lb1 = [sp++]; |
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| 450 | lc0 = [sp++]; |
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| 451 | lc1 = [sp++]; |
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| 452 | lt0 = [sp++]; |
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| 453 | lt1 = [sp++]; |
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| 454 | p2 = [sp++]; |
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| 455 | p3 = [sp++]; |
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| 456 | r3 = [sp++]; |
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| 457 | a0.w = [sp++]; |
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| 458 | a0.x = [sp++]; |
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| 459 | a1.w = [sp++]; |
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| 460 | a1.x = [sp++]; |
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| 461 | |
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| 462 | noHandler: |
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| 463 | r2 = [sp++]; |
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| 464 | /* this disables interrupts again */ |
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| 465 | reti = [sp++]; |
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| 466 | |
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| 467 | p0.h = __ISR_Nest_level; |
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| 468 | p0.l = __ISR_Nest_level; |
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| 469 | r0 = [p0]; |
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| 470 | r0 += -1; |
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| 471 | [p0] = r0; |
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| 472 | cc = r0 == 0; |
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| 473 | if !cc jump noStackRestore; |
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| 474 | sp = [sp]; |
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| 475 | noStackRestore: |
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| 476 | |
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| 477 | /* check this stuff to insure context_switch_necessary and |
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| 478 | isr_signals_to_thread_executing are being handled appropriately. */ |
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| 479 | p0.h = __Thread_Dispatch_disable_level; |
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| 480 | p0.l = __Thread_Dispatch_disable_level; |
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| 481 | r0 = [p0]; |
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| 482 | r0 += -1; |
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| 483 | [p0] = r0; |
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| 484 | cc = r0 == 0; |
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| 485 | if !cc jump noDispatch |
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| 486 | |
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| 487 | /* do thread dispatch if necessary */ |
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| 488 | p0.h = __Context_Switch_necessary; |
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| 489 | p0.l = __Context_Switch_necessary; |
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| 490 | r0 = [p0]; |
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| 491 | cc = r0 == 0; |
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| 492 | p0.h = __ISR_Signals_to_thread_executing; |
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| 493 | p0.l = __ISR_Signals_to_thread_executing; |
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| 494 | if !cc jump doDispatch |
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| 495 | r0 = [p0]; |
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| 496 | cc = r0 == 0; |
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| 497 | if cc jump noDispatch |
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| 498 | doDispatch: |
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| 499 | r0 = 0; |
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| 500 | [p0] = r0; |
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| 501 | raise 15; |
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| 502 | noDispatch: |
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| 503 | r0 = [sp++]; |
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| 504 | r1 = [sp++]; |
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| 505 | p0 = [sp++]; |
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| 506 | p1 = [sp++]; |
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| 507 | astat = [sp++]; |
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| 508 | rti |
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| 509 | |
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| 510 | |
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| 511 | /* the approach here is for the main interrupt handler, when a dispatch is |
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| 512 | wanted, to do a "raise 15". when the main interrupt handler does its |
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| 513 | "rti", the "raise 15" takes effect and we end up here. we can now |
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| 514 | safely call _Thread_Dispatch, and do an "rti" to get back to the |
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| 515 | original interrupted function. this does require self-nesting to be |
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| 516 | enabled; the maximum nest depth is the number of tasks. */ |
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| 517 | .global __ISR15_Handler |
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| 518 | .extern __Thread_Dispatch |
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| 519 | __ISR15_Handler: |
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| 520 | [--sp] = reti; |
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| 521 | [--sp] = rets; |
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| 522 | [--sp] = astat; |
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| 523 | [--sp] = a1.x; |
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| 524 | [--sp] = a1.w; |
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| 525 | [--sp] = a0.x; |
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| 526 | [--sp] = a0.w; |
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| 527 | [--sp] = r3; |
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| 528 | [--sp] = r2; |
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| 529 | [--sp] = r1; |
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| 530 | [--sp] = r0; |
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| 531 | [--sp] = p3; |
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| 532 | [--sp] = p2; |
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| 533 | [--sp] = p1; |
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| 534 | [--sp] = p0; |
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| 535 | [--sp] = lt1; |
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| 536 | [--sp] = lt0; |
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| 537 | [--sp] = lc1; |
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| 538 | [--sp] = lc0; |
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| 539 | [--sp] = lb1; |
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| 540 | [--sp] = lb0; |
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| 541 | [--sp] = i3; |
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| 542 | [--sp] = i2; |
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| 543 | [--sp] = i1; |
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| 544 | [--sp] = i0; |
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| 545 | [--sp] = m3; |
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| 546 | [--sp] = m2; |
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| 547 | [--sp] = m1; |
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| 548 | [--sp] = m0; |
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| 549 | [--sp] = l3; |
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| 550 | [--sp] = l2; |
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| 551 | [--sp] = l1; |
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| 552 | [--sp] = l0; |
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| 553 | [--sp] = b3; |
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| 554 | [--sp] = b2; |
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| 555 | [--sp] = b1; |
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| 556 | [--sp] = b0; |
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| 557 | sp += -12; /* bizarre abi... */ |
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| 558 | call __Thread_Dispatch; |
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| 559 | sp += 12; |
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| 560 | b0 = [sp++]; |
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| 561 | b1 = [sp++]; |
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| 562 | b2 = [sp++]; |
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| 563 | b3 = [sp++]; |
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| 564 | l0 = [sp++]; |
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| 565 | l1 = [sp++]; |
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| 566 | l2 = [sp++]; |
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| 567 | l3 = [sp++]; |
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| 568 | m0 = [sp++]; |
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| 569 | m1 = [sp++]; |
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| 570 | m2 = [sp++]; |
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| 571 | m3 = [sp++]; |
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| 572 | i0 = [sp++]; |
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| 573 | i1 = [sp++]; |
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| 574 | i2 = [sp++]; |
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| 575 | i3 = [sp++]; |
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| 576 | lb0 = [sp++]; |
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| 577 | lb1 = [sp++]; |
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| 578 | lc0 = [sp++]; |
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| 579 | lc1 = [sp++]; |
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| 580 | lt0 = [sp++]; |
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| 581 | lt1 = [sp++]; |
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| 582 | p0 = [sp++]; |
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| 583 | p1 = [sp++]; |
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| 584 | p2 = [sp++]; |
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| 585 | p3 = [sp++]; |
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| 586 | r0 = [sp++]; |
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| 587 | r1 = [sp++]; |
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| 588 | r2 = [sp++]; |
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| 589 | r3 = [sp++]; |
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| 590 | a0.w = [sp++]; |
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| 591 | a0.x = [sp++]; |
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| 592 | a1.w = [sp++]; |
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| 593 | a1.x = [sp++]; |
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| 594 | astat = [sp++]; |
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| 595 | rets = [sp++]; |
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| 596 | reti = [sp++]; |
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| 597 | rti; |
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[d9a6ab3] | 598 | |
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