[d9a6ab3] | 1 | /* cpu_asm.S |
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| 2 | * |
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| 3 | * This file contains the basic algorithms for all assembly code used |
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| 4 | * in the Blackfin port of RTEMS. These algorithms must be implemented |
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| 5 | * in assembly language |
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| 6 | * |
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| 7 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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| 8 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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| 9 | * and Antonio Giovanini <antonio@atos.com.br> |
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| 10 | * |
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| 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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| 13 | * http://www.rtems.com/license/LICENSE. |
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| 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | |
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| 19 | #include <rtems/asm.h> |
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| 20 | #include <rtems/score/cpu_asm.h> |
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| 21 | #include <rtems/score/bfin.h> |
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[9dfd75e] | 22 | #include <rtems/bfin/bfin.h> |
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[d9a6ab3] | 23 | |
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[fbf8301] | 24 | #define LO(con32) ((con32) & 0xFFFF) |
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| 25 | #define HI(con32) (((con32) >> 16) & 0xFFFF) |
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[d9a6ab3] | 26 | |
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| 27 | /* _CPU_Context_switch |
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| 28 | * |
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| 29 | * This routine performs a normal non-FP context switch. |
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| 30 | * |
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| 31 | * bfin Specific Information: |
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| 32 | * |
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| 33 | * For now we simply save all registers. |
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| 34 | * |
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| 35 | */ |
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| 36 | |
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| 37 | .globl __CPU_Context_switch |
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| 38 | __CPU_Context_switch: |
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| 39 | /* Start saving context R0 = current, R1=heir */ |
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| 40 | /*save P0 first*/ |
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| 41 | [FP+0x8] = P0; |
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| 42 | P0 = R0; |
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| 43 | [ P0 + R0_OFFSET ] = R0; |
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| 44 | [ P0 + R1_OFFSET] = R1; |
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| 45 | [ P0 + R2_OFFSET] = R2; |
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| 46 | [ P0 + R4_OFFSET] = R4; |
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| 47 | [ P0 + R3_OFFSET] = R3; |
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| 48 | [ P0 + R5_OFFSET] = R5; |
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| 49 | [ P0 + R6_OFFSET] = R6; |
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| 50 | [ P0 + R7_OFFSET] = R7; |
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| 51 | [ P0 + P1_OFFSET] = P1; |
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| 52 | /* save the original value of P0 */ |
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| 53 | P1 = [FP+0x8]; |
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| 54 | [ P0 + P0_OFFSET] = P1; |
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| 55 | [ P0 + P2_OFFSET] = P2; |
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| 56 | [ P0 + P3_OFFSET] = P3; |
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| 57 | [ P0 + P4_OFFSET] = P4; |
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| 58 | [ P0 + P5_OFFSET] = P5; |
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| 59 | [ P0 + FP_OFFSET] = FP; |
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| 60 | [ P0 + SP_OFFSET] = SP; |
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| 61 | |
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| 62 | /* save ASTAT */ |
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| 63 | R0 = ASTAT; |
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| 64 | [P0 + ASTAT_OFFSET] = R0; |
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| 65 | |
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| 66 | /* save Loop Counters */ |
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| 67 | R0 = LC0; |
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| 68 | [P0 + LC0_OFFSET] = R0; |
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| 69 | R0 = LC1; |
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| 70 | [P0 + LC1_OFFSET] = R0; |
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| 71 | |
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| 72 | /* save Accumulators */ |
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| 73 | R0 = A0.W; |
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| 74 | [P0 + A0W_OFFSET] = R0; |
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| 75 | R0 = A0.X; |
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| 76 | [P0 + A0X_OFFSET] = R0; |
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| 77 | R0 = A1.W; |
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| 78 | [P0 + A1W_OFFSET] = R0; |
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| 79 | R0 = A1.X; |
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| 80 | [P0 + A1X_OFFSET] = R0; |
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| 81 | |
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| 82 | /* save Index Registers */ |
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| 83 | R0 = I0; |
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| 84 | [P0 + I0_OFFSET] = R0; |
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| 85 | R0 = I1; |
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| 86 | [P0 + I1_OFFSET] = R0; |
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| 87 | R0 = I2; |
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| 88 | [P0 + I2_OFFSET] = R0; |
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| 89 | R0 = I3; |
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| 90 | [P0 + I3_OFFSET] = R0; |
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| 91 | |
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| 92 | /* save Modifier Registers */ |
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| 93 | R0 = M0; |
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| 94 | [P0 + M0_OFFSET] = R0; |
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| 95 | R0 = M1; |
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| 96 | [P0 + M1_OFFSET] = R0; |
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| 97 | R0 = M2; |
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| 98 | [P0 + M2_OFFSET] = R0; |
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| 99 | R0 = M3; |
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| 100 | [P0 + M3_OFFSET] = R0; |
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| 101 | |
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| 102 | /* save Length Registers */ |
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| 103 | R0 = L0; |
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| 104 | [P0 + L0_OFFSET] = R0; |
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| 105 | R0 = L1; |
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| 106 | [P0 + L1_OFFSET] = R0; |
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| 107 | R0 = L2; |
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| 108 | [P0 + L2_OFFSET] = R0; |
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| 109 | R0 = L3; |
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| 110 | [P0 + L3_OFFSET] = R0; |
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| 111 | |
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| 112 | /* Base Registers */ |
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| 113 | R0 = B0; |
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| 114 | [P0 + B0_OFFSET] = R0; |
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| 115 | R0 = B1; |
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| 116 | [P0 + B1_OFFSET] = R0; |
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| 117 | R0 = B2; |
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| 118 | [P0 + B2_OFFSET] = R0; |
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| 119 | R0 = B3; |
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| 120 | [P0 + B3_OFFSET] = R0; |
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| 121 | |
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| 122 | /* save RETS */ |
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| 123 | R0 = RETS; |
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| 124 | [ P0 + RETS_OFFSET] = R0; |
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| 125 | |
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| 126 | restore: |
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| 127 | P0 = R1; |
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| 128 | R1 = [P0 + R1_OFFSET]; |
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| 129 | R2 = [P0 + R2_OFFSET]; |
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| 130 | R3 = [P0 + R3_OFFSET]; |
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| 131 | R4 = [P0 + R4_OFFSET]; |
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| 132 | R5 = [P0 + R5_OFFSET]; |
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| 133 | R6 = [P0 + R6_OFFSET]; |
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| 134 | R7 = [P0 + R7_OFFSET]; |
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| 135 | |
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| 136 | P2 = [P0 + P2_OFFSET]; |
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| 137 | P3 = [P0 + P3_OFFSET]; |
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| 138 | P4 = [P0 + P4_OFFSET]; |
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| 139 | P5 = [P0 + P5_OFFSET]; |
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| 140 | |
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| 141 | /* might have to be placed more to the end */ |
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| 142 | FP = [P0 + FP_OFFSET]; |
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| 143 | SP = [P0 + SP_OFFSET]; |
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| 144 | |
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| 145 | /* save ASTAT */ |
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| 146 | R0 = [P0 + ASTAT_OFFSET]; |
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| 147 | ASTAT = R0; |
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| 148 | |
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| 149 | /* save Loop Counters */ |
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| 150 | R0 = [P0 + LC0_OFFSET]; |
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| 151 | LC0 = R0; |
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| 152 | R0 = [P0 + LC1_OFFSET]; |
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| 153 | LC1 = R0; |
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| 154 | |
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| 155 | /* save Accumulators */ |
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| 156 | R0 = [P0 + A0W_OFFSET]; |
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| 157 | A0.W = R0; |
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| 158 | R0 = [P0 + A0X_OFFSET]; |
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| 159 | A0.X = R0; |
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| 160 | R0 = [P0 + A1W_OFFSET]; |
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| 161 | A1.W = R0; |
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| 162 | R0 = [P0 + A1X_OFFSET]; |
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| 163 | A1.X = R0; |
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| 164 | |
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| 165 | /* save Index Registers */ |
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| 166 | R0 = [P0 + I0_OFFSET]; |
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| 167 | I0 = R0; |
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| 168 | R0 = [P0 + I1_OFFSET]; |
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| 169 | I1 = R0; |
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| 170 | R0 = [P0 + I2_OFFSET]; |
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| 171 | I2 = R0; |
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| 172 | R0 = [P0 + I3_OFFSET]; |
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| 173 | I3 = R0; |
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| 174 | |
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| 175 | /* save Modifier Registers */ |
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| 176 | R0 = [P0 + M0_OFFSET]; |
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| 177 | M0 = R0; |
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| 178 | R0 = [P0 + M1_OFFSET]; |
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| 179 | M1 = R0; |
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| 180 | R0 = [P0 + M2_OFFSET]; |
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| 181 | M2 = R0; |
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| 182 | R0 = [P0 + M3_OFFSET]; |
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| 183 | M3 = R0; |
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| 184 | |
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| 185 | /* save Length Registers */ |
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| 186 | R0 = [P0 + L0_OFFSET]; |
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| 187 | L0 = R0; |
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| 188 | R0 = [P0 + L1_OFFSET]; |
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| 189 | L1 = R0; |
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| 190 | R0 = [P0 + L2_OFFSET]; |
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| 191 | L2 = R0; |
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| 192 | R0 = [P0 + L3_OFFSET]; |
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| 193 | L3 = R0; |
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| 194 | |
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| 195 | /* Base Registers */ |
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| 196 | R0 = [P0 + B0_OFFSET]; |
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| 197 | B0 = R0; |
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| 198 | R0 = [P0 + B1_OFFSET]; |
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| 199 | B1 = R0; |
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| 200 | R0 = [P0 + B2_OFFSET]; |
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| 201 | B2 = R0; |
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| 202 | R0 = [P0 + B3_OFFSET]; |
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| 203 | B3 = R0; |
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| 204 | |
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| 205 | /* restore RETS */ |
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| 206 | P1 = [P0 + RETS_OFFSET]; |
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| 207 | RETS = P1; |
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| 208 | |
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| 209 | /* now restore the P1 + P0 */ |
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| 210 | P1 = [P0 + R1_OFFSET]; |
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| 211 | P0 = [P0 + P0_OFFSET]; |
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| 212 | |
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| 213 | rts; |
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| 214 | |
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| 215 | |
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| 216 | /* |
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| 217 | * _CPU_Context_restore |
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| 218 | * |
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| 219 | * This routine is generally used only to restart self in an |
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| 220 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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| 221 | * |
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| 222 | * NOTE: May be unnecessary to reload some registers. |
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| 223 | * |
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| 224 | * Blackfin Specific Information: |
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| 225 | * |
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| 226 | * none |
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| 227 | * |
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| 228 | */ |
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| 229 | .globl __CPU_Context_restore |
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| 230 | __CPU_Context_restore: |
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| 231 | jump restore; |
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| 232 | |
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| 233 | |
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| 234 | |
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| 235 | .globl __ISR_Thread_Dispatch |
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| 236 | __ISR_Thread_Dispatch: |
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| 237 | |
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| 238 | .extern __Thread_Dispatch |
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| 239 | R0.l = __Thread_Dispatch; |
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| 240 | R0.h = __Thread_Dispatch; |
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| 241 | |
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| 242 | /* Puts the address of th Thread_Dispatch function on Stack |
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| 243 | * Where it will be restored to the RTI register |
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| 244 | */ |
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| 245 | P0 = [FP]; |
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| 246 | /* save the old reti */ |
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| 247 | R1 = [P0+0xc]; |
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| 248 | [P0+0xc] = R0; |
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| 249 | /* |
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| 250 | * Overwriting the RETS Register is save because Thread_Dispatch is |
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| 251 | * disabled when we are between call/link or unlink/rts |
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| 252 | */ |
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| 253 | [P0+0x8] = R1; |
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| 254 | |
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| 255 | /* save old rets */ |
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| 256 | |
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| 257 | rts; |
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| 258 | |
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| 259 | |
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| 260 | .globl __ISR_Handler |
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| 261 | __ISR_Handler: |
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| 262 | /* First of all check the Stackpointer and */ |
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| 263 | /* switch to Scratchpad if necessary */ |
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| 264 | |
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| 265 | /* save P0 and R0 in the scratchpad */ |
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| 266 | USP = P0; |
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| 267 | |
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| 268 | /* load base adress of scratchpad */ |
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| 269 | P0.H = HI(SCRATCH); |
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| 270 | P0.L = LO(SCRATCH); |
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[c55364c4] | 271 | |
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| 272 | [--SP] = ASTAT; /* save cc flag*/ |
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[d9a6ab3] | 273 | /* if SP is already inside the SCRATCHPAD */ |
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| 274 | CC=SP<P0 (iu) |
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| 275 | if !CC jump continue; |
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| 276 | |
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| 277 | /* set PO to top of scratchpad */ |
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| 278 | P0.h=HI(SCRATCH_TOP); |
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| 279 | P0.l=LO(SCRATCH_TOP); |
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| 280 | /*save the old SP*/ |
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| 281 | [P0] = SP; |
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| 282 | /*P0 += -4;*/ |
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| 283 | /*set the new Stackpointer*/ |
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| 284 | SP = P0; |
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| 285 | /*restore the old PO*/ |
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| 286 | |
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| 287 | /* The Stackpointer is now setup as we want */ |
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| 288 | continue: |
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| 289 | /* restore P0 and save some context */ |
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| 290 | P0 = USP; |
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| 291 | /* save some state on the isr stack (scratchpad), this enables interrupt nesting */ |
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| 292 | [--SP] = RETI; |
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| 293 | [--SP] = RETS; |
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| 294 | [--SP] = ASTAT; |
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| 295 | [--SP] = FP; |
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| 296 | FP = SP; |
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| 297 | [--SP] = (R7:0, P5:0) ; |
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| 298 | |
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| 299 | |
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| 300 | /* Context is saved, now check which Instruction we were executing |
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| 301 | * If we were between a call and link or between a unlink and rts |
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| 302 | * we have to disable Thread_Dispatch because correct restore of context after |
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| 303 | * Thread_Dispatch would not be possible. */ |
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| 304 | |
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| 305 | P0 = RETI; |
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[c55364c4] | 306 | R0 = P0; |
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| 307 | R0.L = 0x0000; |
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| 308 | R1.H = 0xffa0; |
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| 309 | R1.L = 0x0000; |
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| 310 | CC = R0 == R1; |
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| 311 | if CC jump disablethreaddispatch; |
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| 312 | |
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| 313 | R0 = W[P0](Z); |
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| 314 | |
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[d9a6ab3] | 315 | /* shift 16 bits to the right (select the high nibble ) */ |
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| 316 | /*R0 >>= 16;*/ |
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| 317 | |
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| 318 | R3 = 0; |
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| 319 | /* Check if RETI is a LINK instruction */ |
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[c55364c4] | 320 | R1.h = HI(0x0000); |
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[d9a6ab3] | 321 | R1.l = LO(0xE800); |
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| 322 | CC=R0==R1; |
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| 323 | if cc jump disablethreaddispatch; |
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| 324 | |
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| 325 | /* Check if RETI is a RTS instruction */ |
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[c55364c4] | 326 | R1.h = HI(0x0000); |
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[d9a6ab3] | 327 | R1.l = LO(0x0010); |
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| 328 | CC=R0==R1; |
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| 329 | if cc jump disablethreaddispatch; |
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| 330 | |
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| 331 | jump afterthreaddispatch; |
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| 332 | |
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| 333 | disablethreaddispatch: |
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| 334 | /* _Thread_Dispatch_disable_level++ */ |
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| 335 | .extern _Thread_Dispatch_disable_level |
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| 336 | P0.H = __Thread_Dispatch_disable_level; |
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| 337 | P0.L = __Thread_Dispatch_disable_level; |
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| 338 | R0 = [P0]; |
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| 339 | R0 += 1; |
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| 340 | [P0] = R0; |
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| 341 | R3 = 1; |
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| 342 | |
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| 343 | afterthreaddispatch: |
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| 344 | /* Put R3 on the stack */ |
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| 345 | [--SP] = R3; |
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| 346 | |
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| 347 | /* Obtain a bitlist of the pending interrupts. */ |
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| 348 | P0.H = HI(IPEND); |
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| 349 | P0.L = LO(IPEND); |
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| 350 | R1 = [P0]; |
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| 351 | |
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| 352 | /* |
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| 353 | * Search through the bit list stored in R0 to find the first enabled |
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| 354 | * bit. The offset of this bit is the index of the interrupt that is |
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| 355 | * to be handled. |
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| 356 | */ |
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| 357 | R0 = -1; |
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| 358 | intloop: |
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| 359 | R0 += 1; |
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| 360 | R1 = ROT R1 by -1; |
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| 361 | if !cc jump intloop; |
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| 362 | |
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| 363 | |
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| 364 | /* pass SP as parameter to the C function */ |
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| 365 | R1 = SP |
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| 366 | |
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| 367 | /* pass values by register as well as by stack */ |
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| 368 | /* to comply with the c calling conventions */ |
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| 369 | [--SP] = R0; |
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| 370 | [--SP] = R1; |
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| 371 | |
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| 372 | .extern _ISR_Handler2 |
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| 373 | call _ISR_Handler2 |
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| 374 | |
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| 375 | /* inc 2 to compensate the passing of arguments */ |
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| 376 | R3 = [SP++]; |
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| 377 | R3 = [SP++]; |
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| 378 | /* check if _Thread_Dispatch_disable_level has been incremented */ |
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| 379 | R3 = [SP++] |
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| 380 | CC=R3==0 |
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| 381 | if cc jump dont_decrement; |
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| 382 | .extern _Thread_Dispatch_disable_level |
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| 383 | P0.H = __Thread_Dispatch_disable_level; |
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| 384 | P0.L = __Thread_Dispatch_disable_level; |
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| 385 | R0 = [P0]; |
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| 386 | R0 += -1; |
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| 387 | [P0] = R0; |
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| 388 | |
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| 389 | dont_decrement: |
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| 390 | |
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| 391 | (R7:0, P5:0) = [SP++]; |
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| 392 | FP = [SP++]; |
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| 393 | ASTAT = [SP++]; |
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| 394 | RETS = [SP++]; |
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| 395 | RETI = [SP++]; |
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| 396 | /* Interrupts are now disabled again */ |
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| 397 | |
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| 398 | /*should restore the old stack !!!*/ |
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| 399 | /*if sp now points to SCRATCH_TOP */ |
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| 400 | |
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| 401 | /* load base adress of scratchpad */ |
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| 402 | USP = P0; |
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| 403 | P0.H = HI(SCRATCH_TOP); |
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| 404 | P0.L = LO(SCRATCH_TOP); |
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| 405 | |
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| 406 | CC=SP==P0 |
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| 407 | if !cc jump restoreP0 |
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| 408 | /* restore the stack */ |
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| 409 | SP=[P0]; |
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| 410 | |
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| 411 | restoreP0: |
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| 412 | P0 = USP; |
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[c55364c4] | 413 | ASTAT = [SP++]; /* restore cc flag */ |
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[d9a6ab3] | 414 | |
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| 415 | /*now we should be on the old "user-stack" again */ |
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| 416 | |
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| 417 | /* return from interrupt, will jump to adress stored in RETI */ |
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| 418 | RTI; |
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| 419 | |
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