source: rtems/cpukit/score/cpu/bfin/cpu.c @ ff8dd26

4.104.11
Last change on this file since ff8dd26 was ff8dd26, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 27, 2010 at 2:59:26 PM

2010-03-27 Joel Sherrill <joel.sherrill@…>

  • Makefile.am: Remove unused file.
  • irq.c: Removed.
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#ifdef HAVE_CONFIG_H
15#include "config.h"
16#endif
17
18#include <rtems/system.h>
19#include <rtems/score/isr.h>
20#include <rtems/score/wkspace.h>
21#include <rtems/score/bfin.h>
22#include <rtems/bfin/bfin.h>
23
24/*  _CPU_Initialize
25 *
26 *  This routine performs processor dependent initialization.
27 *
28 *  INPUT PARAMETERS: NONE
29 *
30 *  NO_CPU Specific Information:
31 *
32 *  XXX document implementation including references if appropriate
33 */
34
35
36extern void _ISR15_Handler(void);
37extern void _CPU_Emulation_handler(void);
38extern void _CPU_Reset_handler(void);
39extern void _CPU_NMI_handler(void);
40extern void _CPU_Exception_handler(void);
41extern void _CPU_Unhandled_Interrupt_handler(void);
42
43void _CPU_Initialize(void)
44{
45  /*
46   *  If there is not an easy way to initialize the FP context
47   *  during Context_Initialize, then it is usually easier to
48   *  save an "uninitialized" FP context here and copy it to
49   *  the task's during Context_Initialize.
50   */
51
52  /* FP context initialization support goes here */
53
54
55
56  proc_ptr ignored;
57
58#if 0
59  /* occassionally useful debug stuff */
60  int i;
61  _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
62  _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
63  _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
64  _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
65  for (i = 5; i < 15; i++)
66    _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
67#endif
68
69  /* install handler that will be used to call _Thread_Dispatch */
70  _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
71  /* enable self nesting */
72  __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
73}
74
75
76
77
78/*PAGE
79 *
80 *  _CPU_ISR_Get_level
81 *
82 *  NO_CPU Specific Information:
83 *
84 *  XXX document implementation including references if appropriate
85 */
86
87uint32_t   _CPU_ISR_Get_level( void )
88{
89  /*
90   *  This routine returns the current interrupt level.
91   */
92
93    register uint32_t   _tmpimask;
94
95    /*read from the IMASK registers*/
96
97    _tmpimask = *((uint32_t*)IMASK);
98
99    return (_tmpimask & 0xffe0) ? 0 : 1;
100}
101
102/*PAGE
103 *
104 *  _CPU_ISR_install_raw_handler
105 *
106 *  NO_CPU Specific Information:
107 *
108 *  XXX document implementation including references if appropriate
109 */
110
111void _CPU_ISR_install_raw_handler(
112  uint32_t    vector,
113  proc_ptr    new_handler,
114  proc_ptr   *old_handler
115)
116{
117   proc_ptr *interrupt_table = NULL;
118  /*
119   *  This is where we install the interrupt handler into the "raw" interrupt
120   *  table used by the CPU to dispatch interrupt handlers.
121   */
122
123   /* base of vector table on blackfin architecture */
124   interrupt_table = (void*)0xFFE02000;
125
126   *old_handler = interrupt_table[ vector ];
127   interrupt_table[ vector ] = new_handler;
128
129}
130
131/*PAGE
132 *
133 *  _CPU_ISR_install_vector
134 *
135 *  This kernel routine installs the RTEMS handler for the
136 *  specified vector.
137 *
138 *  Input parameters:
139 *    vector      - interrupt vector number
140 *    old_handler - former ISR for this vector number
141 *    new_handler - replacement ISR for this vector number
142 *
143 *  Output parameters:  NONE
144 *
145 *
146 *  NO_CPU Specific Information:
147 *
148 *  XXX document implementation including references if appropriate
149 */
150
151void _CPU_ISR_install_vector(
152  uint32_t    vector,
153  proc_ptr    new_handler,
154  proc_ptr   *old_handler
155)
156{
157   proc_ptr ignored;
158
159   *old_handler = _ISR_Vector_table[ vector ];
160
161   /*
162    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
163    *  be used by the _ISR_Handler so the user gets control.
164    */
165
166    _ISR_Vector_table[ vector ] = new_handler;
167
168    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
169}
170
171#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
172void *_CPU_Thread_Idle_body(uint32_t ignored)
173{
174  while (1) {
175    __asm__ __volatile__("ssync; idle; ssync");
176  }
177}
178#endif
179
180/*
181 * Copied from the arm port.
182 */
183void _CPU_Context_Initialize(
184  Context_Control  *the_context,
185  uint32_t         *stack_base,
186  uint32_t          size,
187  uint32_t          new_level,
188  void             *entry_point,
189  bool              is_fp
190)
191{
192    uint32_t     stack_high;  /* highest "stack aligned" address */
193    stack_high = ((uint32_t)(stack_base) + size);
194
195    the_context->register_sp = stack_high;
196    the_context->register_rets = (uint32_t) entry_point;
197    the_context->imask = new_level ? 0 : 0xffff;
198}
199
200
201
202/*PAGE
203 *
204 *  _CPU_Install_interrupt_stack
205 *
206 *  NO_CPU Specific Information:
207 *
208 *  XXX document implementation including references if appropriate
209 */
210
211void _CPU_Install_interrupt_stack( void )
212{
213}
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