source: rtems/cpukit/score/cpu/bfin/cpu.c @ ee29de05

4.104.114.9
Last change on this file since ee29de05 was ee29de05, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 4, 2007 at 10:19:10 PM

2007-12-04 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU Table to Configuration Table. Eliminate CPU Table from all ports. Delete references to CPU Table in all forms.
  • Property mode set to 100644
File size: 4.6 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17#include <rtems/score/bfin.h>
18#include <rtems/bfin/bfin.h>
19
20/*  _CPU_Initialize
21 *
22 *  This routine performs processor dependent initialization.
23 *
24 *  INPUT PARAMETERS:
25 *    thread_dispatch - address of disptaching routine
26 *
27 *  NO_CPU Specific Information:
28 *
29 *  XXX document implementation including references if appropriate
30 */
31
32
33void _CPU_Initialize(
34  void      (*thread_dispatch)      /* ignored on this CPU */
35)
36{
37  /*
38   *  The thread_dispatch argument is the address of the entry point
39   *  for the routine called at the end of an ISR once it has been
40   *  decided a context switch is necessary.  On some compilation
41   *  systems it is difficult to call a high-level language routine
42   *  from assembly.  This allows us to trick these systems.
43   *
44   *  If you encounter this problem save the entry point in a CPU
45   *  dependent variable.
46   */
47
48  _CPU_Thread_dispatch_pointer = thread_dispatch;
49
50  /*
51   *  If there is not an easy way to initialize the FP context
52   *  during Context_Initialize, then it is usually easier to
53   *  save an "uninitialized" FP context here and copy it to
54   *  the task's during Context_Initialize.
55   */
56
57  /* FP context initialization support goes here */
58}
59
60/*PAGE
61 *
62 *  _CPU_ISR_Get_level
63 *
64 *  NO_CPU Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68
69uint32_t   _CPU_ISR_Get_level( void )
70{
71  /*
72   *  This routine returns the current interrupt level.
73   */
74
75    register uint32_t   _tmpimask;
76
77    /*read from the IMASK registers*/
78
79    _tmpimask = *((uint32_t*)IMASK);
80
81    return _tmpimask;
82}
83
84/*PAGE
85 *
86 *  _CPU_ISR_install_raw_handler
87 *
88 *  NO_CPU Specific Information:
89 *
90 *  XXX document implementation including references if appropriate
91 */
92
93void _CPU_ISR_install_raw_handler(
94  uint32_t    vector,
95  proc_ptr    new_handler,
96  proc_ptr   *old_handler
97)
98{
99   proc_ptr *interrupt_table = NULL;
100  /*
101   *  This is where we install the interrupt handler into the "raw" interrupt
102   *  table used by the CPU to dispatch interrupt handlers.
103   */
104
105   /* base of vector table on blackfin architecture */
106   interrupt_table = (void*)0xFFE02000;
107
108   *old_handler = interrupt_table[ vector ];
109   interrupt_table[ vector ] = new_handler;
110
111}
112
113/*PAGE
114 *
115 *  _CPU_ISR_install_vector
116 *
117 *  This kernel routine installs the RTEMS handler for the
118 *  specified vector.
119 *
120 *  Input parameters:
121 *    vector      - interrupt vector number
122 *    old_handler - former ISR for this vector number
123 *    new_handler - replacement ISR for this vector number
124 *
125 *  Output parameters:  NONE
126 *
127 *
128 *  NO_CPU Specific Information:
129 *
130 *  XXX document implementation including references if appropriate
131 */
132
133void _CPU_ISR_install_vector(
134  uint32_t    vector,
135  proc_ptr    new_handler,
136  proc_ptr   *old_handler
137)
138{
139   *old_handler = _ISR_Vector_table[ vector ];
140
141   /*
142    *  If the interrupt vector table is a table of pointer to isr entry
143    *  points, then we need to install the appropriate RTEMS interrupt
144    *  handler for this vector number.
145    */
146
147   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
148
149   /*
150    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
151    *  be used by the _ISR_Handler so the user gets control.
152    */
153
154    _ISR_Vector_table[ vector ] = new_handler;
155}
156
157/*
158 * Copied from the arm port.
159 */
160void _CPU_Context_Initialize(
161  Context_Control  *the_context,
162  uint32_t         *stack_base,
163  uint32_t          size,
164  uint32_t          new_level,
165  void             *entry_point,
166  boolean           is_fp
167)
168{
169    uint32_t     stack_high;  /* highest "stack aligned" address */
170    stack_high = ((uint32_t  )(stack_base) + size);
171
172    the_context->register_sp = stack_high;
173    // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp
174    // is this correct ?????
175    the_context->register_fp = stack_high;
176    the_context->register_rets = (uint32_t) entry_point;
177
178    //mask the interrupt level
179}
180
181
182
183/*PAGE
184 *
185 *  _CPU_Install_interrupt_stack
186 *
187 *  NO_CPU Specific Information:
188 *
189 *  XXX document implementation including references if appropriate
190 */
191
192void _CPU_Install_interrupt_stack( void )
193{
194}
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