source: rtems/cpukit/score/cpu/bfin/cpu.c @ d0279f6e

4.9
Last change on this file since d0279f6e was df4fcaa, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 8, 2008 at 3:19:23 PM

2008-09-08 Joel Sherrill <joel.sherrill@…>

  • cpu.c: Remove extraneous spaces.
  • Property mode set to 100644
File size: 5.4 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17#include <rtems/score/bfin.h>
18#include <rtems/bfin/bfin.h>
19
20/*  _CPU_Initialize
21 *
22 *  This routine performs processor dependent initialization.
23 *
24 *  INPUT PARAMETERS:
25 *    thread_dispatch - address of disptaching routine
26 *
27 *  NO_CPU Specific Information:
28 *
29 *  XXX document implementation including references if appropriate
30 */
31
32
33extern void _ISR15_Handler(void);
34extern void _CPU_Emulation_handler(void);
35extern void _CPU_Reset_handler(void);
36extern void _CPU_NMI_handler(void);
37extern void _CPU_Exception_handler(void);
38extern void _CPU_Unhandled_Interrupt_handler(void);
39
40void _CPU_Initialize(
41  void      (*thread_dispatch)      /* ignored on this CPU */
42)
43{
44  /*
45   *  The thread_dispatch argument is the address of the entry point
46   *  for the routine called at the end of an ISR once it has been
47   *  decided a context switch is necessary.  On some compilation
48   *  systems it is difficult to call a high-level language routine
49   *  from assembly.  This allows us to trick these systems.
50   *
51   *  If you encounter this problem save the entry point in a CPU
52   *  dependent variable.
53   */
54
55  /*_CPU_Thread_dispatch_pointer = thread_dispatch;*/
56
57  /*
58   *  If there is not an easy way to initialize the FP context
59   *  during Context_Initialize, then it is usually easier to
60   *  save an "uninitialized" FP context here and copy it to
61   *  the task's during Context_Initialize.
62   */
63
64  /* FP context initialization support goes here */
65
66
67
68  proc_ptr ignored;
69
70#if 0
71  /* occassionally useful debug stuff */
72  int i;
73  _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
74  _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
75  _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
76  _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
77  for (i = 5; i < 15; i++)
78    _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
79#endif
80
81  /* install handler that will be used to call _Thread_Dispatch */
82  _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
83  /* enable self nesting */
84  __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
85}
86
87
88
89
90/*PAGE
91 *
92 *  _CPU_ISR_Get_level
93 *
94 *  NO_CPU Specific Information:
95 *
96 *  XXX document implementation including references if appropriate
97 */
98
99uint32_t   _CPU_ISR_Get_level( void )
100{
101  /*
102   *  This routine returns the current interrupt level.
103   */
104
105    register uint32_t   _tmpimask;
106
107    /*read from the IMASK registers*/
108
109    _tmpimask = *((uint32_t*)IMASK);
110
111    return (_tmpimask & 0xffe0) ? 0 : 1;
112}
113
114/*PAGE
115 *
116 *  _CPU_ISR_install_raw_handler
117 *
118 *  NO_CPU Specific Information:
119 *
120 *  XXX document implementation including references if appropriate
121 */
122
123void _CPU_ISR_install_raw_handler(
124  uint32_t    vector,
125  proc_ptr    new_handler,
126  proc_ptr   *old_handler
127)
128{
129   proc_ptr *interrupt_table = NULL;
130  /*
131   *  This is where we install the interrupt handler into the "raw" interrupt
132   *  table used by the CPU to dispatch interrupt handlers.
133   */
134
135   /* base of vector table on blackfin architecture */
136   interrupt_table = (void*)0xFFE02000;
137
138   *old_handler = interrupt_table[ vector ];
139   interrupt_table[ vector ] = new_handler;
140
141}
142
143/*PAGE
144 *
145 *  _CPU_ISR_install_vector
146 *
147 *  This kernel routine installs the RTEMS handler for the
148 *  specified vector.
149 *
150 *  Input parameters:
151 *    vector      - interrupt vector number
152 *    old_handler - former ISR for this vector number
153 *    new_handler - replacement ISR for this vector number
154 *
155 *  Output parameters:  NONE
156 *
157 *
158 *  NO_CPU Specific Information:
159 *
160 *  XXX document implementation including references if appropriate
161 */
162
163void _CPU_ISR_install_vector(
164  uint32_t    vector,
165  proc_ptr    new_handler,
166  proc_ptr   *old_handler
167)
168{
169   proc_ptr ignored;
170
171   *old_handler = _ISR_Vector_table[ vector ];
172
173   /*
174    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
175    *  be used by the _ISR_Handler so the user gets control.
176    */
177
178    _ISR_Vector_table[ vector ] = new_handler;
179
180    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
181}
182
183#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
184void *_CPU_Thread_Idle_body(uint32_t ignored) {
185
186    while (1) {
187        __asm__ __volatile__("ssync; idle; ssync");
188    }
189}
190#endif
191
192/*
193 * Copied from the arm port.
194 */
195void _CPU_Context_Initialize(
196  Context_Control  *the_context,
197  uint32_t         *stack_base,
198  uint32_t          size,
199  uint32_t          new_level,
200  void             *entry_point,
201  bool              is_fp
202)
203{
204    uint32_t     stack_high;  /* highest "stack aligned" address */
205    stack_high = ((uint32_t)(stack_base) + size);
206
207    the_context->register_sp = stack_high;
208    the_context->register_rets = (uint32_t) entry_point;
209    the_context->imask = new_level ? 0 : 0xffff;
210}
211
212
213
214/*PAGE
215 *
216 *  _CPU_Install_interrupt_stack
217 *
218 *  NO_CPU Specific Information:
219 *
220 *  XXX document implementation including references if appropriate
221 */
222
223void _CPU_Install_interrupt_stack( void )
224{
225}
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