source: rtems/cpukit/score/cpu/bfin/cpu.c @ 9dfd75e

4.104.114.84.9
Last change on this file since 9dfd75e was 9dfd75e, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 24, 2006 at 8:20:36 PM

2006-10-24 Alain Schaefer <alani@…>

  • Makefile.am, cpu.c, cpu_asm.S, preinstall.am, rtems/score/bfin.h: Clean up rtems/score/bfin.h removing parts that are not needed by RTEMS CPUkit to bfin specific .h files.
  • rtems/bfin/bf533.h, rtems/bfin/bfin.h: New files.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17#include <rtems/score/bfin.h>
18#include <rtems/bfin/bfin.h>
19
20/*  _CPU_Initialize
21 *
22 *  This routine performs processor dependent initialization.
23 *
24 *  INPUT PARAMETERS:
25 *    cpu_table       - CPU table to initialize
26 *    thread_dispatch - address of disptaching routine
27 *
28 *  NO_CPU Specific Information:
29 *
30 *  XXX document implementation including references if appropriate
31 */
32
33
34void _CPU_Initialize(
35  rtems_cpu_table  *cpu_table,
36  void      (*thread_dispatch)      /* ignored on this CPU */
37)
38{
39  /*
40   *  The thread_dispatch argument is the address of the entry point
41   *  for the routine called at the end of an ISR once it has been
42   *  decided a context switch is necessary.  On some compilation
43   *  systems it is difficult to call a high-level language routine
44   *  from assembly.  This allows us to trick these systems.
45   *
46   *  If you encounter this problem save the entry point in a CPU
47   *  dependent variable.
48   */
49
50  _CPU_Thread_dispatch_pointer = thread_dispatch;
51
52  /*
53   *  If there is not an easy way to initialize the FP context
54   *  during Context_Initialize, then it is usually easier to
55   *  save an "uninitialized" FP context here and copy it to
56   *  the task's during Context_Initialize.
57   */
58
59  /* FP context initialization support goes here */
60
61  _CPU_Table = *cpu_table;
62}
63
64/*PAGE
65 *
66 *  _CPU_ISR_Get_level
67 *
68 *  NO_CPU Specific Information:
69 *
70 *  XXX document implementation including references if appropriate
71 */
72
73uint32_t   _CPU_ISR_Get_level( void )
74{
75  /*
76   *  This routine returns the current interrupt level.
77   */
78
79    register uint32_t   _tmpimask;
80
81    /*read from the IMASK registers*/
82
83    _tmpimask = *((uint32_t*)IMASK);
84
85    return _tmpimask;
86}
87
88/*PAGE
89 *
90 *  _CPU_ISR_install_raw_handler
91 *
92 *  NO_CPU Specific Information:
93 *
94 *  XXX document implementation including references if appropriate
95 */
96
97void _CPU_ISR_install_raw_handler(
98  uint32_t    vector,
99  proc_ptr    new_handler,
100  proc_ptr   *old_handler
101)
102{
103   proc_ptr *interrupt_table = NULL;
104  /*
105   *  This is where we install the interrupt handler into the "raw" interrupt
106   *  table used by the CPU to dispatch interrupt handlers.
107   */
108
109   /* base of vector table on blackfin architecture */
110   interrupt_table = (void*)0xFFE02000;
111
112   *old_handler = interrupt_table[ vector ];
113   interrupt_table[ vector ] = new_handler;
114
115}
116
117/*PAGE
118 *
119 *  _CPU_ISR_install_vector
120 *
121 *  This kernel routine installs the RTEMS handler for the
122 *  specified vector.
123 *
124 *  Input parameters:
125 *    vector      - interrupt vector number
126 *    old_handler - former ISR for this vector number
127 *    new_handler - replacement ISR for this vector number
128 *
129 *  Output parameters:  NONE
130 *
131 *
132 *  NO_CPU Specific Information:
133 *
134 *  XXX document implementation including references if appropriate
135 */
136
137void _CPU_ISR_install_vector(
138  uint32_t    vector,
139  proc_ptr    new_handler,
140  proc_ptr   *old_handler
141)
142{
143   *old_handler = _ISR_Vector_table[ vector ];
144
145   /*
146    *  If the interrupt vector table is a table of pointer to isr entry
147    *  points, then we need to install the appropriate RTEMS interrupt
148    *  handler for this vector number.
149    */
150
151   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
152
153   /*
154    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
155    *  be used by the _ISR_Handler so the user gets control.
156    */
157
158    _ISR_Vector_table[ vector ] = new_handler;
159}
160
161/*
162 * Copied from the arm port.
163 */
164void _CPU_Context_Initialize(
165  Context_Control  *the_context,
166  uint32_t         *stack_base,
167  uint32_t          size,
168  uint32_t          new_level,
169  void             *entry_point,
170  boolean           is_fp
171)
172{
173    uint32_t     stack_high;  /* highest "stack aligned" address */
174    stack_high = ((uint32_t  )(stack_base) + size);
175
176    the_context->register_sp = stack_high;
177    // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp
178    // is this correct ?????
179    the_context->register_fp = stack_high;
180    the_context->register_rets = (uint32_t) entry_point;
181
182    //mask the interrupt level
183}
184
185
186
187/*PAGE
188 *
189 *  _CPU_Install_interrupt_stack
190 *
191 *  NO_CPU Specific Information:
192 *
193 *  XXX document implementation including references if appropriate
194 */
195
196void _CPU_Install_interrupt_stack( void )
197{
198}
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