source: rtems/cpukit/score/cpu/bfin/cpu.c @ 8b65b574

Last change on this file since 8b65b574 was 8b65b574, checked in by Sebastian Huber <sebastian.huber@…>, on 07/28/21 at 12:41:32

score: Canonicalize _CPU_Fatal_halt()

Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/**
2 * @file
3 *
4 * @brief Blackfin CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
9 *             written by Alain Schaefer <alain.schaefer@easc.ch>
10 *                    and Antonio Giovanini <antonio@atos.com.br>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 */
16
17#ifdef HAVE_CONFIG_H
18#include "config.h"
19#endif
20
21#include <rtems/score/cpuimpl.h>
22#include <rtems/score/isr.h>
23#include <rtems/score/bfin.h>
24#include <rtems/bfin/bfin.h>
25
26/*  _CPU_Initialize
27 *
28 *  This routine performs processor dependent initialization.
29 *
30 *  INPUT PARAMETERS: NONE
31 *
32 *  NO_CPU Specific Information:
33 *
34 *  XXX document implementation including references if appropriate
35 */
36
37
38extern void _ISR15_Handler(void);
39extern void _CPU_Emulation_handler(void);
40extern void _CPU_Reset_handler(void);
41extern void _CPU_NMI_handler(void);
42extern void _CPU_Exception_handler(void);
43extern void _CPU_Unhandled_Interrupt_handler(void);
44
45void _CPU_Initialize(void)
46{
47  /*
48   *  If there is not an easy way to initialize the FP context
49   *  during Context_Initialize, then it is usually easier to
50   *  save an "uninitialized" FP context here and copy it to
51   *  the task's during Context_Initialize.
52   */
53
54  /* FP context initialization support goes here */
55
56
57
58  CPU_ISR_raw_handler ignored;
59
60#if 0
61  /* occassionally useful debug stuff */
62  int i;
63  _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
64  _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
65  _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
66  _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
67  for (i = 5; i < 15; i++)
68    _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
69#endif
70
71  /* install handler that will be used to call _Thread_Dispatch */
72  _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
73  /* enable self nesting */
74  __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
75}
76
77void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
78{
79  __asm__ volatile ( "cli R1; R1 = %0; _halt: idle; jump _halt;"
80                     : : "r" (error) );
81}
82
83/* end of Fatal Error manager macros */
84
85
86
87
88/*
89 *  _CPU_ISR_Get_level
90 *
91 *  NO_CPU Specific Information:
92 *
93 *  XXX document implementation including references if appropriate
94 */
95
96uint32_t   _CPU_ISR_Get_level( void )
97{
98  /*
99   *  This routine returns the current interrupt level.
100   */
101
102    register uint32_t   _tmpimask;
103
104    /*read from the IMASK registers*/
105
106    _tmpimask = *((uint32_t*)IMASK);
107
108    return (_tmpimask & 0xffe0) ? 0 : 1;
109}
110
111void _CPU_ISR_install_raw_handler(
112  uint32_t             vector,
113  CPU_ISR_raw_handler  new_handler,
114  CPU_ISR_raw_handler *old_handler
115)
116{
117   CPU_ISR_raw_handler *interrupt_table;
118
119  /*
120   *  This is where we install the interrupt handler into the "raw" interrupt
121   *  table used by the CPU to dispatch interrupt handlers.
122   */
123
124   /* base of vector table on blackfin architecture */
125   interrupt_table = (void*)0xFFE02000;
126
127   *old_handler = interrupt_table[ vector ];
128   interrupt_table[ vector ] = new_handler;
129
130}
131
132void _CPU_ISR_install_vector(
133  uint32_t         vector,
134  CPU_ISR_handler  new_handler,
135  CPU_ISR_handler *old_handler
136)
137{
138   CPU_ISR_raw_handler ignored;
139
140   *old_handler = _ISR_Vector_table[ vector ];
141
142   /*
143    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
144    *  be used by the _ISR_Handler so the user gets control.
145    */
146
147    _ISR_Vector_table[ vector ] = new_handler;
148
149    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
150}
151
152void *_CPU_Thread_Idle_body(uintptr_t ignored)
153{
154  while (1) {
155    __asm__ __volatile__("ssync; idle; ssync");
156  }
157}
158
159/*
160 * Copied from the arm port.
161 */
162void _CPU_Context_Initialize(
163  Context_Control  *the_context,
164  uint32_t         *stack_base,
165  uint32_t          size,
166  uint32_t          new_level,
167  void             *entry_point,
168  bool              is_fp,
169  void             *tls_area
170)
171{
172    uint32_t     stack_high;  /* highest "stack aligned" address */
173    stack_high = ((uint32_t)(stack_base) + size);
174
175    /* blackfin abi requires caller to reserve 12 bytes on stack */
176    the_context->register_sp = stack_high - 12;
177    the_context->register_rets = (uint32_t) entry_point;
178    the_context->imask = new_level ? 0 : 0xffff;
179}
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