source: rtems/cpukit/score/cpu/bfin/cpu.c @ 5b8b467

4.104.114.84.9
Last change on this file since 5b8b467 was 5b8b467, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 23, 2006 at 5:19:52 PM

2006-10-23 Joel Sherrill <joel@…>

  • cpu.c, rtems/score/cpu.h: Use the default IDLE thread body.
  • Property mode set to 100644
File size: 4.7 KB
Line 
1/*  Blackfin CPU Dependent Source
2 *
3 *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
4 *             written by Alain Schaefer <alain.schaefer@easc.ch>
5 *                    and Antonio Giovanini <antonio@atos.com.br>
6 *
7 *  The license and distribution terms for this file may be
8 *  found in the file LICENSE in this distribution or at
9 *  http://www.rtems.com/license/LICENSE.
10 *
11 *  $Id$
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17#include <rtems/score/bfin.h>
18
19/*  _CPU_Initialize
20 *
21 *  This routine performs processor dependent initialization.
22 *
23 *  INPUT PARAMETERS:
24 *    cpu_table       - CPU table to initialize
25 *    thread_dispatch - address of disptaching routine
26 *
27 *  NO_CPU Specific Information:
28 *
29 *  XXX document implementation including references if appropriate
30 */
31
32
33void _CPU_Initialize(
34  rtems_cpu_table  *cpu_table,
35  void      (*thread_dispatch)      /* ignored on this CPU */
36)
37{
38  /*
39   *  The thread_dispatch argument is the address of the entry point
40   *  for the routine called at the end of an ISR once it has been
41   *  decided a context switch is necessary.  On some compilation
42   *  systems it is difficult to call a high-level language routine
43   *  from assembly.  This allows us to trick these systems.
44   *
45   *  If you encounter this problem save the entry point in a CPU
46   *  dependent variable.
47   */
48
49  _CPU_Thread_dispatch_pointer = thread_dispatch;
50
51  /*
52   *  If there is not an easy way to initialize the FP context
53   *  during Context_Initialize, then it is usually easier to
54   *  save an "uninitialized" FP context here and copy it to
55   *  the task's during Context_Initialize.
56   */
57
58  /* FP context initialization support goes here */
59
60  _CPU_Table = *cpu_table;
61}
62
63/*PAGE
64 *
65 *  _CPU_ISR_Get_level
66 *
67 *  NO_CPU Specific Information:
68 *
69 *  XXX document implementation including references if appropriate
70 */
71
72uint32_t   _CPU_ISR_Get_level( void )
73{
74  /*
75   *  This routine returns the current interrupt level.
76   */
77
78    register uint32_t   _tmpimask;
79
80    /*read from the IMASK registers*/
81
82    _tmpimask = *((uint32_t*)IMASK);
83
84    return _tmpimask;
85}
86
87/*PAGE
88 *
89 *  _CPU_ISR_install_raw_handler
90 *
91 *  NO_CPU Specific Information:
92 *
93 *  XXX document implementation including references if appropriate
94 */
95
96void _CPU_ISR_install_raw_handler(
97  uint32_t    vector,
98  proc_ptr    new_handler,
99  proc_ptr   *old_handler
100)
101{
102   proc_ptr *interrupt_table = NULL;
103  /*
104   *  This is where we install the interrupt handler into the "raw" interrupt
105   *  table used by the CPU to dispatch interrupt handlers.
106   */
107
108   /* base of vector table on blackfin architecture */
109   interrupt_table = (void*)0xFFE02000;
110
111   *old_handler = interrupt_table[ vector ];
112   interrupt_table[ vector ] = new_handler;
113
114}
115
116/*PAGE
117 *
118 *  _CPU_ISR_install_vector
119 *
120 *  This kernel routine installs the RTEMS handler for the
121 *  specified vector.
122 *
123 *  Input parameters:
124 *    vector      - interrupt vector number
125 *    old_handler - former ISR for this vector number
126 *    new_handler - replacement ISR for this vector number
127 *
128 *  Output parameters:  NONE
129 *
130 *
131 *  NO_CPU Specific Information:
132 *
133 *  XXX document implementation including references if appropriate
134 */
135
136void _CPU_ISR_install_vector(
137  uint32_t    vector,
138  proc_ptr    new_handler,
139  proc_ptr   *old_handler
140)
141{
142   *old_handler = _ISR_Vector_table[ vector ];
143
144   /*
145    *  If the interrupt vector table is a table of pointer to isr entry
146    *  points, then we need to install the appropriate RTEMS interrupt
147    *  handler for this vector number.
148    */
149
150   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
151
152   /*
153    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
154    *  be used by the _ISR_Handler so the user gets control.
155    */
156
157    _ISR_Vector_table[ vector ] = new_handler;
158}
159
160/*
161 * Copied from the arm port.
162 */
163void _CPU_Context_Initialize(
164  Context_Control  *the_context,
165  uint32_t         *stack_base,
166  uint32_t          size,
167  uint32_t          new_level,
168  void             *entry_point,
169  boolean           is_fp
170)
171{
172    uint32_t     stack_high;  /* highest "stack aligned" address */
173    stack_high = ((uint32_t  )(stack_base) + size);
174
175    the_context->register_sp = stack_high;
176    // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp
177    // is this correct ?????
178    the_context->register_fp = stack_high;
179    the_context->register_rets = (uint32_t) entry_point;
180
181    //mask the interrupt level
182}
183
184
185
186/*PAGE
187 *
188 *  _CPU_Install_interrupt_stack
189 *
190 *  NO_CPU Specific Information:
191 *
192 *  XXX document implementation including references if appropriate
193 */
194
195void _CPU_Install_interrupt_stack( void )
196{
197}
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