source: rtems/cpukit/score/cpu/bfin/cpu.c @ 511dc4b

5
Last change on this file since 511dc4b was 511dc4b, checked in by Sebastian Huber <sebastian.huber@…>, on 06/19/18 at 07:09:51

Rework initialization and interrupt stack support

Statically initialize the interrupt stack area
(_Configuration_Interrupt_stack_area_begin,
_Configuration_Interrupt_stack_area_end, and
_Configuration_Interrupt_stack_size) via <rtems/confdefs.h>. Place the
interrupt stack area in a special section ".rtemsstack.interrupt". Let
BSPs define the optimal placement of this section in their linker
command files (e.g. in a fast on-chip memory).

This change makes makes the CPU_HAS_SOFTWARE_INTERRUPT_STACK and
CPU_HAS_HARDWARE_INTERRUPT_STACK CPU port defines superfluous, since the
low level initialization code has all information available via global
symbols.

This change makes the CPU_ALLOCATE_INTERRUPT_STACK CPU port define
superfluous, since the interrupt stacks are allocated by confdefs.h for
all architectures. There is no need for BSP-specific linker command
file magic (except the section placement), see previous ARM linker
command file as a bad example.

Remove _CPU_Install_interrupt_stack(). Initialize the hardware
interrupt stack in _CPU_Initialize() if necessary (e.g.
m68k_install_interrupt_stack()).

The optional _CPU_Interrupt_stack_setup() is still useful to customize
the registration of the interrupt stack area in the per-CPU information.

The initialization stack can reuse the interrupt stack, since

  • interrupts are disabled during the sequential system initialization, and
  • the boot_card() function does not return.

This stack resuse saves memory.

Changes per architecture:

arm:

  • Mostly replace the linker symbol based configuration of stacks with the standard <rtems/confdefs.h> configuration via CONFIGURE_INTERRUPT_STACK_SIZE. The size of the FIQ, ABT and UND mode stack is still defined via linker symbols. These modes are rarely used in applications and the default values provided by the BSP should be sufficient in most cases.
  • Remove the bsp_processor_count linker symbol hack used for the SMP support. This is possible since the interrupt stack area is now allocated by the linker and not allocated from the heap. This makes some configure.ac stuff obsolete. Remove the now superfluous BSP variants altcycv_devkit_smp and realview_pbx_a9_qemu_smp.

bfin:

  • Remove unused magic linker command file allocation of initialization stack. Maybe a previous linker command file copy and paste problem? In the start.S the initialization stack is set to a hard coded value.

lm32, m32c, mips, nios2, riscv, sh, v850:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

m68k:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.

powerpc:

  • Remove magic linker command file allocation of initialization stack. Reuse interrupt stack for initialization stack.
  • Used dedicated memory region (REGION_RTEMSSTACK) for the interrupt stack on BSPs using the shared linkcmds.base (replacement for REGION_RWEXTRA).

sparc:

  • Remove the hard coded initialization stack. Use the interrupt stack for the initialization stack on the boot processor. This saves 16KiB of RAM.

Update #3459.

  • Property mode set to 100644
File size: 4.7 KB
Line 
1/**
2 * @file
3 *
4 * @brief Blackfin CPU Dependent Source
5 */
6
7/*
8 *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
9 *             written by Alain Schaefer <alain.schaefer@easc.ch>
10 *                    and Antonio Giovanini <antonio@atos.com.br>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 */
16
17#ifdef HAVE_CONFIG_H
18#include "config.h"
19#endif
20
21#include <rtems/system.h>
22#include <rtems/score/isr.h>
23#include <rtems/score/wkspace.h>
24#include <rtems/score/bfin.h>
25#include <rtems/bfin/bfin.h>
26
27/*  _CPU_Initialize
28 *
29 *  This routine performs processor dependent initialization.
30 *
31 *  INPUT PARAMETERS: NONE
32 *
33 *  NO_CPU Specific Information:
34 *
35 *  XXX document implementation including references if appropriate
36 */
37
38
39extern void _ISR15_Handler(void);
40extern void _CPU_Emulation_handler(void);
41extern void _CPU_Reset_handler(void);
42extern void _CPU_NMI_handler(void);
43extern void _CPU_Exception_handler(void);
44extern void _CPU_Unhandled_Interrupt_handler(void);
45
46void _CPU_Initialize(void)
47{
48  /*
49   *  If there is not an easy way to initialize the FP context
50   *  during Context_Initialize, then it is usually easier to
51   *  save an "uninitialized" FP context here and copy it to
52   *  the task's during Context_Initialize.
53   */
54
55  /* FP context initialization support goes here */
56
57
58
59  proc_ptr ignored;
60
61#if 0
62  /* occassionally useful debug stuff */
63  int i;
64  _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored);
65  _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored);
66  _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored);
67  _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored);
68  for (i = 5; i < 15; i++)
69    _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored);
70#endif
71
72  /* install handler that will be used to call _Thread_Dispatch */
73  _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored );
74  /* enable self nesting */
75  __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004));
76}
77
78
79
80
81/*
82 *  _CPU_ISR_Get_level
83 *
84 *  NO_CPU Specific Information:
85 *
86 *  XXX document implementation including references if appropriate
87 */
88
89uint32_t   _CPU_ISR_Get_level( void )
90{
91  /*
92   *  This routine returns the current interrupt level.
93   */
94
95    register uint32_t   _tmpimask;
96
97    /*read from the IMASK registers*/
98
99    _tmpimask = *((uint32_t*)IMASK);
100
101    return (_tmpimask & 0xffe0) ? 0 : 1;
102}
103
104/*
105 *  _CPU_ISR_install_raw_handler
106 *
107 *  NO_CPU Specific Information:
108 *
109 *  XXX document implementation including references if appropriate
110 */
111
112void _CPU_ISR_install_raw_handler(
113  uint32_t    vector,
114  proc_ptr    new_handler,
115  proc_ptr   *old_handler
116)
117{
118   proc_ptr *interrupt_table = NULL;
119  /*
120   *  This is where we install the interrupt handler into the "raw" interrupt
121   *  table used by the CPU to dispatch interrupt handlers.
122   */
123
124   /* base of vector table on blackfin architecture */
125   interrupt_table = (void*)0xFFE02000;
126
127   *old_handler = interrupt_table[ vector ];
128   interrupt_table[ vector ] = new_handler;
129
130}
131
132/*
133 *  _CPU_ISR_install_vector
134 *
135 *  This kernel routine installs the RTEMS handler for the
136 *  specified vector.
137 *
138 *  Input parameters:
139 *    vector      - interrupt vector number
140 *    old_handler - former ISR for this vector number
141 *    new_handler - replacement ISR for this vector number
142 *
143 *  Output parameters:  NONE
144 *
145 *
146 *  NO_CPU Specific Information:
147 *
148 *  XXX document implementation including references if appropriate
149 */
150
151void _CPU_ISR_install_vector(
152  uint32_t    vector,
153  proc_ptr    new_handler,
154  proc_ptr   *old_handler
155)
156{
157   proc_ptr ignored;
158
159   *old_handler = _ISR_Vector_table[ vector ];
160
161   /*
162    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
163    *  be used by the _ISR_Handler so the user gets control.
164    */
165
166    _ISR_Vector_table[ vector ] = new_handler;
167
168    _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
169}
170
171#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
172void *_CPU_Thread_Idle_body(uint32_t ignored)
173{
174  while (1) {
175    __asm__ __volatile__("ssync; idle; ssync");
176  }
177}
178#endif
179
180/*
181 * Copied from the arm port.
182 */
183void _CPU_Context_Initialize(
184  Context_Control  *the_context,
185  uint32_t         *stack_base,
186  uint32_t          size,
187  uint32_t          new_level,
188  void             *entry_point,
189  bool              is_fp,
190  void             *tls_area
191)
192{
193    uint32_t     stack_high;  /* highest "stack aligned" address */
194    stack_high = ((uint32_t)(stack_base) + size);
195
196    /* blackfin abi requires caller to reserve 12 bytes on stack */
197    the_context->register_sp = stack_high - 12;
198    the_context->register_rets = (uint32_t) entry_point;
199    the_context->imask = new_level ? 0 : 0xffff;
200}
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