[d9a6ab3] | 1 | /* Blackfin CPU Dependent Source |
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| 2 | * |
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| 3 | * Copyright (c) 2006 by Atos Automacao Industrial Ltda. |
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| 4 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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| 5 | * and Antonio Giovanini <antonio@atos.com.br> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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| 15 | #include <rtems/score/isr.h> |
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| 16 | #include <rtems/score/wkspace.h> |
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| 17 | #include <rtems/score/bfin.h> |
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[9dfd75e] | 18 | #include <rtems/bfin/bfin.h> |
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[d9a6ab3] | 19 | |
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| 20 | /* _CPU_Initialize |
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| 21 | * |
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| 22 | * This routine performs processor dependent initialization. |
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| 23 | * |
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| 24 | * INPUT PARAMETERS: |
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| 25 | * cpu_table - CPU table to initialize |
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| 26 | * thread_dispatch - address of disptaching routine |
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| 27 | * |
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| 28 | * NO_CPU Specific Information: |
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| 29 | * |
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| 30 | * XXX document implementation including references if appropriate |
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| 31 | */ |
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| 32 | |
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| 33 | |
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| 34 | void _CPU_Initialize( |
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| 35 | rtems_cpu_table *cpu_table, |
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| 36 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 37 | ) |
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| 38 | { |
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| 39 | /* |
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| 40 | * The thread_dispatch argument is the address of the entry point |
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| 41 | * for the routine called at the end of an ISR once it has been |
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| 42 | * decided a context switch is necessary. On some compilation |
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| 43 | * systems it is difficult to call a high-level language routine |
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| 44 | * from assembly. This allows us to trick these systems. |
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| 45 | * |
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| 46 | * If you encounter this problem save the entry point in a CPU |
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| 47 | * dependent variable. |
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| 48 | */ |
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| 49 | |
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| 50 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 51 | |
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| 52 | /* |
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| 53 | * If there is not an easy way to initialize the FP context |
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| 54 | * during Context_Initialize, then it is usually easier to |
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| 55 | * save an "uninitialized" FP context here and copy it to |
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| 56 | * the task's during Context_Initialize. |
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| 57 | */ |
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| 58 | |
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| 59 | /* FP context initialization support goes here */ |
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| 60 | } |
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| 61 | |
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| 62 | /*PAGE |
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| 63 | * |
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| 64 | * _CPU_ISR_Get_level |
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| 65 | * |
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| 66 | * NO_CPU Specific Information: |
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| 67 | * |
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| 68 | * XXX document implementation including references if appropriate |
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| 69 | */ |
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| 70 | |
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| 71 | uint32_t _CPU_ISR_Get_level( void ) |
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| 72 | { |
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| 73 | /* |
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| 74 | * This routine returns the current interrupt level. |
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| 75 | */ |
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| 76 | |
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| 77 | register uint32_t _tmpimask; |
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| 78 | |
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| 79 | /*read from the IMASK registers*/ |
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| 80 | |
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| 81 | _tmpimask = *((uint32_t*)IMASK); |
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| 82 | |
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| 83 | return _tmpimask; |
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| 84 | } |
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| 85 | |
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| 86 | /*PAGE |
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| 87 | * |
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| 88 | * _CPU_ISR_install_raw_handler |
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| 89 | * |
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| 90 | * NO_CPU Specific Information: |
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| 91 | * |
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| 92 | * XXX document implementation including references if appropriate |
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| 93 | */ |
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| 94 | |
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| 95 | void _CPU_ISR_install_raw_handler( |
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| 96 | uint32_t vector, |
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| 97 | proc_ptr new_handler, |
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| 98 | proc_ptr *old_handler |
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| 99 | ) |
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| 100 | { |
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| 101 | proc_ptr *interrupt_table = NULL; |
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| 102 | /* |
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| 103 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 104 | * table used by the CPU to dispatch interrupt handlers. |
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| 105 | */ |
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| 106 | |
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| 107 | /* base of vector table on blackfin architecture */ |
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| 108 | interrupt_table = (void*)0xFFE02000; |
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| 109 | |
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| 110 | *old_handler = interrupt_table[ vector ]; |
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| 111 | interrupt_table[ vector ] = new_handler; |
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| 112 | |
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| 113 | } |
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| 114 | |
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| 115 | /*PAGE |
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| 116 | * |
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| 117 | * _CPU_ISR_install_vector |
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| 118 | * |
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| 119 | * This kernel routine installs the RTEMS handler for the |
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| 120 | * specified vector. |
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| 121 | * |
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| 122 | * Input parameters: |
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| 123 | * vector - interrupt vector number |
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| 124 | * old_handler - former ISR for this vector number |
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| 125 | * new_handler - replacement ISR for this vector number |
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| 126 | * |
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| 127 | * Output parameters: NONE |
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| 128 | * |
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| 129 | * |
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| 130 | * NO_CPU Specific Information: |
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| 131 | * |
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| 132 | * XXX document implementation including references if appropriate |
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| 133 | */ |
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| 134 | |
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| 135 | void _CPU_ISR_install_vector( |
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| 136 | uint32_t vector, |
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| 137 | proc_ptr new_handler, |
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| 138 | proc_ptr *old_handler |
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| 139 | ) |
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| 140 | { |
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| 141 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 142 | |
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| 143 | /* |
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| 144 | * If the interrupt vector table is a table of pointer to isr entry |
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| 145 | * points, then we need to install the appropriate RTEMS interrupt |
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| 146 | * handler for this vector number. |
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| 147 | */ |
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| 148 | |
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| 149 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler ); |
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| 150 | |
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| 151 | /* |
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| 152 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 153 | * be used by the _ISR_Handler so the user gets control. |
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| 154 | */ |
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| 155 | |
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| 156 | _ISR_Vector_table[ vector ] = new_handler; |
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| 157 | } |
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| 158 | |
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| 159 | /* |
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| 160 | * Copied from the arm port. |
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| 161 | */ |
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| 162 | void _CPU_Context_Initialize( |
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| 163 | Context_Control *the_context, |
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| 164 | uint32_t *stack_base, |
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| 165 | uint32_t size, |
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| 166 | uint32_t new_level, |
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| 167 | void *entry_point, |
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| 168 | boolean is_fp |
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| 169 | ) |
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| 170 | { |
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| 171 | uint32_t stack_high; /* highest "stack aligned" address */ |
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| 172 | stack_high = ((uint32_t )(stack_base) + size); |
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| 173 | |
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| 174 | the_context->register_sp = stack_high; |
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| 175 | // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp |
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| 176 | // is this correct ????? |
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| 177 | the_context->register_fp = stack_high; |
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| 178 | the_context->register_rets = (uint32_t) entry_point; |
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| 179 | |
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| 180 | //mask the interrupt level |
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| 181 | } |
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| 182 | |
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| 183 | |
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| 184 | |
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| 185 | /*PAGE |
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| 186 | * |
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| 187 | * _CPU_Install_interrupt_stack |
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| 188 | * |
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| 189 | * NO_CPU Specific Information: |
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| 190 | * |
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| 191 | * XXX document implementation including references if appropriate |
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| 192 | */ |
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| 193 | |
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| 194 | void _CPU_Install_interrupt_stack( void ) |
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| 195 | { |
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| 196 | } |
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