[43e0599] | 1 | /** |
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| 2 | * @file |
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[d9a6ab3] | 3 | * |
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[43e0599] | 4 | * @brief Blackfin CPU Dependent Source |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[fe834391] | 8 | * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. |
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[d9a6ab3] | 9 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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| 10 | * and Antonio Giovanini <antonio@atos.com.br> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[c499856] | 14 | * http://www.rtems.org/license/LICENSE. |
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[d9a6ab3] | 15 | */ |
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| 16 | |
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[ff8dd26] | 17 | #ifdef HAVE_CONFIG_H |
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| 18 | #include "config.h" |
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| 19 | #endif |
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| 20 | |
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[d9a6ab3] | 21 | #include <rtems/system.h> |
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| 22 | #include <rtems/score/isr.h> |
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| 23 | #include <rtems/score/wkspace.h> |
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| 24 | #include <rtems/score/bfin.h> |
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[9dfd75e] | 25 | #include <rtems/bfin/bfin.h> |
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[d9a6ab3] | 26 | |
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| 27 | /* _CPU_Initialize |
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| 28 | * |
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| 29 | * This routine performs processor dependent initialization. |
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| 30 | * |
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[c03e2bc] | 31 | * INPUT PARAMETERS: NONE |
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[d9a6ab3] | 32 | * |
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| 33 | * NO_CPU Specific Information: |
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| 34 | * |
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| 35 | * XXX document implementation including references if appropriate |
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| 36 | */ |
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| 37 | |
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| 38 | |
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[4daebbd] | 39 | extern void _ISR15_Handler(void); |
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| 40 | extern void _CPU_Emulation_handler(void); |
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| 41 | extern void _CPU_Reset_handler(void); |
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| 42 | extern void _CPU_NMI_handler(void); |
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| 43 | extern void _CPU_Exception_handler(void); |
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| 44 | extern void _CPU_Unhandled_Interrupt_handler(void); |
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| 45 | |
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[c03e2bc] | 46 | void _CPU_Initialize(void) |
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[d9a6ab3] | 47 | { |
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| 48 | /* |
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| 49 | * If there is not an easy way to initialize the FP context |
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| 50 | * during Context_Initialize, then it is usually easier to |
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| 51 | * save an "uninitialized" FP context here and copy it to |
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| 52 | * the task's during Context_Initialize. |
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| 53 | */ |
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| 54 | |
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| 55 | /* FP context initialization support goes here */ |
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[4daebbd] | 56 | |
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| 57 | |
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| 58 | |
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| 59 | proc_ptr ignored; |
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| 60 | |
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| 61 | #if 0 |
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| 62 | /* occassionally useful debug stuff */ |
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| 63 | int i; |
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| 64 | _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored); |
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| 65 | _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored); |
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| 66 | _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored); |
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| 67 | _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored); |
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| 68 | for (i = 5; i < 15; i++) |
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| 69 | _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored); |
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| 70 | #endif |
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| 71 | |
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| 72 | /* install handler that will be used to call _Thread_Dispatch */ |
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| 73 | _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored ); |
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| 74 | /* enable self nesting */ |
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| 75 | __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004)); |
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[d9a6ab3] | 76 | } |
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| 77 | |
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[4daebbd] | 78 | |
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| 79 | |
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| 80 | |
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[ce02cc0] | 81 | /* |
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[d9a6ab3] | 82 | * _CPU_ISR_Get_level |
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| 83 | * |
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| 84 | * NO_CPU Specific Information: |
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| 85 | * |
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| 86 | * XXX document implementation including references if appropriate |
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| 87 | */ |
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| 88 | |
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| 89 | uint32_t _CPU_ISR_Get_level( void ) |
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| 90 | { |
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| 91 | /* |
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| 92 | * This routine returns the current interrupt level. |
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| 93 | */ |
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| 94 | |
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| 95 | register uint32_t _tmpimask; |
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| 96 | |
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| 97 | /*read from the IMASK registers*/ |
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| 98 | |
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| 99 | _tmpimask = *((uint32_t*)IMASK); |
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| 100 | |
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[4daebbd] | 101 | return (_tmpimask & 0xffe0) ? 0 : 1; |
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[d9a6ab3] | 102 | } |
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| 103 | |
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[ce02cc0] | 104 | /* |
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[d9a6ab3] | 105 | * _CPU_ISR_install_raw_handler |
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| 106 | * |
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| 107 | * NO_CPU Specific Information: |
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| 108 | * |
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| 109 | * XXX document implementation including references if appropriate |
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| 110 | */ |
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| 111 | |
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| 112 | void _CPU_ISR_install_raw_handler( |
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| 113 | uint32_t vector, |
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| 114 | proc_ptr new_handler, |
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| 115 | proc_ptr *old_handler |
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| 116 | ) |
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| 117 | { |
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| 118 | proc_ptr *interrupt_table = NULL; |
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| 119 | /* |
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| 120 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 121 | * table used by the CPU to dispatch interrupt handlers. |
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| 122 | */ |
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| 123 | |
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| 124 | /* base of vector table on blackfin architecture */ |
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| 125 | interrupt_table = (void*)0xFFE02000; |
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| 126 | |
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| 127 | *old_handler = interrupt_table[ vector ]; |
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| 128 | interrupt_table[ vector ] = new_handler; |
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| 129 | |
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| 130 | } |
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| 131 | |
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[ce02cc0] | 132 | /* |
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[d9a6ab3] | 133 | * _CPU_ISR_install_vector |
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| 134 | * |
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| 135 | * This kernel routine installs the RTEMS handler for the |
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| 136 | * specified vector. |
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| 137 | * |
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| 138 | * Input parameters: |
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| 139 | * vector - interrupt vector number |
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| 140 | * old_handler - former ISR for this vector number |
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| 141 | * new_handler - replacement ISR for this vector number |
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| 142 | * |
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| 143 | * Output parameters: NONE |
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| 144 | * |
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| 145 | * |
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| 146 | * NO_CPU Specific Information: |
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| 147 | * |
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| 148 | * XXX document implementation including references if appropriate |
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| 149 | */ |
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| 150 | |
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| 151 | void _CPU_ISR_install_vector( |
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| 152 | uint32_t vector, |
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| 153 | proc_ptr new_handler, |
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| 154 | proc_ptr *old_handler |
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| 155 | ) |
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| 156 | { |
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[4daebbd] | 157 | proc_ptr ignored; |
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[d9a6ab3] | 158 | |
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[4daebbd] | 159 | *old_handler = _ISR_Vector_table[ vector ]; |
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[d9a6ab3] | 160 | |
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| 161 | /* |
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| 162 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 163 | * be used by the _ISR_Handler so the user gets control. |
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| 164 | */ |
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| 165 | |
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| 166 | _ISR_Vector_table[ vector ] = new_handler; |
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[4daebbd] | 167 | |
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| 168 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[d9a6ab3] | 169 | } |
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| 170 | |
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[4daebbd] | 171 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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[cca8379] | 172 | void *_CPU_Thread_Idle_body(uint32_t ignored) |
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| 173 | { |
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| 174 | while (1) { |
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| 175 | __asm__ __volatile__("ssync; idle; ssync"); |
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| 176 | } |
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[4daebbd] | 177 | } |
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| 178 | #endif |
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| 179 | |
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[d9a6ab3] | 180 | /* |
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| 181 | * Copied from the arm port. |
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| 182 | */ |
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| 183 | void _CPU_Context_Initialize( |
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| 184 | Context_Control *the_context, |
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| 185 | uint32_t *stack_base, |
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| 186 | uint32_t size, |
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| 187 | uint32_t new_level, |
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| 188 | void *entry_point, |
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[022851a] | 189 | bool is_fp, |
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| 190 | void *tls_area |
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[d9a6ab3] | 191 | ) |
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| 192 | { |
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| 193 | uint32_t stack_high; /* highest "stack aligned" address */ |
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[df4fcaa] | 194 | stack_high = ((uint32_t)(stack_base) + size); |
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[d9a6ab3] | 195 | |
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[dace69bf] | 196 | /* blackfin abi requires caller to reserve 12 bytes on stack */ |
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| 197 | the_context->register_sp = stack_high - 12; |
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[d9a6ab3] | 198 | the_context->register_rets = (uint32_t) entry_point; |
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[4daebbd] | 199 | the_context->imask = new_level ? 0 : 0xffff; |
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[d9a6ab3] | 200 | } |
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