[d9a6ab3] | 1 | /* Blackfin CPU Dependent Source |
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| 2 | * |
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[fe834391] | 3 | * COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda. |
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[d9a6ab3] | 4 | * written by Alain Schaefer <alain.schaefer@easc.ch> |
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| 5 | * and Antonio Giovanini <antonio@atos.com.br> |
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| 6 | * |
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| 7 | * The license and distribution terms for this file may be |
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| 8 | * found in the file LICENSE in this distribution or at |
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| 9 | * http://www.rtems.com/license/LICENSE. |
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| 10 | * |
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| 11 | * $Id$ |
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| 12 | */ |
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| 13 | |
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| 14 | #include <rtems/system.h> |
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| 15 | #include <rtems/score/isr.h> |
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| 16 | #include <rtems/score/wkspace.h> |
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| 17 | #include <rtems/score/bfin.h> |
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[9dfd75e] | 18 | #include <rtems/bfin/bfin.h> |
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[d9a6ab3] | 19 | |
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| 20 | /* _CPU_Initialize |
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| 21 | * |
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| 22 | * This routine performs processor dependent initialization. |
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| 23 | * |
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| 24 | * INPUT PARAMETERS: |
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| 25 | * thread_dispatch - address of disptaching routine |
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| 26 | * |
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| 27 | * NO_CPU Specific Information: |
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| 28 | * |
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| 29 | * XXX document implementation including references if appropriate |
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| 30 | */ |
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| 31 | |
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| 32 | |
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[4daebbd] | 33 | extern void _ISR15_Handler(void); |
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| 34 | extern void _CPU_Emulation_handler(void); |
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| 35 | extern void _CPU_Reset_handler(void); |
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| 36 | extern void _CPU_NMI_handler(void); |
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| 37 | extern void _CPU_Exception_handler(void); |
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| 38 | extern void _CPU_Unhandled_Interrupt_handler(void); |
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| 39 | |
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[d9a6ab3] | 40 | void _CPU_Initialize( |
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| 41 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 42 | ) |
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| 43 | { |
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| 44 | /* |
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| 45 | * The thread_dispatch argument is the address of the entry point |
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| 46 | * for the routine called at the end of an ISR once it has been |
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| 47 | * decided a context switch is necessary. On some compilation |
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| 48 | * systems it is difficult to call a high-level language routine |
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| 49 | * from assembly. This allows us to trick these systems. |
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| 50 | * |
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| 51 | * If you encounter this problem save the entry point in a CPU |
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| 52 | * dependent variable. |
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| 53 | */ |
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| 54 | |
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[4daebbd] | 55 | /*_CPU_Thread_dispatch_pointer = thread_dispatch;*/ |
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[d9a6ab3] | 56 | |
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| 57 | /* |
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| 58 | * If there is not an easy way to initialize the FP context |
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| 59 | * during Context_Initialize, then it is usually easier to |
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| 60 | * save an "uninitialized" FP context here and copy it to |
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| 61 | * the task's during Context_Initialize. |
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| 62 | */ |
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| 63 | |
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| 64 | /* FP context initialization support goes here */ |
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[4daebbd] | 65 | |
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| 66 | |
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| 67 | |
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| 68 | proc_ptr ignored; |
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| 69 | |
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| 70 | #if 0 |
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| 71 | /* occassionally useful debug stuff */ |
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| 72 | int i; |
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| 73 | _CPU_ISR_install_raw_handler(0, _CPU_Emulation_handler, &ignored); |
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| 74 | _CPU_ISR_install_raw_handler(1, _CPU_Reset_handler, &ignored); |
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| 75 | _CPU_ISR_install_raw_handler(2, _CPU_NMI_handler, &ignored); |
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| 76 | _CPU_ISR_install_raw_handler(3, _CPU_Exception_handler, &ignored); |
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| 77 | for (i = 5; i < 15; i++) |
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| 78 | _CPU_ISR_install_raw_handler(i, _CPU_Unhandled_Interrupt_handler, &ignored); |
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| 79 | #endif |
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| 80 | |
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| 81 | /* install handler that will be used to call _Thread_Dispatch */ |
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| 82 | _CPU_ISR_install_raw_handler( 15, _ISR15_Handler, &ignored ); |
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| 83 | /* enable self nesting */ |
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| 84 | __asm__ __volatile__ ("syscfg = %0" : : "d" (0x00000004)); |
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[d9a6ab3] | 85 | } |
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| 86 | |
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[4daebbd] | 87 | |
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| 88 | |
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| 89 | |
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[d9a6ab3] | 90 | /*PAGE |
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| 91 | * |
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| 92 | * _CPU_ISR_Get_level |
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| 93 | * |
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| 94 | * NO_CPU Specific Information: |
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| 95 | * |
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| 96 | * XXX document implementation including references if appropriate |
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| 97 | */ |
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| 98 | |
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| 99 | uint32_t _CPU_ISR_Get_level( void ) |
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| 100 | { |
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| 101 | /* |
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| 102 | * This routine returns the current interrupt level. |
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| 103 | */ |
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| 104 | |
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| 105 | register uint32_t _tmpimask; |
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| 106 | |
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| 107 | /*read from the IMASK registers*/ |
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| 108 | |
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| 109 | _tmpimask = *((uint32_t*)IMASK); |
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| 110 | |
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[4daebbd] | 111 | return (_tmpimask & 0xffe0) ? 0 : 1; |
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[d9a6ab3] | 112 | } |
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| 113 | |
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| 114 | /*PAGE |
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| 115 | * |
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| 116 | * _CPU_ISR_install_raw_handler |
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| 117 | * |
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| 118 | * NO_CPU Specific Information: |
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| 119 | * |
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| 120 | * XXX document implementation including references if appropriate |
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| 121 | */ |
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| 122 | |
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| 123 | void _CPU_ISR_install_raw_handler( |
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| 124 | uint32_t vector, |
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| 125 | proc_ptr new_handler, |
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| 126 | proc_ptr *old_handler |
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| 127 | ) |
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| 128 | { |
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| 129 | proc_ptr *interrupt_table = NULL; |
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| 130 | /* |
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| 131 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 132 | * table used by the CPU to dispatch interrupt handlers. |
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| 133 | */ |
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| 134 | |
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| 135 | /* base of vector table on blackfin architecture */ |
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| 136 | interrupt_table = (void*)0xFFE02000; |
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| 137 | |
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| 138 | *old_handler = interrupt_table[ vector ]; |
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| 139 | interrupt_table[ vector ] = new_handler; |
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| 140 | |
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| 141 | } |
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| 142 | |
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| 143 | /*PAGE |
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| 144 | * |
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| 145 | * _CPU_ISR_install_vector |
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| 146 | * |
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| 147 | * This kernel routine installs the RTEMS handler for the |
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| 148 | * specified vector. |
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| 149 | * |
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| 150 | * Input parameters: |
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| 151 | * vector - interrupt vector number |
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| 152 | * old_handler - former ISR for this vector number |
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| 153 | * new_handler - replacement ISR for this vector number |
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| 154 | * |
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| 155 | * Output parameters: NONE |
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| 156 | * |
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| 157 | * |
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| 158 | * NO_CPU Specific Information: |
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| 159 | * |
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| 160 | * XXX document implementation including references if appropriate |
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| 161 | */ |
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| 162 | |
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| 163 | void _CPU_ISR_install_vector( |
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| 164 | uint32_t vector, |
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| 165 | proc_ptr new_handler, |
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| 166 | proc_ptr *old_handler |
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| 167 | ) |
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| 168 | { |
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[4daebbd] | 169 | proc_ptr ignored; |
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[d9a6ab3] | 170 | |
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[4daebbd] | 171 | *old_handler = _ISR_Vector_table[ vector ]; |
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[d9a6ab3] | 172 | |
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| 173 | /* |
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| 174 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 175 | * be used by the _ISR_Handler so the user gets control. |
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| 176 | */ |
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| 177 | |
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| 178 | _ISR_Vector_table[ vector ] = new_handler; |
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[4daebbd] | 179 | |
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| 180 | _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored ); |
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[d9a6ab3] | 181 | } |
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| 182 | |
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[4daebbd] | 183 | #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE) |
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| 184 | void *_CPU_Thread_Idle_body(uint32_t ignored) { |
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| 185 | |
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| 186 | while (1) { |
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| 187 | __asm__ __volatile__("ssync; idle; ssync"); |
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| 188 | } |
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| 189 | } |
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| 190 | #endif |
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| 191 | |
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[d9a6ab3] | 192 | /* |
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| 193 | * Copied from the arm port. |
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| 194 | */ |
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| 195 | void _CPU_Context_Initialize( |
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| 196 | Context_Control *the_context, |
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| 197 | uint32_t *stack_base, |
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| 198 | uint32_t size, |
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| 199 | uint32_t new_level, |
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| 200 | void *entry_point, |
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| 201 | boolean is_fp |
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| 202 | ) |
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| 203 | { |
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| 204 | uint32_t stack_high; /* highest "stack aligned" address */ |
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| 205 | stack_high = ((uint32_t )(stack_base) + size); |
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| 206 | |
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| 207 | the_context->register_sp = stack_high; |
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| 208 | the_context->register_rets = (uint32_t) entry_point; |
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[4daebbd] | 209 | the_context->imask = new_level ? 0 : 0xffff; |
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[d9a6ab3] | 210 | } |
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| 211 | |
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| 212 | |
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| 213 | |
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| 214 | /*PAGE |
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| 215 | * |
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| 216 | * _CPU_Install_interrupt_stack |
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| 217 | * |
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| 218 | * NO_CPU Specific Information: |
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| 219 | * |
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| 220 | * XXX document implementation including references if appropriate |
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| 221 | */ |
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| 222 | |
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| 223 | void _CPU_Install_interrupt_stack( void ) |
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| 224 | { |
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| 225 | } |
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