source: rtems/cpukit/score/cpu/avr/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 35.6 KB
Line 
1/**
2 * @file
3 *
4 * @brief Intel AVR CPU Department Source
5 *
6 * This include file contains information pertaining to the AVR
7 * processor.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2006.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/avr.h>
28#include <avr/common.h>
29
30/* conditional compilation parameters */
31
32#ifndef RTEMS_USE_16_BIT_OBJECT
33#define RTEMS_USE_16_BIT_OBJECT
34#endif
35
36/*
37 *  Should the calls to _Thread_Enable_dispatch be inlined?
38 *
39 *  If TRUE, then they are inlined.
40 *  If FALSE, then a subroutine call is made.
41 *
42 *  Basically this is an example of the classic trade-off of size
43 *  versus speed.  Inlining the call (TRUE) typically increases the
44 *  size of RTEMS while speeding up the enabling of dispatching.
45 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
46 *  only be 0 or 1 unless you are in an interrupt handler and that
47 *  interrupt handler invokes the executive.]  When not inlined
48 *  something calls _Thread_Enable_dispatch which in turns calls
49 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
50 *  one subroutine call is avoided entirely.]
51 *
52 *  AVR Specific Information:
53 *
54 *  XXX document implementation including references if appropriate
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 *
76 *  AVR Specific Information:
77 *
78 *  XXX document implementation including references if appropriate
79 */
80
81#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
82
83/*
84 *  Does RTEMS manage a dedicated interrupt stack in software?
85 *
86 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
87 *  If FALSE, nothing is done.
88 *
89 *  If the CPU supports a dedicated interrupt stack in hardware,
90 *  then it is generally the responsibility of the BSP to allocate it
91 *  and set it up.
92 *
93 *  If the CPU does not support a dedicated interrupt stack, then
94 *  the porter has two options: (1) execute interrupts on the
95 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
96 *  interrupt stack.
97 *
98 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
99 *
100 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
101 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
102 *  possible that both are FALSE for a particular CPU.  Although it
103 *  is unclear what that would imply about the interrupt processing
104 *  procedure on that CPU.
105 *
106 *  AVR Specific Information:
107 *
108 *  XXX document implementation including references if appropriate
109 */
110
111#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
112
113/*
114 *  Does this CPU have hardware support for a dedicated interrupt stack?
115 *
116 *  If TRUE, then it must be installed during initialization.
117 *  If FALSE, then no installation is performed.
118 *
119 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
120 *
121 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
122 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
123 *  possible that both are FALSE for a particular CPU.  Although it
124 *  is unclear what that would imply about the interrupt processing
125 *  procedure on that CPU.
126 *
127 *  AVR Specific Information:
128 *
129 *  XXX document implementation including references if appropriate
130 */
131
132#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
133
134/*
135 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
136 *
137 *  If TRUE, then the memory is allocated during initialization.
138 *  If FALSE, then the memory is allocated during initialization.
139 *
140 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
141 *
142 *  AVR Specific Information:
143 *
144 *  XXX document implementation including references if appropriate
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
148
149/*
150 *  Does the RTEMS invoke the user's ISR with the vector number and
151 *  a pointer to the saved interrupt frame (1) or just the vector
152 *  number (0)?
153 *
154 *  AVR Specific Information:
155 *
156 *  XXX document implementation including references if appropriate
157 */
158
159#define CPU_ISR_PASSES_FRAME_POINTER 0
160
161/*
162 *  Does the CPU follow the simple vectored interrupt model?
163 *
164 *  If TRUE, then RTEMS allocates the vector table it internally manages.
165 *  If FALSE, then the BSP is assumed to allocate and manage the vector
166 *  table
167 *
168 *  AVR Specific Information:
169 *
170 *  XXX document implementation including references if appropriate
171 */
172#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
173
174/*
175 *  Does the CPU have hardware floating point?
176 *
177 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
178 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
179 *
180 *  If there is a FP coprocessor such as the i387 or mc68881, then
181 *  the answer is TRUE.
182 *
183 *  The macro name "AVR_HAS_FPU" should be made CPU specific.
184 *  It indicates whether or not this CPU model has FP support.  For
185 *  example, it would be possible to have an i386_nofp CPU model
186 *  which set this to false to indicate that you have an i386 without
187 *  an i387 and wish to leave floating point support out of RTEMS.
188 *
189 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
190 *  is software implemented floating point that must be context
191 *  switched.  The determination of whether or not this applies
192 *  is very tool specific and the state saved/restored is also
193 *  compiler specific.
194 *
195 *  AVR Specific Information:
196 *
197 *  XXX document implementation including references if appropriate
198 */
199
200#if ( AVR_HAS_FPU == 1 )
201#define CPU_HARDWARE_FP     TRUE
202#else
203#define CPU_HARDWARE_FP     FALSE
204#endif
205#define CPU_SOFTWARE_FP     FALSE
206
207/*
208 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
209 *
210 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
211 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
212 *
213 *  So far, the only CPUs in which this option has been used are the
214 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
215 *  gcc both implicitly used the floating point registers to perform
216 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
217 *  seen to allocate floating point local variables and touch the FPU
218 *  even when the flow through a subroutine (like vfprintf()) might
219 *  not use floating point formats.
220 *
221 *  If a function which you would not think utilize the FP unit DOES,
222 *  then one can not easily predict which tasks will use the FP hardware.
223 *  In this case, this option should be TRUE.
224 *
225 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
226 *
227 *  AVR Specific Information:
228 *
229 *  XXX document implementation including references if appropriate
230 */
231
232#define CPU_ALL_TASKS_ARE_FP     TRUE
233
234/*
235 *  Should the IDLE task have a floating point context?
236 *
237 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
238 *  and it has a floating point context which is switched in and out.
239 *  If FALSE, then the IDLE task does not have a floating point context.
240 *
241 *  Setting this to TRUE negatively impacts the time required to preempt
242 *  the IDLE task from an interrupt because the floating point context
243 *  must be saved as part of the preemption.
244 *
245 *  AVR Specific Information:
246 *
247 *  XXX document implementation including references if appropriate
248 */
249
250#define CPU_IDLE_TASK_IS_FP      FALSE
251
252/*
253 *  Should the saving of the floating point registers be deferred
254 *  until a context switch is made to another different floating point
255 *  task?
256 *
257 *  If TRUE, then the floating point context will not be stored until
258 *  necessary.  It will remain in the floating point registers and not
259 *  disturned until another floating point task is switched to.
260 *
261 *  If FALSE, then the floating point context is saved when a floating
262 *  point task is switched out and restored when the next floating point
263 *  task is restored.  The state of the floating point registers between
264 *  those two operations is not specified.
265 *
266 *  If the floating point context does NOT have to be saved as part of
267 *  interrupt dispatching, then it should be safe to set this to TRUE.
268 *
269 *  Setting this flag to TRUE results in using a different algorithm
270 *  for deciding when to save and restore the floating point context.
271 *  The deferred FP switch algorithm minimizes the number of times
272 *  the FP context is saved and restored.  The FP context is not saved
273 *  until a context switch is made to another, different FP task.
274 *  Thus in a system with only one FP task, the FP context will never
275 *  be saved or restored.
276 *
277 *  AVR Specific Information:
278 *
279 *  XXX document implementation including references if appropriate
280 */
281
282#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
283
284/*
285 *  Does this port provide a CPU dependent IDLE task implementation?
286 *
287 *  If TRUE, then the routine _CPU_Thread_Idle_body
288 *  must be provided and is the default IDLE thread body instead of
289 *  _CPU_Thread_Idle_body.
290 *
291 *  If FALSE, then use the generic IDLE thread body if the BSP does
292 *  not provide one.
293 *
294 *  This is intended to allow for supporting processors which have
295 *  a low power or idle mode.  When the IDLE thread is executed, then
296 *  the CPU can be powered down.
297 *
298 *  The order of precedence for selecting the IDLE thread body is:
299 *
300 *    1.  BSP provided
301 *    2.  CPU dependent (if provided)
302 *    3.  generic (if no BSP and no CPU dependent)
303 *
304 *  AVR Specific Information:
305 *
306 *  XXX document implementation including references if appropriate
307 */
308
309#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
310
311/*
312 *  Does the stack grow up (toward higher addresses) or down
313 *  (toward lower addresses)?
314 *
315 *  If TRUE, then the grows upward.
316 *  If FALSE, then the grows toward smaller addresses.
317 *
318 *  AVR Specific Information:
319 *
320 *  XXX document implementation including references if appropriate
321 */
322
323#define CPU_STACK_GROWS_UP               FALSE
324
325/*
326 *  The following is the variable attribute used to force alignment
327 *  of critical RTEMS structures.  On some processors it may make
328 *  sense to have these aligned on tighter boundaries than
329 *  the minimum requirements of the compiler in order to have as
330 *  much of the critical data area as possible in a cache line.
331 *
332 *  The placement of this macro in the declaration of the variables
333 *  is based on the syntactically requirements of the GNU C
334 *  "__attribute__" extension.  For example with GNU C, use
335 *  the following to force a structures to a 32 byte boundary.
336 *
337 *      __attribute__ ((aligned (32)))
338 *
339 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
340 *         To benefit from using this, the data must be heavily
341 *         used so it will stay in the cache and used frequently enough
342 *         in the executive to justify turning this on.
343 *
344 *  AVR Specific Information:
345 *
346 *  XXX document implementation including references if appropriate
347 */
348
349#define CPU_STRUCTURE_ALIGNMENT
350
351#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
352
353/*
354 *  Define what is required to specify how the network to host conversion
355 *  routines are handled.
356 *
357 *  AVR Specific Information:
358 *
359 *  XXX document implementation including references if appropriate
360 */
361
362#define CPU_BIG_ENDIAN                           TRUE
363#define CPU_LITTLE_ENDIAN                        FALSE
364
365/*
366 *  The following defines the number of bits actually used in the
367 *  interrupt field of the task mode.  How those bits map to the
368 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
369 *
370 *  AVR Specific Information:
371 *
372 *  XXX document implementation including references if appropriate
373 */
374
375#define CPU_MODES_INTERRUPT_MASK   0x00000001
376
377#define CPU_PER_CPU_CONTROL_SIZE 0
378
379/*
380 *  Processor defined structures required for cpukit/score.
381 *
382 *  AVR Specific Information:
383 *
384 *  XXX document implementation including references if appropriate
385 */
386
387/* may need to put some structures here.  */
388
389#ifndef ASM
390
391typedef struct {
392  /* There is no CPU specific per-CPU state */
393} CPU_Per_CPU_control;
394
395/*
396 * Contexts
397 *
398 *  Generally there are 2 types of context to save.
399 *     1. Interrupt registers to save
400 *     2. Task level registers to save
401 *
402 *  This means we have the following 3 context items:
403 *     1. task level context stuff::  Context_Control
404 *     2. floating point task stuff:: Context_Control_fp
405 *     3. special interrupt level context :: Context_Control_interrupt
406 *
407 *  On some processors, it is cost-effective to save only the callee
408 *  preserved registers during a task context switch.  This means
409 *  that the ISR code needs to save those registers which do not
410 *  persist across function calls.  It is not mandatory to make this
411 *  distinctions between the caller/callee saves registers for the
412 *  purpose of minimizing context saved during task switch and on interrupts.
413 *  If the cost of saving extra registers is minimal, simplicity is the
414 *  choice.  Save the same context on interrupt entry as for tasks in
415 *  this case.
416 *
417 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
418 *  care should be used in designing the context area.
419 *
420 *  On some CPUs with hardware floating point support, the Context_Control_fp
421 *  structure will not be used or it simply consist of an array of a
422 *  fixed number of bytes.   This is done when the floating point context
423 *  is dumped by a "FP save context" type instruction and the format
424 *  is not really defined by the CPU.  In this case, there is no need
425 *  to figure out the exact format -- only the size.  Of course, although
426 *  this is enough information for RTEMS, it is probably not enough for
427 *  a debugger such as gdb.  But that is another problem.
428 *
429 *  AVR Specific Information:
430 *
431 *  XXX document implementation including references if appropriate
432 */
433
434typedef struct {
435        uint16_t        stack_pointer;
436        uint8_t         status; /* SREG */
437} Context_Control;
438
439#define _CPU_Context_Get_SP( _context ) \
440  (_context)->stack_pointer
441
442
443
444
445typedef struct {
446    double      some_float_register;
447} Context_Control_fp;
448
449typedef struct {
450    uint32_t   special_interrupt_register;
451} CPU_Interrupt_frame;
452
453/*
454 *  This variable is optional.  It is used on CPUs on which it is difficult
455 *  to generate an "uninitialized" FP context.  It is filled in by
456 *  _CPU_Initialize and copied into the task's FP context area during
457 *  _CPU_Context_Initialize.
458 *
459 *  AVR Specific Information:
460 *
461 *  XXX document implementation including references if appropriate
462 */
463
464SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
465
466#endif /* ASM */
467
468/*
469 *  Nothing prevents the porter from declaring more CPU specific variables.
470 *
471 *  AVR Specific Information:
472 *
473 *  XXX document implementation including references if appropriate
474 */
475
476/* XXX: if needed, put more variables here */
477
478/*
479 *  The size of the floating point context area.  On some CPUs this
480 *  will not be a "sizeof" because the format of the floating point
481 *  area is not defined -- only the size is.  This is usually on
482 *  CPUs with a "floating point save context" instruction.
483 *
484 *  AVR Specific Information:
485 *
486 *  XXX document implementation including references if appropriate
487 */
488
489#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
490
491/*
492 *  Amount of extra stack (above minimum stack size) required by
493 *  MPCI receive server thread.  Remember that in a multiprocessor
494 *  system this thread must exist and be able to process all directives.
495 *
496 *  AVR Specific Information:
497 *
498 *  XXX document implementation including references if appropriate
499 */
500
501#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
502
503/*
504 *  This defines the number of entries in the ISR_Vector_table managed
505 *  by RTEMS.
506 *
507 *  AVR Specific Information:
508 *
509 *  XXX document implementation including references if appropriate
510 */
511
512#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
513#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
514
515/*
516 *  This is defined if the port has a special way to report the ISR nesting
517 *  level.  Most ports maintain the variable _ISR_Nest_level.
518 */
519
520#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
521
522/*
523 *  Should be large enough to run all RTEMS tests.  This ensures
524 *  that a "reasonable" small application should not have any problems.
525 *
526 *  AVR Specific Information:
527 *
528 *  XXX document implementation including references if appropriate
529 */
530
531#define CPU_STACK_MINIMUM_SIZE          512
532
533/*
534 *  Maximum priority of a thread. Note based from 0 which is the idle task.
535 */
536#define CPU_PRIORITY_MAXIMUM             15
537
538#define CPU_SIZEOF_POINTER 2
539
540/*
541 *  CPU's worst alignment requirement for data types on a byte boundary.  This
542 *  alignment does not take into account the requirements for the stack.
543 *
544 *  AVR Specific Information:
545 *
546 *  XXX document implementation including references if appropriate
547 */
548
549#define CPU_ALIGNMENT              4
550
551/*
552 *  This number corresponds to the byte alignment requirement for the
553 *  heap handler.  This alignment requirement may be stricter than that
554 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
555 *  common for the heap to follow the same alignment requirement as
556 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
557 *  then this should be set to CPU_ALIGNMENT.
558 *
559 *  NOTE:  This does not have to be a power of 2 although it should be
560 *         a multiple of 2 greater than or equal to 2.  The requirement
561 *         to be a multiple of 2 is because the heap uses the least
562 *         significant field of the front and back flags to indicate
563 *         that a block is in use or free.  So you do not want any odd
564 *         length blocks really putting length data in that bit.
565 *
566 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
567 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
568 *         elements allocated from the heap meet all restrictions.
569 *
570 *  AVR Specific Information:
571 *
572 *  XXX document implementation including references if appropriate
573 */
574
575#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
576
577/*
578 *  This number corresponds to the byte alignment requirement for memory
579 *  buffers allocated by the partition manager.  This alignment requirement
580 *  may be stricter than that for the data types alignment specified by
581 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
582 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
583 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
584 *
585 *  NOTE:  This does not have to be a power of 2.  It does have to
586 *         be greater or equal to than CPU_ALIGNMENT.
587 *
588 *  AVR Specific Information:
589 *
590 *  XXX document implementation including references if appropriate
591 */
592
593#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
594
595/*
596 *  This number corresponds to the byte alignment requirement for the
597 *  stack.  This alignment requirement may be stricter than that for the
598 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
599 *  is strict enough for the stack, then this should be set to 0.
600 *
601 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
602 *
603 *  AVR Specific Information:
604 *
605 *  XXX document implementation including references if appropriate
606 */
607
608#define CPU_STACK_ALIGNMENT        0
609
610/*
611 *  ISR handler macros
612 */
613
614/*
615 *  Support routine to initialize the RTEMS vector table after it is allocated.
616 *
617 *  AVR Specific Information:
618 *
619 *  XXX document implementation including references if appropriate
620 */
621
622#define _CPU_Initialize_vectors()
623
624/*
625 *  Disable all interrupts for an RTEMS critical section.  The previous
626 *  level is returned in _level.
627 *
628 *  AVR Specific Information:
629 *
630 *  XXX document implementation including references if appropriate
631 */
632
633#define _CPU_ISR_Disable( _isr_cookie ) \
634  do { \
635        (_isr_cookie) = SREG; \
636        __asm__ volatile ("cli"::); \
637  } while (0)
638
639/*
640 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
641 *  This indicates the end of an RTEMS critical section.  The parameter
642 *  _level is not modified.
643 *
644 *  AVR Specific Information:
645 *
646 *  XXX document implementation including references if appropriate
647 */
648
649#define _CPU_ISR_Enable( _isr_cookie )  \
650  do { \
651        SREG  = _isr_cookie; \
652        __asm__ volatile ("sei"::); \
653  } while (0)
654
655/*
656 *  This temporarily restores the interrupt to _level before immediately
657 *  disabling them again.  This is used to divide long RTEMS critical
658 *  sections into two or more parts.  The parameter _level is not
659 * modified.
660 *
661 *  AVR Specific Information:
662 *
663 *  XXX document implementation including references if appropriate
664 */
665
666#define _CPU_ISR_Flash( _isr_cookie ) \
667  do { \
668        SREG=(_isr_cookie); \
669        __asm__ volatile("sei"::); \
670        (_isr_cookie) = SREG; \
671        __asm__ volatile("cli"::); \
672  } while (0)
673
674/*
675 *  Map interrupt level in task mode onto the hardware that the CPU
676 *  actually provides.  Currently, interrupt levels which do not
677 *  map onto the CPU in a generic fashion are undefined.  Someday,
678 *  it would be nice if these were "mapped" by the application
679 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
680 *  8 - 255 would be available for bsp/application specific meaning.
681 *  This could be used to manage a programmable interrupt controller
682 *  via the rtems_task_mode directive.
683 *
684 *  The get routine usually must be implemented as a subroutine.
685 *
686 *  AVR Specific Information:
687 *
688 *  XXX document implementation including references if appropriate
689 */
690
691#define _CPU_ISR_Set_level( new_level ) \
692  { \
693  }
694
695#ifndef ASM
696
697uint32_t   _CPU_ISR_Get_level( void );
698
699/* end of ISR handler macros */
700
701/* Context handler macros */
702
703/*
704 *  Initialize the context to a state suitable for starting a
705 *  task after a context restore operation.  Generally, this
706 *  involves:
707 *
708 *     - setting a starting address
709 *     - preparing the stack
710 *     - preparing the stack and frame pointers
711 *     - setting the proper interrupt level in the context
712 *     - initializing the floating point context
713 *
714 *  This routine generally does not set any unnecessary register
715 *  in the context.  The state of the "general data" registers is
716 *  undefined at task start time.
717 *
718 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
719 *        point thread.  This is typically only used on CPUs where the
720 *        FPU may be easily disabled by software such as on the SPARC
721 *        where the PSR contains an enable FPU bit.
722 *
723 *  AVR Specific Information:
724 *
725 *  XXX document implementation including references if appropriate
726 */
727/*
728#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
729                                 _isr, _entry_point, _is_fp ) \
730  \
731        do { \
732        uint16_t *_stack;\
733        _stack  = (uint16_t) (_stack_base) + (uint16_t)(_size);\
734        (_the_context)->stack_pointer = _stack-1;       \
735        *(_stack) = *(_entry_point);    \
736        printk("the ret address is %x\n", *(uint16_t *)(_stack));\
737        printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \
738        printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\
739        printk("struct starting address = 0x%x\n", _the_context);\
740        printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\
741        } while ( 0 )
742
743*/
744/*
745 *  This routine is responsible for somehow restarting the currently
746 *  executing task.  If you are lucky, then all that is necessary
747 *  is restoring the context.  Otherwise, there will need to be
748 *  a special assembly routine which does something special in this
749 *  case.  Context_Restore should work most of the time.  It will
750 *  not work if restarting self conflicts with the stack frame
751 *  assumptions of restoring a context.
752 *
753 *  AVR Specific Information:
754 *
755 *  XXX document implementation including references if appropriate
756 */
757
758#define _CPU_Context_Restart_self( _the_context ) \
759   _CPU_Context_restore( _the_context );
760
761/*
762 *  The purpose of this macro is to allow the initial pointer into
763 *  a floating point context area (used to save the floating point
764 *  context) to be at an arbitrary place in the floating point
765 *  context area.
766 *
767 *  This is necessary because some FP units are designed to have
768 *  their context saved as a stack which grows into lower addresses.
769 *  Other FP units can be saved by simply moving registers into offsets
770 *  from the base of the context area.  Finally some FP units provide
771 *  a "dump context" instruction which could fill in from high to low
772 *  or low to high based on the whim of the CPU designers.
773 *
774 *  AVR Specific Information:
775 *
776 *  XXX document implementation including references if appropriate
777 */
778
779#define _CPU_Context_Fp_start( _base, _offset ) \
780   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
781
782/*
783 *  This routine initializes the FP context area passed to it to.
784 *  There are a few standard ways in which to initialize the
785 *  floating point context.  The code included for this macro assumes
786 *  that this is a CPU in which a "initial" FP context was saved into
787 *  _CPU_Null_fp_context and it simply copies it to the destination
788 *  context passed to it.
789 *
790 *  Other models include (1) not doing anything, and (2) putting
791 *  a "null FP status word" in the correct place in the FP context.
792 *
793 *  AVR Specific Information:
794 *
795 *  XXX document implementation including references if appropriate
796 */
797
798#define _CPU_Context_Initialize_fp( _destination ) \
799  { \
800   *(*(_destination)) = _CPU_Null_fp_context; \
801  }
802
803/* end of Context handler macros */
804
805/* Fatal Error manager macros */
806
807/*
808 *  This routine copies _error into a known place -- typically a stack
809 *  location or a register, optionally disables interrupts, and
810 *  halts/stops the CPU.
811 *
812 *  AVR Specific Information:
813 *
814 *  XXX document implementation including references if appropriate
815 */
816
817#define _CPU_Fatal_halt( _source, _error ) \
818  { \
819  }
820
821/* end of Fatal Error manager macros */
822
823/* Bitfield handler macros */
824
825/*
826 *  This routine sets _output to the bit number of the first bit
827 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
828 *  This type may be either 16 or 32 bits wide although only the 16
829 *  least significant bits will be used.
830 *
831 *  There are a number of variables in using a "find first bit" type
832 *  instruction.
833 *
834 *    (1) What happens when run on a value of zero?
835 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
836 *    (3) The numbering may be zero or one based.
837 *    (4) The "find first bit" instruction may search from MSB or LSB.
838 *
839 *  RTEMS guarantees that (1) will never happen so it is not a concern.
840 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
841 *  _CPU_Priority_bits_index().  These three form a set of routines
842 *  which must logically operate together.  Bits in the _value are
843 *  set and cleared based on masks built by _CPU_Priority_mask().
844 *  The basic major and minor values calculated by _Priority_Major()
845 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
846 *  to properly range between the values returned by the "find first bit"
847 *  instruction.  This makes it possible for _Priority_Get_highest() to
848 *  calculate the major and directly index into the minor table.
849 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
850 *  is the first bit found.
851 *
852 *  This entire "find first bit" and mapping process depends heavily
853 *  on the manner in which a priority is broken into a major and minor
854 *  components with the major being the 4 MSB of a priority and minor
855 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
856 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
857 *  to the lowest priority.
858 *
859 *  If your CPU does not have a "find first bit" instruction, then
860 *  there are ways to make do without it.  Here are a handful of ways
861 *  to implement this in software:
862 *
863 *    - a series of 16 bit test instructions
864 *    - a "binary search using if's"
865 *    - _number = 0
866 *      if _value > 0x00ff
867 *        _value >>=8
868 *        _number = 8;
869 *
870 *      if _value > 0x0000f
871 *        _value >=8
872 *        _number += 4
873 *
874 *      _number += bit_set_table[ _value ]
875 *
876 *    where bit_set_table[ 16 ] has values which indicate the first
877 *      bit set
878 *
879 *  AVR Specific Information:
880 *
881 *  XXX document implementation including references if appropriate
882 */
883
884#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
885#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
886
887#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
888
889#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
890  { \
891    (_output) = 0;   /* do something to prevent warnings */ \
892  }
893
894#endif
895
896/* end of Bitfield handler macros */
897
898/*
899 *  This routine builds the mask which corresponds to the bit fields
900 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
901 *  for that routine.
902 *
903 *  AVR Specific Information:
904 *
905 *  XXX document implementation including references if appropriate
906 */
907
908#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
909
910#define _CPU_Priority_Mask( _bit_number ) \
911  ( 1 << (_bit_number) )
912
913#endif
914
915/*
916 *  This routine translates the bit numbers returned by
917 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
918 *  a major or minor component of a priority.  See the discussion
919 *  for that routine.
920 *
921 *  AVR Specific Information:
922 *
923 *  XXX document implementation including references if appropriate
924 */
925
926#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
927
928#define _CPU_Priority_bits_index( _priority ) \
929  (_priority)
930
931#endif
932
933/* end of Priority handler macros */
934
935/* functions */
936
937/*context_initialize asm-function*/
938
939void context_initialize(unsigned short* context,
940                unsigned short stack_add,
941                unsigned short entry_point);
942
943/*
944 *  _CPU_Context_Initialize
945 *
946 *  This kernel routine initializes the basic non-FP context area associated
947 *  with each thread.
948 *
949 *  Input parameters:
950 *    the_context  - pointer to the context area
951 *    stack_base   - address of memory for the SPARC
952 *    size         - size in bytes of the stack area
953 *    new_level    - interrupt level for this context area
954 *    entry_point  - the starting execution point for this this context
955 *    is_fp        - TRUE if this context is associated with an FP thread
956 *
957 *  Output parameters: NONE
958 */
959
960void _CPU_Context_Initialize(
961  Context_Control  *the_context,
962  uint32_t         *stack_base,
963  uint32_t          size,
964  uint32_t          new_level,
965  void             *entry_point,
966  bool              is_fp,
967  void             *tls_area
968);
969
970/*
971*
972*  _CPU_Push
973*
974*  this routine pushes 2 bytes onto the stack
975*
976*
977*
978*
979*
980*
981*
982*/
983
984void _CPU_Push(uint16_t _SP_, uint16_t entry_point);
985
986
987
988
989/*
990 *  _CPU_Initialize
991 *
992 *  This routine performs CPU dependent initialization.
993 *
994 *  AVR Specific Information:
995 *
996 *  XXX document implementation including references if appropriate
997 */
998
999void _CPU_Initialize(void);
1000
1001/*
1002 *  _CPU_ISR_install_raw_handler
1003 *
1004 *  This routine installs a "raw" interrupt handler directly into the
1005 *  processor's vector table.
1006 *
1007 *  AVR Specific Information:
1008 *
1009 *  XXX document implementation including references if appropriate
1010 */
1011
1012void _CPU_ISR_install_raw_handler(
1013  uint32_t    vector,
1014  proc_ptr    new_handler,
1015  proc_ptr   *old_handler
1016);
1017
1018/*
1019 *  _CPU_ISR_install_vector
1020 *
1021 *  This routine installs an interrupt vector.
1022 *
1023 *  AVR Specific Information:
1024 *
1025 *  XXX document implementation including references if appropriate
1026 */
1027
1028void _CPU_ISR_install_vector(
1029  uint32_t    vector,
1030  proc_ptr    new_handler,
1031  proc_ptr   *old_handler
1032);
1033
1034/*
1035 *  _CPU_Install_interrupt_stack
1036 *
1037 *  This routine installs the hardware interrupt stack pointer.
1038 *
1039 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1040 *         is TRUE.
1041 *
1042 *  AVR Specific Information:
1043 *
1044 *  XXX document implementation including references if appropriate
1045 */
1046
1047void _CPU_Install_interrupt_stack( void );
1048
1049/*
1050 *  _CPU_Thread_Idle_body
1051 *
1052 *  This routine is the CPU dependent IDLE thread body.
1053 *
1054 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1055 *         is TRUE.
1056 *
1057 *  AVR Specific Information:
1058 *
1059 *  XXX document implementation including references if appropriate
1060 */
1061
1062void *_CPU_Thread_Idle_body( uintptr_t ignored );
1063
1064/*
1065 *  _CPU_Context_switch
1066 *
1067 *  This routine switches from the run context to the heir context.
1068 *
1069 *  AVR Specific Information:
1070 *
1071 *  XXX document implementation including references if appropriate
1072 */
1073
1074void _CPU_Context_switch(
1075  Context_Control  *run,
1076  Context_Control  *heir
1077);
1078
1079/*
1080 *  _CPU_Context_restore
1081 *
1082 *  This routine is generally used only to restart self in an
1083 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1084 *
1085 *  NOTE: May be unnecessary to reload some registers.
1086 *
1087 *  AVR Specific Information:
1088 *
1089 *  XXX document implementation including references if appropriate
1090 */
1091
1092void _CPU_Context_restore(
1093  Context_Control *new_context
1094) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1095
1096/*
1097 *  _CPU_Context_save_fp
1098 *
1099 *  This routine saves the floating point context passed to it.
1100 *
1101 *  AVR Specific Information:
1102 *
1103 *  XXX document implementation including references if appropriate
1104 */
1105
1106void _CPU_Context_save_fp(
1107  Context_Control_fp **fp_context_ptr
1108);
1109
1110/*
1111 *  _CPU_Context_restore_fp
1112 *
1113 *  This routine restores the floating point context passed to it.
1114 *
1115 *  AVR Specific Information:
1116 *
1117 *  XXX document implementation including references if appropriate
1118 */
1119
1120void _CPU_Context_restore_fp(
1121  Context_Control_fp **fp_context_ptr
1122);
1123
1124static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
1125{
1126  /* TODO */
1127}
1128
1129static inline void _CPU_Context_validate( uintptr_t pattern )
1130{
1131  while (1) {
1132    /* TODO */
1133  }
1134}
1135
1136/* FIXME */
1137typedef CPU_Interrupt_frame CPU_Exception_frame;
1138
1139void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1140
1141/*  The following routine swaps the endian format of an unsigned int.
1142 *  It must be static because it is referenced indirectly.
1143 *
1144 *  This version will work on any processor, but if there is a better
1145 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1146 *
1147 *     swap least significant two bytes with 16-bit rotate
1148 *     swap upper and lower 16-bits
1149 *     swap most significant two bytes with 16-bit rotate
1150 *
1151 *  Some CPUs have special instructions which swap a 32-bit quantity in
1152 *  a single instruction (e.g. i486).  It is probably best to avoid
1153 *  an "endian swapping control bit" in the CPU.  One good reason is
1154 *  that interrupts would probably have to be disabled to ensure that
1155 *  an interrupt does not try to access the same "chunk" with the wrong
1156 *  endian.  Another good reason is that on some CPUs, the endian bit
1157 *  endianness for ALL fetches -- both code and data -- so the code
1158 *  will be fetched incorrectly.
1159 *
1160 *  AVR Specific Information:
1161 *
1162 *  XXX document implementation including references if appropriate
1163 */
1164
1165static inline uint32_t CPU_swap_u32(
1166  uint32_t value
1167)
1168{
1169  uint32_t   byte1, byte2, byte3, byte4, swapped;
1170
1171  byte4 = (value >> 24) & 0xff;
1172  byte3 = (value >> 16) & 0xff;
1173  byte2 = (value >> 8)  & 0xff;
1174  byte1 =  value        & 0xff;
1175
1176  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1177  return( swapped );
1178}
1179
1180#define CPU_swap_u16( value ) \
1181  (((value&0xff) << 8) | ((value >> 8)&0xff))
1182
1183typedef uint32_t CPU_Counter_ticks;
1184
1185CPU_Counter_ticks _CPU_Counter_read( void );
1186
1187static inline CPU_Counter_ticks _CPU_Counter_difference(
1188  CPU_Counter_ticks second,
1189  CPU_Counter_ticks first
1190)
1191{
1192  return second - first;
1193}
1194
1195#endif /* ASM */
1196
1197#ifdef __cplusplus
1198}
1199#endif
1200
1201#endif
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