source: rtems/cpukit/score/cpu/avr/rtems/score/cpu.h @ c03e2bc

4.104.115
Last change on this file since c03e2bc was c03e2bc, checked in by Joel Sherrill <joel.sherrill@…>, on 02/11/09 at 21:45:05

2009-02-11 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
  • Property mode set to 100644
File size: 33.7 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the AVR
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/avr.h>            /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33/*
34 *  Should the calls to _Thread_Enable_dispatch be inlined?
35 *
36 *  If TRUE, then they are inlined.
37 *  If FALSE, then a subroutine call is made.
38 *
39 *  Basically this is an example of the classic trade-off of size
40 *  versus speed.  Inlining the call (TRUE) typically increases the
41 *  size of RTEMS while speeding up the enabling of dispatching.
42 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
43 *  only be 0 or 1 unless you are in an interrupt handler and that
44 *  interrupt handler invokes the executive.]  When not inlined
45 *  something calls _Thread_Enable_dispatch which in turns calls
46 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
47 *  one subroutine call is avoided entirely.]
48 *
49 *  AVR Specific Information:
50 *
51 *  XXX document implementation including references if appropriate
52 */
53
54#define CPU_INLINE_ENABLE_DISPATCH       FALSE
55
56/*
57 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
58 *  be unrolled one time?  In unrolled each iteration of the loop examines
59 *  two "nodes" on the chain being searched.  Otherwise, only one node
60 *  is examined per iteration.
61 *
62 *  If TRUE, then the loops are unrolled.
63 *  If FALSE, then the loops are not unrolled.
64 *
65 *  The primary factor in making this decision is the cost of disabling
66 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
67 *  body of the loop.  On some CPUs, the flash is more expensive than
68 *  one iteration of the loop body.  In this case, it might be desirable
69 *  to unroll the loop.  It is important to note that on some CPUs, this
70 *  code is the longest interrupt disable period in RTEMS.  So it is
71 *  necessary to strike a balance when setting this parameter.
72 *
73 *  AVR Specific Information:
74 *
75 *  XXX document implementation including references if appropriate
76 */
77
78#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
79
80/*
81 *  Does RTEMS manage a dedicated interrupt stack in software?
82 *
83 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
84 *  If FALSE, nothing is done.
85 *
86 *  If the CPU supports a dedicated interrupt stack in hardware,
87 *  then it is generally the responsibility of the BSP to allocate it
88 *  and set it up.
89 *
90 *  If the CPU does not support a dedicated interrupt stack, then
91 *  the porter has two options: (1) execute interrupts on the
92 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
93 *  interrupt stack.
94 *
95 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
96 *
97 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
98 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
99 *  possible that both are FALSE for a particular CPU.  Although it
100 *  is unclear what that would imply about the interrupt processing
101 *  procedure on that CPU.
102 *
103 *  AVR Specific Information:
104 *
105 *  XXX document implementation including references if appropriate
106 */
107
108#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
109
110/*
111 *  Does this CPU have hardware support for a dedicated interrupt stack?
112 *
113 *  If TRUE, then it must be installed during initialization.
114 *  If FALSE, then no installation is performed.
115 *
116 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
117 *
118 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
119 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
120 *  possible that both are FALSE for a particular CPU.  Although it
121 *  is unclear what that would imply about the interrupt processing
122 *  procedure on that CPU.
123 *
124 *  AVR Specific Information:
125 *
126 *  XXX document implementation including references if appropriate
127 */
128
129#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
130
131/*
132 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
133 *
134 *  If TRUE, then the memory is allocated during initialization.
135 *  If FALSE, then the memory is allocated during initialization.
136 *
137 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
138 *
139 *  AVR Specific Information:
140 *
141 *  XXX document implementation including references if appropriate
142 */
143
144#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
145
146/*
147 *  Does the RTEMS invoke the user's ISR with the vector number and
148 *  a pointer to the saved interrupt frame (1) or just the vector
149 *  number (0)?
150 *
151 *  AVR Specific Information:
152 *
153 *  XXX document implementation including references if appropriate
154 */
155
156#define CPU_ISR_PASSES_FRAME_POINTER 0
157
158/*
159 *  Does the CPU follow the simple vectored interrupt model?
160 *
161 *  If TRUE, then RTEMS allocates the vector table it internally manages.
162 *  If FALSE, then the BSP is assumed to allocate and manage the vector
163 *  table
164 *
165 *  AVR Specific Information:
166 *
167 *  XXX document implementation including references if appropriate
168 */
169#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
170
171/*
172 *  Does the CPU have hardware floating point?
173 *
174 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
175 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
176 *
177 *  If there is a FP coprocessor such as the i387 or mc68881, then
178 *  the answer is TRUE.
179 *
180 *  The macro name "AVR_HAS_FPU" should be made CPU specific.
181 *  It indicates whether or not this CPU model has FP support.  For
182 *  example, it would be possible to have an i386_nofp CPU model
183 *  which set this to false to indicate that you have an i386 without
184 *  an i387 and wish to leave floating point support out of RTEMS.
185 *
186 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
187 *  is software implemented floating point that must be context
188 *  switched.  The determination of whether or not this applies
189 *  is very tool specific and the state saved/restored is also
190 *  compiler specific.
191 *
192 *  AVR Specific Information:
193 *
194 *  XXX document implementation including references if appropriate
195 */
196
197#if ( AVR_HAS_FPU == 1 )
198#define CPU_HARDWARE_FP     TRUE
199#else
200#define CPU_HARDWARE_FP     FALSE
201#endif
202#define CPU_SOFTWARE_FP     FALSE
203
204/*
205 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
206 *
207 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
208 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
209 *
210 *  So far, the only CPUs in which this option has been used are the
211 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
212 *  gcc both implicitly used the floating point registers to perform
213 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
214 *  seen to allocate floating point local variables and touch the FPU
215 *  even when the flow through a subroutine (like vfprintf()) might
216 *  not use floating point formats.
217 *
218 *  If a function which you would not think utilize the FP unit DOES,
219 *  then one can not easily predict which tasks will use the FP hardware.
220 *  In this case, this option should be TRUE.
221 *
222 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
223 *
224 *  AVR Specific Information:
225 *
226 *  XXX document implementation including references if appropriate
227 */
228
229#define CPU_ALL_TASKS_ARE_FP     TRUE
230
231/*
232 *  Should the IDLE task have a floating point context?
233 *
234 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
235 *  and it has a floating point context which is switched in and out.
236 *  If FALSE, then the IDLE task does not have a floating point context.
237 *
238 *  Setting this to TRUE negatively impacts the time required to preempt
239 *  the IDLE task from an interrupt because the floating point context
240 *  must be saved as part of the preemption.
241 *
242 *  AVR Specific Information:
243 *
244 *  XXX document implementation including references if appropriate
245 */
246
247#define CPU_IDLE_TASK_IS_FP      FALSE
248
249/*
250 *  Should the saving of the floating point registers be deferred
251 *  until a context switch is made to another different floating point
252 *  task?
253 *
254 *  If TRUE, then the floating point context will not be stored until
255 *  necessary.  It will remain in the floating point registers and not
256 *  disturned until another floating point task is switched to.
257 *
258 *  If FALSE, then the floating point context is saved when a floating
259 *  point task is switched out and restored when the next floating point
260 *  task is restored.  The state of the floating point registers between
261 *  those two operations is not specified.
262 *
263 *  If the floating point context does NOT have to be saved as part of
264 *  interrupt dispatching, then it should be safe to set this to TRUE.
265 *
266 *  Setting this flag to TRUE results in using a different algorithm
267 *  for deciding when to save and restore the floating point context.
268 *  The deferred FP switch algorithm minimizes the number of times
269 *  the FP context is saved and restored.  The FP context is not saved
270 *  until a context switch is made to another, different FP task.
271 *  Thus in a system with only one FP task, the FP context will never
272 *  be saved or restored.
273 *
274 *  AVR Specific Information:
275 *
276 *  XXX document implementation including references if appropriate
277 */
278
279#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
280
281/*
282 *  Does this port provide a CPU dependent IDLE task implementation?
283 *
284 *  If TRUE, then the routine _CPU_Thread_Idle_body
285 *  must be provided and is the default IDLE thread body instead of
286 *  _CPU_Thread_Idle_body.
287 *
288 *  If FALSE, then use the generic IDLE thread body if the BSP does
289 *  not provide one.
290 *
291 *  This is intended to allow for supporting processors which have
292 *  a low power or idle mode.  When the IDLE thread is executed, then
293 *  the CPU can be powered down.
294 *
295 *  The order of precedence for selecting the IDLE thread body is:
296 *
297 *    1.  BSP provided
298 *    2.  CPU dependent (if provided)
299 *    3.  generic (if no BSP and no CPU dependent)
300 *
301 *  AVR Specific Information:
302 *
303 *  XXX document implementation including references if appropriate
304 */
305
306#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
307
308/*
309 *  Does the stack grow up (toward higher addresses) or down
310 *  (toward lower addresses)?
311 *
312 *  If TRUE, then the grows upward.
313 *  If FALSE, then the grows toward smaller addresses.
314 *
315 *  AVR Specific Information:
316 *
317 *  XXX document implementation including references if appropriate
318 */
319
320#define CPU_STACK_GROWS_UP               TRUE
321
322/*
323 *  The following is the variable attribute used to force alignment
324 *  of critical RTEMS structures.  On some processors it may make
325 *  sense to have these aligned on tighter boundaries than
326 *  the minimum requirements of the compiler in order to have as
327 *  much of the critical data area as possible in a cache line.
328 *
329 *  The placement of this macro in the declaration of the variables
330 *  is based on the syntactically requirements of the GNU C
331 *  "__attribute__" extension.  For example with GNU C, use
332 *  the following to force a structures to a 32 byte boundary.
333 *
334 *      __attribute__ ((aligned (32)))
335 *
336 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
337 *         To benefit from using this, the data must be heavily
338 *         used so it will stay in the cache and used frequently enough
339 *         in the executive to justify turning this on.
340 *
341 *  AVR Specific Information:
342 *
343 *  XXX document implementation including references if appropriate
344 */
345
346#define CPU_STRUCTURE_ALIGNMENT
347
348/*
349 *  Define what is required to specify how the network to host conversion
350 *  routines are handled.
351 *
352 *  AVR Specific Information:
353 *
354 *  XXX document implementation including references if appropriate
355 */
356
357#define CPU_BIG_ENDIAN                           TRUE
358#define CPU_LITTLE_ENDIAN                        FALSE
359
360/*
361 *  The following defines the number of bits actually used in the
362 *  interrupt field of the task mode.  How those bits map to the
363 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
364 *
365 *  AVR Specific Information:
366 *
367 *  XXX document implementation including references if appropriate
368 */
369
370#define CPU_MODES_INTERRUPT_MASK   0x00000001
371
372/*
373 *  Processor defined structures required for cpukit/score.
374 *
375 *  AVR Specific Information:
376 *
377 *  XXX document implementation including references if appropriate
378 */
379
380/* may need to put some structures here.  */
381
382/*
383 * Contexts
384 *
385 *  Generally there are 2 types of context to save.
386 *     1. Interrupt registers to save
387 *     2. Task level registers to save
388 *
389 *  This means we have the following 3 context items:
390 *     1. task level context stuff::  Context_Control
391 *     2. floating point task stuff:: Context_Control_fp
392 *     3. special interrupt level context :: Context_Control_interrupt
393 *
394 *  On some processors, it is cost-effective to save only the callee
395 *  preserved registers during a task context switch.  This means
396 *  that the ISR code needs to save those registers which do not
397 *  persist across function calls.  It is not mandatory to make this
398 *  distinctions between the caller/callee saves registers for the
399 *  purpose of minimizing context saved during task switch and on interrupts.
400 *  If the cost of saving extra registers is minimal, simplicity is the
401 *  choice.  Save the same context on interrupt entry as for tasks in
402 *  this case.
403 *
404 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
405 *  care should be used in designing the context area.
406 *
407 *  On some CPUs with hardware floating point support, the Context_Control_fp
408 *  structure will not be used or it simply consist of an array of a
409 *  fixed number of bytes.   This is done when the floating point context
410 *  is dumped by a "FP save context" type instruction and the format
411 *  is not really defined by the CPU.  In this case, there is no need
412 *  to figure out the exact format -- only the size.  Of course, although
413 *  this is enough information for RTEMS, it is probably not enough for
414 *  a debugger such as gdb.  But that is another problem.
415 *
416 *  AVR Specific Information:
417 *
418 *  XXX document implementation including references if appropriate
419 */
420
421typedef struct {
422    uint32_t   some_integer_register;
423    uint32_t   some_system_register;
424    uint32_t   stack_pointer;
425} Context_Control;
426
427#define _CPU_Context_Get_SP( _context ) \
428  (_context)->stack_pointer
429
430typedef struct {
431    double      some_float_register;
432} Context_Control_fp;
433
434typedef struct {
435    uint32_t   special_interrupt_register;
436} CPU_Interrupt_frame;
437
438/*
439 *  This variable is optional.  It is used on CPUs on which it is difficult
440 *  to generate an "uninitialized" FP context.  It is filled in by
441 *  _CPU_Initialize and copied into the task's FP context area during
442 *  _CPU_Context_Initialize.
443 *
444 *  AVR Specific Information:
445 *
446 *  XXX document implementation including references if appropriate
447 */
448
449SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
450
451/*
452 *  On some CPUs, RTEMS supports a software managed interrupt stack.
453 *  This stack is allocated by the Interrupt Manager and the switch
454 *  is performed in _ISR_Handler.  These variables contain pointers
455 *  to the lowest and highest addresses in the chunk of memory allocated
456 *  for the interrupt stack.  Since it is unknown whether the stack
457 *  grows up or down (in general), this give the CPU dependent
458 *  code the option of picking the version it wants to use.
459 *
460 *  NOTE: These two variables are required if the macro
461 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
462 *
463 *  AVR Specific Information:
464 *
465 *  XXX document implementation including references if appropriate
466 */
467
468SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
469SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
470
471/*
472 *  Nothing prevents the porter from declaring more CPU specific variables.
473 *
474 *  AVR Specific Information:
475 *
476 *  XXX document implementation including references if appropriate
477 */
478
479/* XXX: if needed, put more variables here */
480
481/*
482 *  The size of the floating point context area.  On some CPUs this
483 *  will not be a "sizeof" because the format of the floating point
484 *  area is not defined -- only the size is.  This is usually on
485 *  CPUs with a "floating point save context" instruction.
486 *
487 *  AVR Specific Information:
488 *
489 *  XXX document implementation including references if appropriate
490 */
491
492#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
493
494/*
495 *  Amount of extra stack (above minimum stack size) required by
496 *  MPCI receive server thread.  Remember that in a multiprocessor
497 *  system this thread must exist and be able to process all directives.
498 *
499 *  AVR Specific Information:
500 *
501 *  XXX document implementation including references if appropriate
502 */
503
504#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
505
506/*
507 *  This defines the number of entries in the ISR_Vector_table managed
508 *  by RTEMS.
509 *
510 *  AVR Specific Information:
511 *
512 *  XXX document implementation including references if appropriate
513 */
514
515#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
516#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
517
518/*
519 *  This is defined if the port has a special way to report the ISR nesting
520 *  level.  Most ports maintain the variable _ISR_Nest_level.
521 */
522
523#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
524
525/*
526 *  Should be large enough to run all RTEMS tests.  This ensures
527 *  that a "reasonable" small application should not have any problems.
528 *
529 *  AVR Specific Information:
530 *
531 *  XXX document implementation including references if appropriate
532 */
533
534#define CPU_STACK_MINIMUM_SIZE          (1024*4)
535
536/*
537 *  CPU's worst alignment requirement for data types on a byte boundary.  This
538 *  alignment does not take into account the requirements for the stack.
539 *
540 *  AVR Specific Information:
541 *
542 *  XXX document implementation including references if appropriate
543 */
544
545#define CPU_ALIGNMENT              8
546
547/*
548 *  This number corresponds to the byte alignment requirement for the
549 *  heap handler.  This alignment requirement may be stricter than that
550 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
551 *  common for the heap to follow the same alignment requirement as
552 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
553 *  then this should be set to CPU_ALIGNMENT.
554 *
555 *  NOTE:  This does not have to be a power of 2 although it should be
556 *         a multiple of 2 greater than or equal to 2.  The requirement
557 *         to be a multiple of 2 is because the heap uses the least
558 *         significant field of the front and back flags to indicate
559 *         that a block is in use or free.  So you do not want any odd
560 *         length blocks really putting length data in that bit.
561 *
562 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
563 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
564 *         elements allocated from the heap meet all restrictions.
565 *
566 *  AVR Specific Information:
567 *
568 *  XXX document implementation including references if appropriate
569 */
570
571#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
572
573/*
574 *  This number corresponds to the byte alignment requirement for memory
575 *  buffers allocated by the partition manager.  This alignment requirement
576 *  may be stricter than that for the data types alignment specified by
577 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
578 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
579 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
580 *
581 *  NOTE:  This does not have to be a power of 2.  It does have to
582 *         be greater or equal to than CPU_ALIGNMENT.
583 *
584 *  AVR Specific Information:
585 *
586 *  XXX document implementation including references if appropriate
587 */
588
589#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
590
591/*
592 *  This number corresponds to the byte alignment requirement for the
593 *  stack.  This alignment requirement may be stricter than that for the
594 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
595 *  is strict enough for the stack, then this should be set to 0.
596 *
597 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
598 *
599 *  AVR Specific Information:
600 *
601 *  XXX document implementation including references if appropriate
602 */
603
604#define CPU_STACK_ALIGNMENT        0
605
606/*
607 *  ISR handler macros
608 */
609
610/*
611 *  Support routine to initialize the RTEMS vector table after it is allocated.
612 *
613 *  AVR Specific Information:
614 *
615 *  XXX document implementation including references if appropriate
616 */
617
618#define _CPU_Initialize_vectors()
619
620/*
621 *  Disable all interrupts for an RTEMS critical section.  The previous
622 *  level is returned in _level.
623 *
624 *  AVR Specific Information:
625 *
626 *  XXX document implementation including references if appropriate
627 */
628
629#define _CPU_ISR_Disable( _isr_cookie ) \
630  { \
631    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
632  }
633
634/*
635 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
636 *  This indicates the end of an RTEMS critical section.  The parameter
637 *  _level is not modified.
638 *
639 *  AVR Specific Information:
640 *
641 *  XXX document implementation including references if appropriate
642 */
643
644#define _CPU_ISR_Enable( _isr_cookie )  \
645  { \
646  }
647
648/*
649 *  This temporarily restores the interrupt to _level before immediately
650 *  disabling them again.  This is used to divide long RTEMS critical
651 *  sections into two or more parts.  The parameter _level is not
652 * modified.
653 *
654 *  AVR Specific Information:
655 *
656 *  XXX document implementation including references if appropriate
657 */
658
659#define _CPU_ISR_Flash( _isr_cookie ) \
660  { \
661  }
662
663/*
664 *  Map interrupt level in task mode onto the hardware that the CPU
665 *  actually provides.  Currently, interrupt levels which do not
666 *  map onto the CPU in a generic fashion are undefined.  Someday,
667 *  it would be nice if these were "mapped" by the application
668 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
669 *  8 - 255 would be available for bsp/application specific meaning.
670 *  This could be used to manage a programmable interrupt controller
671 *  via the rtems_task_mode directive.
672 *
673 *  The get routine usually must be implemented as a subroutine.
674 *
675 *  AVR Specific Information:
676 *
677 *  XXX document implementation including references if appropriate
678 */
679
680#define _CPU_ISR_Set_level( new_level ) \
681  { \
682  }
683
684uint32_t   _CPU_ISR_Get_level( void );
685
686/* end of ISR handler macros */
687
688/* Context handler macros */
689
690/*
691 *  Initialize the context to a state suitable for starting a
692 *  task after a context restore operation.  Generally, this
693 *  involves:
694 *
695 *     - setting a starting address
696 *     - preparing the stack
697 *     - preparing the stack and frame pointers
698 *     - setting the proper interrupt level in the context
699 *     - initializing the floating point context
700 *
701 *  This routine generally does not set any unnecessary register
702 *  in the context.  The state of the "general data" registers is
703 *  undefined at task start time.
704 *
705 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
706 *        point thread.  This is typically only used on CPUs where the
707 *        FPU may be easily disabled by software such as on the SPARC
708 *        where the PSR contains an enable FPU bit.
709 *
710 *  AVR Specific Information:
711 *
712 *  XXX document implementation including references if appropriate
713 */
714
715#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
716                                 _isr, _entry_point, _is_fp ) \
717  { \
718  }
719
720/*
721 *  This routine is responsible for somehow restarting the currently
722 *  executing task.  If you are lucky, then all that is necessary
723 *  is restoring the context.  Otherwise, there will need to be
724 *  a special assembly routine which does something special in this
725 *  case.  Context_Restore should work most of the time.  It will
726 *  not work if restarting self conflicts with the stack frame
727 *  assumptions of restoring a context.
728 *
729 *  AVR Specific Information:
730 *
731 *  XXX document implementation including references if appropriate
732 */
733
734#define _CPU_Context_Restart_self( _the_context ) \
735   _CPU_Context_restore( (_the_context) );
736
737/*
738 *  The purpose of this macro is to allow the initial pointer into
739 *  a floating point context area (used to save the floating point
740 *  context) to be at an arbitrary place in the floating point
741 *  context area.
742 *
743 *  This is necessary because some FP units are designed to have
744 *  their context saved as a stack which grows into lower addresses.
745 *  Other FP units can be saved by simply moving registers into offsets
746 *  from the base of the context area.  Finally some FP units provide
747 *  a "dump context" instruction which could fill in from high to low
748 *  or low to high based on the whim of the CPU designers.
749 *
750 *  AVR Specific Information:
751 *
752 *  XXX document implementation including references if appropriate
753 */
754
755#define _CPU_Context_Fp_start( _base, _offset ) \
756   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
757
758/*
759 *  This routine initializes the FP context area passed to it to.
760 *  There are a few standard ways in which to initialize the
761 *  floating point context.  The code included for this macro assumes
762 *  that this is a CPU in which a "initial" FP context was saved into
763 *  _CPU_Null_fp_context and it simply copies it to the destination
764 *  context passed to it.
765 *
766 *  Other models include (1) not doing anything, and (2) putting
767 *  a "null FP status word" in the correct place in the FP context.
768 *
769 *  AVR Specific Information:
770 *
771 *  XXX document implementation including references if appropriate
772 */
773
774#define _CPU_Context_Initialize_fp( _destination ) \
775  { \
776   *(*(_destination)) = _CPU_Null_fp_context; \
777  }
778
779/* end of Context handler macros */
780
781/* Fatal Error manager macros */
782
783/*
784 *  This routine copies _error into a known place -- typically a stack
785 *  location or a register, optionally disables interrupts, and
786 *  halts/stops the CPU.
787 *
788 *  AVR Specific Information:
789 *
790 *  XXX document implementation including references if appropriate
791 */
792
793#define _CPU_Fatal_halt( _error ) \
794  { \
795  }
796
797/* end of Fatal Error manager macros */
798
799/* Bitfield handler macros */
800
801/*
802 *  This routine sets _output to the bit number of the first bit
803 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
804 *  This type may be either 16 or 32 bits wide although only the 16
805 *  least significant bits will be used.
806 *
807 *  There are a number of variables in using a "find first bit" type
808 *  instruction.
809 *
810 *    (1) What happens when run on a value of zero?
811 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
812 *    (3) The numbering may be zero or one based.
813 *    (4) The "find first bit" instruction may search from MSB or LSB.
814 *
815 *  RTEMS guarantees that (1) will never happen so it is not a concern.
816 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
817 *  _CPU_Priority_bits_index().  These three form a set of routines
818 *  which must logically operate together.  Bits in the _value are
819 *  set and cleared based on masks built by _CPU_Priority_mask().
820 *  The basic major and minor values calculated by _Priority_Major()
821 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
822 *  to properly range between the values returned by the "find first bit"
823 *  instruction.  This makes it possible for _Priority_Get_highest() to
824 *  calculate the major and directly index into the minor table.
825 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
826 *  is the first bit found.
827 *
828 *  This entire "find first bit" and mapping process depends heavily
829 *  on the manner in which a priority is broken into a major and minor
830 *  components with the major being the 4 MSB of a priority and minor
831 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
832 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
833 *  to the lowest priority.
834 *
835 *  If your CPU does not have a "find first bit" instruction, then
836 *  there are ways to make do without it.  Here are a handful of ways
837 *  to implement this in software:
838 *
839 *    - a series of 16 bit test instructions
840 *    - a "binary search using if's"
841 *    - _number = 0
842 *      if _value > 0x00ff
843 *        _value >>=8
844 *        _number = 8;
845 *
846 *      if _value > 0x0000f
847 *        _value >=8
848 *        _number += 4
849 *
850 *      _number += bit_set_table[ _value ]
851 *
852 *    where bit_set_table[ 16 ] has values which indicate the first
853 *      bit set
854 *
855 *  AVR Specific Information:
856 *
857 *  XXX document implementation including references if appropriate
858 */
859
860#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
861#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
862
863#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
864
865#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
866  { \
867    (_output) = 0;   /* do something to prevent warnings */ \
868  }
869
870#endif
871
872/* end of Bitfield handler macros */
873
874/*
875 *  This routine builds the mask which corresponds to the bit fields
876 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
877 *  for that routine.
878 *
879 *  AVR Specific Information:
880 *
881 *  XXX document implementation including references if appropriate
882 */
883
884#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
885
886#define _CPU_Priority_Mask( _bit_number ) \
887  ( 1 << (_bit_number) )
888
889#endif
890
891/*
892 *  This routine translates the bit numbers returned by
893 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
894 *  a major or minor component of a priority.  See the discussion
895 *  for that routine.
896 *
897 *  AVR Specific Information:
898 *
899 *  XXX document implementation including references if appropriate
900 */
901
902#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
903
904#define _CPU_Priority_bits_index( _priority ) \
905  (_priority)
906
907#endif
908
909/* end of Priority handler macros */
910
911/* functions */
912
913/*
914 *  _CPU_Initialize
915 *
916 *  This routine performs CPU dependent initialization.
917 *
918 *  AVR Specific Information:
919 *
920 *  XXX document implementation including references if appropriate
921 */
922
923void _CPU_Initialize(void);
924
925/*
926 *  _CPU_ISR_install_raw_handler
927 *
928 *  This routine installs a "raw" interrupt handler directly into the
929 *  processor's vector table.
930 *
931 *  AVR Specific Information:
932 *
933 *  XXX document implementation including references if appropriate
934 */
935 
936void _CPU_ISR_install_raw_handler(
937  uint32_t    vector,
938  proc_ptr    new_handler,
939  proc_ptr   *old_handler
940);
941
942/*
943 *  _CPU_ISR_install_vector
944 *
945 *  This routine installs an interrupt vector.
946 *
947 *  AVR Specific Information:
948 *
949 *  XXX document implementation including references if appropriate
950 */
951
952void _CPU_ISR_install_vector(
953  uint32_t    vector,
954  proc_ptr    new_handler,
955  proc_ptr   *old_handler
956);
957
958/*
959 *  _CPU_Install_interrupt_stack
960 *
961 *  This routine installs the hardware interrupt stack pointer.
962 *
963 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
964 *         is TRUE.
965 *
966 *  AVR Specific Information:
967 *
968 *  XXX document implementation including references if appropriate
969 */
970
971void _CPU_Install_interrupt_stack( void );
972
973/*
974 *  _CPU_Thread_Idle_body
975 *
976 *  This routine is the CPU dependent IDLE thread body.
977 *
978 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
979 *         is TRUE.
980 *
981 *  AVR Specific Information:
982 *
983 *  XXX document implementation including references if appropriate
984 */
985
986void *_CPU_Thread_Idle_body( uint32_t );
987
988/*
989 *  _CPU_Context_switch
990 *
991 *  This routine switches from the run context to the heir context.
992 *
993 *  AVR Specific Information:
994 *
995 *  XXX document implementation including references if appropriate
996 */
997
998void _CPU_Context_switch(
999  Context_Control  *run,
1000  Context_Control  *heir
1001);
1002
1003/*
1004 *  _CPU_Context_restore
1005 *
1006 *  This routine is generally used only to restart self in an
1007 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1008 *
1009 *  NOTE: May be unnecessary to reload some registers.
1010 *
1011 *  AVR Specific Information:
1012 *
1013 *  XXX document implementation including references if appropriate
1014 */
1015
1016void _CPU_Context_restore(
1017  Context_Control *new_context
1018);
1019
1020/*
1021 *  _CPU_Context_save_fp
1022 *
1023 *  This routine saves the floating point context passed to it.
1024 *
1025 *  AVR Specific Information:
1026 *
1027 *  XXX document implementation including references if appropriate
1028 */
1029
1030void _CPU_Context_save_fp(
1031  Context_Control_fp **fp_context_ptr
1032);
1033
1034/*
1035 *  _CPU_Context_restore_fp
1036 *
1037 *  This routine restores the floating point context passed to it.
1038 *
1039 *  AVR Specific Information:
1040 *
1041 *  XXX document implementation including references if appropriate
1042 */
1043
1044void _CPU_Context_restore_fp(
1045  Context_Control_fp **fp_context_ptr
1046);
1047
1048/*  The following routine swaps the endian format of an unsigned int.
1049 *  It must be static because it is referenced indirectly.
1050 *
1051 *  This version will work on any processor, but if there is a better
1052 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1053 *
1054 *     swap least significant two bytes with 16-bit rotate
1055 *     swap upper and lower 16-bits
1056 *     swap most significant two bytes with 16-bit rotate
1057 *
1058 *  Some CPUs have special instructions which swap a 32-bit quantity in
1059 *  a single instruction (e.g. i486).  It is probably best to avoid
1060 *  an "endian swapping control bit" in the CPU.  One good reason is
1061 *  that interrupts would probably have to be disabled to ensure that
1062 *  an interrupt does not try to access the same "chunk" with the wrong
1063 *  endian.  Another good reason is that on some CPUs, the endian bit
1064 *  endianness for ALL fetches -- both code and data -- so the code
1065 *  will be fetched incorrectly.
1066 *
1067 *  AVR Specific Information:
1068 *
1069 *  XXX document implementation including references if appropriate
1070 */
1071 
1072static inline uint32_t CPU_swap_u32(
1073  uint32_t value
1074)
1075{
1076  uint32_t   byte1, byte2, byte3, byte4, swapped;
1077 
1078  byte4 = (value >> 24) & 0xff;
1079  byte3 = (value >> 16) & 0xff;
1080  byte2 = (value >> 8)  & 0xff;
1081  byte1 =  value        & 0xff;
1082 
1083  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1084  return( swapped );
1085}
1086
1087#define CPU_swap_u16( value ) \
1088  (((value&0xff) << 8) | ((value >> 8)&0xff))
1089
1090#ifdef __cplusplus
1091}
1092#endif
1093
1094#endif
Note: See TracBrowser for help on using the repository browser.