source: rtems/cpukit/score/cpu/avr/rtems/score/cpu.h @ 815994f

4.115
Last change on this file since 815994f was 815994f, checked in by Sebastian Huber <sebastian.huber@…>, on 11/25/12 at 16:48:11

score: Add CPU_Exception_frame

Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().

The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().

Add rtems_exception_frame and rtems_exception_frame_print().

Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.

Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().

Add test sptests/spfatal26.

  • Property mode set to 100644
File size: 35.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the AVR
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 */
16
17#ifndef _RTEMS_SCORE_CPU_H
18#define _RTEMS_SCORE_CPU_H
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24#include <rtems/score/types.h>
25#include <rtems/score/avr.h>
26#include <avr/common.h>
27
28/* conditional compilation parameters */
29
30#ifndef RTEMS_USE_16_BIT_OBJECT
31#define RTEMS_USE_16_BIT_OBJECT
32#endif
33
34/*
35 *  Should the calls to _Thread_Enable_dispatch be inlined?
36 *
37 *  If TRUE, then they are inlined.
38 *  If FALSE, then a subroutine call is made.
39 *
40 *  Basically this is an example of the classic trade-off of size
41 *  versus speed.  Inlining the call (TRUE) typically increases the
42 *  size of RTEMS while speeding up the enabling of dispatching.
43 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
44 *  only be 0 or 1 unless you are in an interrupt handler and that
45 *  interrupt handler invokes the executive.]  When not inlined
46 *  something calls _Thread_Enable_dispatch which in turns calls
47 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
48 *  one subroutine call is avoided entirely.]
49 *
50 *  AVR Specific Information:
51 *
52 *  XXX document implementation including references if appropriate
53 */
54
55#define CPU_INLINE_ENABLE_DISPATCH       FALSE
56
57/*
58 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
59 *  be unrolled one time?  In unrolled each iteration of the loop examines
60 *  two "nodes" on the chain being searched.  Otherwise, only one node
61 *  is examined per iteration.
62 *
63 *  If TRUE, then the loops are unrolled.
64 *  If FALSE, then the loops are not unrolled.
65 *
66 *  The primary factor in making this decision is the cost of disabling
67 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
68 *  body of the loop.  On some CPUs, the flash is more expensive than
69 *  one iteration of the loop body.  In this case, it might be desirable
70 *  to unroll the loop.  It is important to note that on some CPUs, this
71 *  code is the longest interrupt disable period in RTEMS.  So it is
72 *  necessary to strike a balance when setting this parameter.
73 *
74 *  AVR Specific Information:
75 *
76 *  XXX document implementation including references if appropriate
77 */
78
79#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
80
81/*
82 *  Does RTEMS manage a dedicated interrupt stack in software?
83 *
84 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
85 *  If FALSE, nothing is done.
86 *
87 *  If the CPU supports a dedicated interrupt stack in hardware,
88 *  then it is generally the responsibility of the BSP to allocate it
89 *  and set it up.
90 *
91 *  If the CPU does not support a dedicated interrupt stack, then
92 *  the porter has two options: (1) execute interrupts on the
93 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
94 *  interrupt stack.
95 *
96 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 *  possible that both are FALSE for a particular CPU.  Although it
101 *  is unclear what that would imply about the interrupt processing
102 *  procedure on that CPU.
103 *
104 *  AVR Specific Information:
105 *
106 *  XXX document implementation including references if appropriate
107 */
108
109#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
110
111/*
112 *  Does this CPU have hardware support for a dedicated interrupt stack?
113 *
114 *  If TRUE, then it must be installed during initialization.
115 *  If FALSE, then no installation is performed.
116 *
117 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
118 *
119 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
120 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
121 *  possible that both are FALSE for a particular CPU.  Although it
122 *  is unclear what that would imply about the interrupt processing
123 *  procedure on that CPU.
124 *
125 *  AVR Specific Information:
126 *
127 *  XXX document implementation including references if appropriate
128 */
129
130#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
131
132/*
133 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
134 *
135 *  If TRUE, then the memory is allocated during initialization.
136 *  If FALSE, then the memory is allocated during initialization.
137 *
138 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
139 *
140 *  AVR Specific Information:
141 *
142 *  XXX document implementation including references if appropriate
143 */
144
145#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
146
147/*
148 *  Does the RTEMS invoke the user's ISR with the vector number and
149 *  a pointer to the saved interrupt frame (1) or just the vector
150 *  number (0)?
151 *
152 *  AVR Specific Information:
153 *
154 *  XXX document implementation including references if appropriate
155 */
156
157#define CPU_ISR_PASSES_FRAME_POINTER 0
158
159/*
160 *  Does the CPU follow the simple vectored interrupt model?
161 *
162 *  If TRUE, then RTEMS allocates the vector table it internally manages.
163 *  If FALSE, then the BSP is assumed to allocate and manage the vector
164 *  table
165 *
166 *  AVR Specific Information:
167 *
168 *  XXX document implementation including references if appropriate
169 */
170#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
171
172/*
173 *  Does the CPU have hardware floating point?
174 *
175 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
176 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
177 *
178 *  If there is a FP coprocessor such as the i387 or mc68881, then
179 *  the answer is TRUE.
180 *
181 *  The macro name "AVR_HAS_FPU" should be made CPU specific.
182 *  It indicates whether or not this CPU model has FP support.  For
183 *  example, it would be possible to have an i386_nofp CPU model
184 *  which set this to false to indicate that you have an i386 without
185 *  an i387 and wish to leave floating point support out of RTEMS.
186 *
187 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
188 *  is software implemented floating point that must be context
189 *  switched.  The determination of whether or not this applies
190 *  is very tool specific and the state saved/restored is also
191 *  compiler specific.
192 *
193 *  AVR Specific Information:
194 *
195 *  XXX document implementation including references if appropriate
196 */
197
198#if ( AVR_HAS_FPU == 1 )
199#define CPU_HARDWARE_FP     TRUE
200#else
201#define CPU_HARDWARE_FP     FALSE
202#endif
203#define CPU_SOFTWARE_FP     FALSE
204
205/*
206 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
207 *
208 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
209 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
210 *
211 *  So far, the only CPUs in which this option has been used are the
212 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
213 *  gcc both implicitly used the floating point registers to perform
214 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
215 *  seen to allocate floating point local variables and touch the FPU
216 *  even when the flow through a subroutine (like vfprintf()) might
217 *  not use floating point formats.
218 *
219 *  If a function which you would not think utilize the FP unit DOES,
220 *  then one can not easily predict which tasks will use the FP hardware.
221 *  In this case, this option should be TRUE.
222 *
223 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
224 *
225 *  AVR Specific Information:
226 *
227 *  XXX document implementation including references if appropriate
228 */
229
230#define CPU_ALL_TASKS_ARE_FP     TRUE
231
232/*
233 *  Should the IDLE task have a floating point context?
234 *
235 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
236 *  and it has a floating point context which is switched in and out.
237 *  If FALSE, then the IDLE task does not have a floating point context.
238 *
239 *  Setting this to TRUE negatively impacts the time required to preempt
240 *  the IDLE task from an interrupt because the floating point context
241 *  must be saved as part of the preemption.
242 *
243 *  AVR Specific Information:
244 *
245 *  XXX document implementation including references if appropriate
246 */
247
248#define CPU_IDLE_TASK_IS_FP      FALSE
249
250/*
251 *  Should the saving of the floating point registers be deferred
252 *  until a context switch is made to another different floating point
253 *  task?
254 *
255 *  If TRUE, then the floating point context will not be stored until
256 *  necessary.  It will remain in the floating point registers and not
257 *  disturned until another floating point task is switched to.
258 *
259 *  If FALSE, then the floating point context is saved when a floating
260 *  point task is switched out and restored when the next floating point
261 *  task is restored.  The state of the floating point registers between
262 *  those two operations is not specified.
263 *
264 *  If the floating point context does NOT have to be saved as part of
265 *  interrupt dispatching, then it should be safe to set this to TRUE.
266 *
267 *  Setting this flag to TRUE results in using a different algorithm
268 *  for deciding when to save and restore the floating point context.
269 *  The deferred FP switch algorithm minimizes the number of times
270 *  the FP context is saved and restored.  The FP context is not saved
271 *  until a context switch is made to another, different FP task.
272 *  Thus in a system with only one FP task, the FP context will never
273 *  be saved or restored.
274 *
275 *  AVR Specific Information:
276 *
277 *  XXX document implementation including references if appropriate
278 */
279
280#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
281
282/*
283 *  Does this port provide a CPU dependent IDLE task implementation?
284 *
285 *  If TRUE, then the routine _CPU_Thread_Idle_body
286 *  must be provided and is the default IDLE thread body instead of
287 *  _CPU_Thread_Idle_body.
288 *
289 *  If FALSE, then use the generic IDLE thread body if the BSP does
290 *  not provide one.
291 *
292 *  This is intended to allow for supporting processors which have
293 *  a low power or idle mode.  When the IDLE thread is executed, then
294 *  the CPU can be powered down.
295 *
296 *  The order of precedence for selecting the IDLE thread body is:
297 *
298 *    1.  BSP provided
299 *    2.  CPU dependent (if provided)
300 *    3.  generic (if no BSP and no CPU dependent)
301 *
302 *  AVR Specific Information:
303 *
304 *  XXX document implementation including references if appropriate
305 */
306
307#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
308
309/*
310 *  Does the stack grow up (toward higher addresses) or down
311 *  (toward lower addresses)?
312 *
313 *  If TRUE, then the grows upward.
314 *  If FALSE, then the grows toward smaller addresses.
315 *
316 *  AVR Specific Information:
317 *
318 *  XXX document implementation including references if appropriate
319 */
320
321#define CPU_STACK_GROWS_UP               FALSE
322
323/*
324 *  The following is the variable attribute used to force alignment
325 *  of critical RTEMS structures.  On some processors it may make
326 *  sense to have these aligned on tighter boundaries than
327 *  the minimum requirements of the compiler in order to have as
328 *  much of the critical data area as possible in a cache line.
329 *
330 *  The placement of this macro in the declaration of the variables
331 *  is based on the syntactically requirements of the GNU C
332 *  "__attribute__" extension.  For example with GNU C, use
333 *  the following to force a structures to a 32 byte boundary.
334 *
335 *      __attribute__ ((aligned (32)))
336 *
337 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
338 *         To benefit from using this, the data must be heavily
339 *         used so it will stay in the cache and used frequently enough
340 *         in the executive to justify turning this on.
341 *
342 *  AVR Specific Information:
343 *
344 *  XXX document implementation including references if appropriate
345 */
346
347#define CPU_STRUCTURE_ALIGNMENT
348
349#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
350
351/*
352 *  Define what is required to specify how the network to host conversion
353 *  routines are handled.
354 *
355 *  AVR Specific Information:
356 *
357 *  XXX document implementation including references if appropriate
358 */
359
360#define CPU_BIG_ENDIAN                           TRUE
361#define CPU_LITTLE_ENDIAN                        FALSE
362
363/*
364 *  The following defines the number of bits actually used in the
365 *  interrupt field of the task mode.  How those bits map to the
366 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
367 *
368 *  AVR Specific Information:
369 *
370 *  XXX document implementation including references if appropriate
371 */
372
373#define CPU_MODES_INTERRUPT_MASK   0x00000001
374
375/*
376 *  Processor defined structures required for cpukit/score.
377 *
378 *  AVR Specific Information:
379 *
380 *  XXX document implementation including references if appropriate
381 */
382
383/* may need to put some structures here.  */
384
385#ifndef ASM
386
387/*
388 * Contexts
389 *
390 *  Generally there are 2 types of context to save.
391 *     1. Interrupt registers to save
392 *     2. Task level registers to save
393 *
394 *  This means we have the following 3 context items:
395 *     1. task level context stuff::  Context_Control
396 *     2. floating point task stuff:: Context_Control_fp
397 *     3. special interrupt level context :: Context_Control_interrupt
398 *
399 *  On some processors, it is cost-effective to save only the callee
400 *  preserved registers during a task context switch.  This means
401 *  that the ISR code needs to save those registers which do not
402 *  persist across function calls.  It is not mandatory to make this
403 *  distinctions between the caller/callee saves registers for the
404 *  purpose of minimizing context saved during task switch and on interrupts.
405 *  If the cost of saving extra registers is minimal, simplicity is the
406 *  choice.  Save the same context on interrupt entry as for tasks in
407 *  this case.
408 *
409 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
410 *  care should be used in designing the context area.
411 *
412 *  On some CPUs with hardware floating point support, the Context_Control_fp
413 *  structure will not be used or it simply consist of an array of a
414 *  fixed number of bytes.   This is done when the floating point context
415 *  is dumped by a "FP save context" type instruction and the format
416 *  is not really defined by the CPU.  In this case, there is no need
417 *  to figure out the exact format -- only the size.  Of course, although
418 *  this is enough information for RTEMS, it is probably not enough for
419 *  a debugger such as gdb.  But that is another problem.
420 *
421 *  AVR Specific Information:
422 *
423 *  XXX document implementation including references if appropriate
424 */
425
426typedef struct {
427        uint16_t        stack_pointer;
428        uint8_t         status; /* SREG */
429} Context_Control;
430
431#define _CPU_Context_Get_SP( _context ) \
432  (_context)->stack_pointer
433
434
435
436
437typedef struct {
438    double      some_float_register;
439} Context_Control_fp;
440
441typedef struct {
442    uint32_t   special_interrupt_register;
443} CPU_Interrupt_frame;
444
445/*
446 *  This variable is optional.  It is used on CPUs on which it is difficult
447 *  to generate an "uninitialized" FP context.  It is filled in by
448 *  _CPU_Initialize and copied into the task's FP context area during
449 *  _CPU_Context_Initialize.
450 *
451 *  AVR Specific Information:
452 *
453 *  XXX document implementation including references if appropriate
454 */
455
456SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
457
458#endif /* ASM */
459
460/*
461 *  Nothing prevents the porter from declaring more CPU specific variables.
462 *
463 *  AVR Specific Information:
464 *
465 *  XXX document implementation including references if appropriate
466 */
467
468/* XXX: if needed, put more variables here */
469
470/*
471 *  The size of the floating point context area.  On some CPUs this
472 *  will not be a "sizeof" because the format of the floating point
473 *  area is not defined -- only the size is.  This is usually on
474 *  CPUs with a "floating point save context" instruction.
475 *
476 *  AVR Specific Information:
477 *
478 *  XXX document implementation including references if appropriate
479 */
480
481#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
482
483/*
484 *  Amount of extra stack (above minimum stack size) required by
485 *  MPCI receive server thread.  Remember that in a multiprocessor
486 *  system this thread must exist and be able to process all directives.
487 *
488 *  AVR Specific Information:
489 *
490 *  XXX document implementation including references if appropriate
491 */
492
493#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
494
495/*
496 *  This defines the number of entries in the ISR_Vector_table managed
497 *  by RTEMS.
498 *
499 *  AVR Specific Information:
500 *
501 *  XXX document implementation including references if appropriate
502 */
503
504#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
505#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
506
507/*
508 *  This is defined if the port has a special way to report the ISR nesting
509 *  level.  Most ports maintain the variable _ISR_Nest_level.
510 */
511
512#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
513
514/*
515 *  Should be large enough to run all RTEMS tests.  This ensures
516 *  that a "reasonable" small application should not have any problems.
517 *
518 *  AVR Specific Information:
519 *
520 *  XXX document implementation including references if appropriate
521 */
522
523#define CPU_STACK_MINIMUM_SIZE          512
524
525/*
526 *  Maximum priority of a thread. Note based from 0 which is the idle task.
527 */
528#define CPU_PRIORITY_MAXIMUM             15
529
530#define CPU_SIZEOF_POINTER 2
531
532/*
533 *  CPU's worst alignment requirement for data types on a byte boundary.  This
534 *  alignment does not take into account the requirements for the stack.
535 *
536 *  AVR Specific Information:
537 *
538 *  XXX document implementation including references if appropriate
539 */
540
541#define CPU_ALIGNMENT              4
542
543/*
544 *  This number corresponds to the byte alignment requirement for the
545 *  heap handler.  This alignment requirement may be stricter than that
546 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
547 *  common for the heap to follow the same alignment requirement as
548 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
549 *  then this should be set to CPU_ALIGNMENT.
550 *
551 *  NOTE:  This does not have to be a power of 2 although it should be
552 *         a multiple of 2 greater than or equal to 2.  The requirement
553 *         to be a multiple of 2 is because the heap uses the least
554 *         significant field of the front and back flags to indicate
555 *         that a block is in use or free.  So you do not want any odd
556 *         length blocks really putting length data in that bit.
557 *
558 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
559 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
560 *         elements allocated from the heap meet all restrictions.
561 *
562 *  AVR Specific Information:
563 *
564 *  XXX document implementation including references if appropriate
565 */
566
567#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
568
569/*
570 *  This number corresponds to the byte alignment requirement for memory
571 *  buffers allocated by the partition manager.  This alignment requirement
572 *  may be stricter than that for the data types alignment specified by
573 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
574 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
575 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
576 *
577 *  NOTE:  This does not have to be a power of 2.  It does have to
578 *         be greater or equal to than CPU_ALIGNMENT.
579 *
580 *  AVR Specific Information:
581 *
582 *  XXX document implementation including references if appropriate
583 */
584
585#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
586
587/*
588 *  This number corresponds to the byte alignment requirement for the
589 *  stack.  This alignment requirement may be stricter than that for the
590 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
591 *  is strict enough for the stack, then this should be set to 0.
592 *
593 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
594 *
595 *  AVR Specific Information:
596 *
597 *  XXX document implementation including references if appropriate
598 */
599
600#define CPU_STACK_ALIGNMENT        0
601
602/*
603 *  ISR handler macros
604 */
605
606/*
607 *  Support routine to initialize the RTEMS vector table after it is allocated.
608 *
609 *  AVR Specific Information:
610 *
611 *  XXX document implementation including references if appropriate
612 */
613
614#define _CPU_Initialize_vectors()
615
616/*
617 *  Disable all interrupts for an RTEMS critical section.  The previous
618 *  level is returned in _level.
619 *
620 *  AVR Specific Information:
621 *
622 *  XXX document implementation including references if appropriate
623 */
624
625#define _CPU_ISR_Disable( _isr_cookie ) \
626  do { \
627        (_isr_cookie) = SREG; \
628        __asm__ volatile ("cli"::); \
629  } while (0)
630
631/*
632 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
633 *  This indicates the end of an RTEMS critical section.  The parameter
634 *  _level is not modified.
635 *
636 *  AVR Specific Information:
637 *
638 *  XXX document implementation including references if appropriate
639 */
640
641#define _CPU_ISR_Enable( _isr_cookie )  \
642  do { \
643        SREG  = _isr_cookie; \
644        __asm__ volatile ("sei"::); \
645  } while (0)
646
647/*
648 *  This temporarily restores the interrupt to _level before immediately
649 *  disabling them again.  This is used to divide long RTEMS critical
650 *  sections into two or more parts.  The parameter _level is not
651 * modified.
652 *
653 *  AVR Specific Information:
654 *
655 *  XXX document implementation including references if appropriate
656 */
657
658#define _CPU_ISR_Flash( _isr_cookie ) \
659  do { \
660        SREG=(_isr_cookie); \
661        __asm__ volatile("sei"::); \
662        (_isr_cookie) = SREG; \
663        __asm__ volatile("cli"::); \
664  } while (0)
665
666/*
667 *  Map interrupt level in task mode onto the hardware that the CPU
668 *  actually provides.  Currently, interrupt levels which do not
669 *  map onto the CPU in a generic fashion are undefined.  Someday,
670 *  it would be nice if these were "mapped" by the application
671 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
672 *  8 - 255 would be available for bsp/application specific meaning.
673 *  This could be used to manage a programmable interrupt controller
674 *  via the rtems_task_mode directive.
675 *
676 *  The get routine usually must be implemented as a subroutine.
677 *
678 *  AVR Specific Information:
679 *
680 *  XXX document implementation including references if appropriate
681 */
682
683#define _CPU_ISR_Set_level( new_level ) \
684  { \
685  }
686
687#ifndef ASM
688
689uint32_t   _CPU_ISR_Get_level( void );
690
691/* end of ISR handler macros */
692
693/* Context handler macros */
694
695/*
696 *  Initialize the context to a state suitable for starting a
697 *  task after a context restore operation.  Generally, this
698 *  involves:
699 *
700 *     - setting a starting address
701 *     - preparing the stack
702 *     - preparing the stack and frame pointers
703 *     - setting the proper interrupt level in the context
704 *     - initializing the floating point context
705 *
706 *  This routine generally does not set any unnecessary register
707 *  in the context.  The state of the "general data" registers is
708 *  undefined at task start time.
709 *
710 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
711 *        point thread.  This is typically only used on CPUs where the
712 *        FPU may be easily disabled by software such as on the SPARC
713 *        where the PSR contains an enable FPU bit.
714 *
715 *  AVR Specific Information:
716 *
717 *  XXX document implementation including references if appropriate
718 */
719/*
720#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
721                                 _isr, _entry_point, _is_fp ) \
722  \
723        do { \
724        uint16_t *_stack;\
725        _stack  = (uint16_t) (_stack_base) + (uint16_t)(_size);\
726        (_the_context)->stack_pointer = _stack-1;       \
727        *(_stack) = *(_entry_point);    \
728        printk("the ret address is %x\n", *(uint16_t *)(_stack));\
729        printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \
730        printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\
731        printk("struct starting address = 0x%x\n", _the_context);\
732        printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\
733        } while ( 0 )
734
735*/
736/*
737 *  This routine is responsible for somehow restarting the currently
738 *  executing task.  If you are lucky, then all that is necessary
739 *  is restoring the context.  Otherwise, there will need to be
740 *  a special assembly routine which does something special in this
741 *  case.  Context_Restore should work most of the time.  It will
742 *  not work if restarting self conflicts with the stack frame
743 *  assumptions of restoring a context.
744 *
745 *  AVR Specific Information:
746 *
747 *  XXX document implementation including references if appropriate
748 */
749
750#define _CPU_Context_Restart_self( _the_context ) \
751   _CPU_Context_restore( _the_context );
752
753/*
754 *  The purpose of this macro is to allow the initial pointer into
755 *  a floating point context area (used to save the floating point
756 *  context) to be at an arbitrary place in the floating point
757 *  context area.
758 *
759 *  This is necessary because some FP units are designed to have
760 *  their context saved as a stack which grows into lower addresses.
761 *  Other FP units can be saved by simply moving registers into offsets
762 *  from the base of the context area.  Finally some FP units provide
763 *  a "dump context" instruction which could fill in from high to low
764 *  or low to high based on the whim of the CPU designers.
765 *
766 *  AVR Specific Information:
767 *
768 *  XXX document implementation including references if appropriate
769 */
770
771#define _CPU_Context_Fp_start( _base, _offset ) \
772   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
773
774/*
775 *  This routine initializes the FP context area passed to it to.
776 *  There are a few standard ways in which to initialize the
777 *  floating point context.  The code included for this macro assumes
778 *  that this is a CPU in which a "initial" FP context was saved into
779 *  _CPU_Null_fp_context and it simply copies it to the destination
780 *  context passed to it.
781 *
782 *  Other models include (1) not doing anything, and (2) putting
783 *  a "null FP status word" in the correct place in the FP context.
784 *
785 *  AVR Specific Information:
786 *
787 *  XXX document implementation including references if appropriate
788 */
789
790#define _CPU_Context_Initialize_fp( _destination ) \
791  { \
792   *(*(_destination)) = _CPU_Null_fp_context; \
793  }
794
795/* end of Context handler macros */
796
797/* Fatal Error manager macros */
798
799/*
800 *  This routine copies _error into a known place -- typically a stack
801 *  location or a register, optionally disables interrupts, and
802 *  halts/stops the CPU.
803 *
804 *  AVR Specific Information:
805 *
806 *  XXX document implementation including references if appropriate
807 */
808
809#define _CPU_Fatal_halt( _error ) \
810  { \
811  }
812
813/* end of Fatal Error manager macros */
814
815/* Bitfield handler macros */
816
817/*
818 *  This routine sets _output to the bit number of the first bit
819 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
820 *  This type may be either 16 or 32 bits wide although only the 16
821 *  least significant bits will be used.
822 *
823 *  There are a number of variables in using a "find first bit" type
824 *  instruction.
825 *
826 *    (1) What happens when run on a value of zero?
827 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
828 *    (3) The numbering may be zero or one based.
829 *    (4) The "find first bit" instruction may search from MSB or LSB.
830 *
831 *  RTEMS guarantees that (1) will never happen so it is not a concern.
832 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
833 *  _CPU_Priority_bits_index().  These three form a set of routines
834 *  which must logically operate together.  Bits in the _value are
835 *  set and cleared based on masks built by _CPU_Priority_mask().
836 *  The basic major and minor values calculated by _Priority_Major()
837 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
838 *  to properly range between the values returned by the "find first bit"
839 *  instruction.  This makes it possible for _Priority_Get_highest() to
840 *  calculate the major and directly index into the minor table.
841 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
842 *  is the first bit found.
843 *
844 *  This entire "find first bit" and mapping process depends heavily
845 *  on the manner in which a priority is broken into a major and minor
846 *  components with the major being the 4 MSB of a priority and minor
847 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
848 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
849 *  to the lowest priority.
850 *
851 *  If your CPU does not have a "find first bit" instruction, then
852 *  there are ways to make do without it.  Here are a handful of ways
853 *  to implement this in software:
854 *
855 *    - a series of 16 bit test instructions
856 *    - a "binary search using if's"
857 *    - _number = 0
858 *      if _value > 0x00ff
859 *        _value >>=8
860 *        _number = 8;
861 *
862 *      if _value > 0x0000f
863 *        _value >=8
864 *        _number += 4
865 *
866 *      _number += bit_set_table[ _value ]
867 *
868 *    where bit_set_table[ 16 ] has values which indicate the first
869 *      bit set
870 *
871 *  AVR Specific Information:
872 *
873 *  XXX document implementation including references if appropriate
874 */
875
876#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
877#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
878
879#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
880
881#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
882  { \
883    (_output) = 0;   /* do something to prevent warnings */ \
884  }
885
886#endif
887
888/* end of Bitfield handler macros */
889
890/*
891 *  This routine builds the mask which corresponds to the bit fields
892 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
893 *  for that routine.
894 *
895 *  AVR Specific Information:
896 *
897 *  XXX document implementation including references if appropriate
898 */
899
900#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
901
902#define _CPU_Priority_Mask( _bit_number ) \
903  ( 1 << (_bit_number) )
904
905#endif
906
907/*
908 *  This routine translates the bit numbers returned by
909 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
910 *  a major or minor component of a priority.  See the discussion
911 *  for that routine.
912 *
913 *  AVR Specific Information:
914 *
915 *  XXX document implementation including references if appropriate
916 */
917
918#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
919
920#define _CPU_Priority_bits_index( _priority ) \
921  (_priority)
922
923#endif
924
925/* end of Priority handler macros */
926
927/* functions */
928
929/*context_initialize asm-function*/
930
931void context_initialize(unsigned short* context,
932                unsigned short stack_add,
933                unsigned short entry_point);
934
935/*
936 *  _CPU_Context_Initialize
937 *
938 *  This kernel routine initializes the basic non-FP context area associated
939 *  with each thread.
940 *
941 *  Input parameters:
942 *    the_context  - pointer to the context area
943 *    stack_base   - address of memory for the SPARC
944 *    size         - size in bytes of the stack area
945 *    new_level    - interrupt level for this context area
946 *    entry_point  - the starting execution point for this this context
947 *    is_fp        - TRUE if this context is associated with an FP thread
948 *
949 *  Output parameters: NONE
950 */
951
952void _CPU_Context_Initialize(
953  Context_Control  *the_context,
954  uint32_t         *stack_base,
955  uint32_t          size,
956  uint32_t          new_level,
957  void             *entry_point,
958  bool              is_fp
959);
960
961/*
962*
963*  _CPU_Push
964*
965*  this routine pushes 2 bytes onto the stack
966*
967*
968*
969*
970*
971*
972*
973*/
974
975void _CPU_Push(uint16_t _SP_, uint16_t entry_point);
976
977
978
979
980/*
981 *  _CPU_Initialize
982 *
983 *  This routine performs CPU dependent initialization.
984 *
985 *  AVR Specific Information:
986 *
987 *  XXX document implementation including references if appropriate
988 */
989
990void _CPU_Initialize(void);
991
992/*
993 *  _CPU_ISR_install_raw_handler
994 *
995 *  This routine installs a "raw" interrupt handler directly into the
996 *  processor's vector table.
997 *
998 *  AVR Specific Information:
999 *
1000 *  XXX document implementation including references if appropriate
1001 */
1002
1003void _CPU_ISR_install_raw_handler(
1004  uint32_t    vector,
1005  proc_ptr    new_handler,
1006  proc_ptr   *old_handler
1007);
1008
1009/*
1010 *  _CPU_ISR_install_vector
1011 *
1012 *  This routine installs an interrupt vector.
1013 *
1014 *  AVR Specific Information:
1015 *
1016 *  XXX document implementation including references if appropriate
1017 */
1018
1019void _CPU_ISR_install_vector(
1020  uint32_t    vector,
1021  proc_ptr    new_handler,
1022  proc_ptr   *old_handler
1023);
1024
1025/*
1026 *  _CPU_Install_interrupt_stack
1027 *
1028 *  This routine installs the hardware interrupt stack pointer.
1029 *
1030 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1031 *         is TRUE.
1032 *
1033 *  AVR Specific Information:
1034 *
1035 *  XXX document implementation including references if appropriate
1036 */
1037
1038void _CPU_Install_interrupt_stack( void );
1039
1040/*
1041 *  _CPU_Thread_Idle_body
1042 *
1043 *  This routine is the CPU dependent IDLE thread body.
1044 *
1045 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1046 *         is TRUE.
1047 *
1048 *  AVR Specific Information:
1049 *
1050 *  XXX document implementation including references if appropriate
1051 */
1052
1053void *_CPU_Thread_Idle_body( uintptr_t ignored );
1054
1055/*
1056 *  _CPU_Context_switch
1057 *
1058 *  This routine switches from the run context to the heir context.
1059 *
1060 *  AVR Specific Information:
1061 *
1062 *  XXX document implementation including references if appropriate
1063 */
1064
1065void _CPU_Context_switch(
1066  Context_Control  *run,
1067  Context_Control  *heir
1068);
1069
1070/*
1071 *  _CPU_Context_restore
1072 *
1073 *  This routine is generally used only to restart self in an
1074 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1075 *
1076 *  NOTE: May be unnecessary to reload some registers.
1077 *
1078 *  AVR Specific Information:
1079 *
1080 *  XXX document implementation including references if appropriate
1081 */
1082
1083void _CPU_Context_restore(
1084  Context_Control *new_context
1085) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1086
1087/*
1088 *  _CPU_Context_save_fp
1089 *
1090 *  This routine saves the floating point context passed to it.
1091 *
1092 *  AVR Specific Information:
1093 *
1094 *  XXX document implementation including references if appropriate
1095 */
1096
1097void _CPU_Context_save_fp(
1098  Context_Control_fp **fp_context_ptr
1099);
1100
1101/*
1102 *  _CPU_Context_restore_fp
1103 *
1104 *  This routine restores the floating point context passed to it.
1105 *
1106 *  AVR Specific Information:
1107 *
1108 *  XXX document implementation including references if appropriate
1109 */
1110
1111void _CPU_Context_restore_fp(
1112  Context_Control_fp **fp_context_ptr
1113);
1114
1115/* FIXME */
1116typedef CPU_Interrupt_frame CPU_Exception_frame;
1117
1118void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1119
1120/*  The following routine swaps the endian format of an unsigned int.
1121 *  It must be static because it is referenced indirectly.
1122 *
1123 *  This version will work on any processor, but if there is a better
1124 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1125 *
1126 *     swap least significant two bytes with 16-bit rotate
1127 *     swap upper and lower 16-bits
1128 *     swap most significant two bytes with 16-bit rotate
1129 *
1130 *  Some CPUs have special instructions which swap a 32-bit quantity in
1131 *  a single instruction (e.g. i486).  It is probably best to avoid
1132 *  an "endian swapping control bit" in the CPU.  One good reason is
1133 *  that interrupts would probably have to be disabled to ensure that
1134 *  an interrupt does not try to access the same "chunk" with the wrong
1135 *  endian.  Another good reason is that on some CPUs, the endian bit
1136 *  endianness for ALL fetches -- both code and data -- so the code
1137 *  will be fetched incorrectly.
1138 *
1139 *  AVR Specific Information:
1140 *
1141 *  XXX document implementation including references if appropriate
1142 */
1143
1144static inline uint32_t CPU_swap_u32(
1145  uint32_t value
1146)
1147{
1148  uint32_t   byte1, byte2, byte3, byte4, swapped;
1149
1150  byte4 = (value >> 24) & 0xff;
1151  byte3 = (value >> 16) & 0xff;
1152  byte2 = (value >> 8)  & 0xff;
1153  byte1 =  value        & 0xff;
1154
1155  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1156  return( swapped );
1157}
1158
1159#define CPU_swap_u16( value ) \
1160  (((value&0xff) << 8) | ((value >> 8)&0xff))
1161
1162#endif /* ASM */
1163
1164#ifdef __cplusplus
1165}
1166#endif
1167
1168#endif
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