source: rtems/cpukit/score/cpu/avr/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 34.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the AVR
7 *  processor.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/avr.h>
28#include <avr/common.h>
29
30/* conditional compilation parameters */
31
32#ifndef RTEMS_USE_16_BIT_OBJECT
33#define RTEMS_USE_16_BIT_OBJECT
34#endif
35
36/*
37 *  Should the calls to _Thread_Enable_dispatch be inlined?
38 *
39 *  If TRUE, then they are inlined.
40 *  If FALSE, then a subroutine call is made.
41 *
42 *  Basically this is an example of the classic trade-off of size
43 *  versus speed.  Inlining the call (TRUE) typically increases the
44 *  size of RTEMS while speeding up the enabling of dispatching.
45 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
46 *  only be 0 or 1 unless you are in an interrupt handler and that
47 *  interrupt handler invokes the executive.]  When not inlined
48 *  something calls _Thread_Enable_dispatch which in turns calls
49 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
50 *  one subroutine call is avoided entirely.]
51 *
52 *  AVR Specific Information:
53 *
54 *  XXX document implementation including references if appropriate
55 */
56
57#define CPU_INLINE_ENABLE_DISPATCH       FALSE
58
59/*
60 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
61 *  be unrolled one time?  In unrolled each iteration of the loop examines
62 *  two "nodes" on the chain being searched.  Otherwise, only one node
63 *  is examined per iteration.
64 *
65 *  If TRUE, then the loops are unrolled.
66 *  If FALSE, then the loops are not unrolled.
67 *
68 *  The primary factor in making this decision is the cost of disabling
69 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
70 *  body of the loop.  On some CPUs, the flash is more expensive than
71 *  one iteration of the loop body.  In this case, it might be desirable
72 *  to unroll the loop.  It is important to note that on some CPUs, this
73 *  code is the longest interrupt disable period in RTEMS.  So it is
74 *  necessary to strike a balance when setting this parameter.
75 *
76 *  AVR Specific Information:
77 *
78 *  XXX document implementation including references if appropriate
79 */
80
81#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
82
83/*
84 *  Does RTEMS manage a dedicated interrupt stack in software?
85 *
86 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
87 *  If FALSE, nothing is done.
88 *
89 *  If the CPU supports a dedicated interrupt stack in hardware,
90 *  then it is generally the responsibility of the BSP to allocate it
91 *  and set it up.
92 *
93 *  If the CPU does not support a dedicated interrupt stack, then
94 *  the porter has two options: (1) execute interrupts on the
95 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
96 *  interrupt stack.
97 *
98 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
99 *
100 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
101 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
102 *  possible that both are FALSE for a particular CPU.  Although it
103 *  is unclear what that would imply about the interrupt processing
104 *  procedure on that CPU.
105 *
106 *  AVR Specific Information:
107 *
108 *  XXX document implementation including references if appropriate
109 */
110
111#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
112
113/*
114 *  Does this CPU have hardware support for a dedicated interrupt stack?
115 *
116 *  If TRUE, then it must be installed during initialization.
117 *  If FALSE, then no installation is performed.
118 *
119 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
120 *
121 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
122 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
123 *  possible that both are FALSE for a particular CPU.  Although it
124 *  is unclear what that would imply about the interrupt processing
125 *  procedure on that CPU.
126 *
127 *  AVR Specific Information:
128 *
129 *  XXX document implementation including references if appropriate
130 */
131
132#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
133
134/*
135 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
136 *
137 *  If TRUE, then the memory is allocated during initialization.
138 *  If FALSE, then the memory is allocated during initialization.
139 *
140 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
141 *
142 *  AVR Specific Information:
143 *
144 *  XXX document implementation including references if appropriate
145 */
146
147#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
148
149/*
150 *  Does the RTEMS invoke the user's ISR with the vector number and
151 *  a pointer to the saved interrupt frame (1) or just the vector
152 *  number (0)?
153 *
154 *  AVR Specific Information:
155 *
156 *  XXX document implementation including references if appropriate
157 */
158
159#define CPU_ISR_PASSES_FRAME_POINTER 0
160
161/*
162 *  Does the CPU follow the simple vectored interrupt model?
163 *
164 *  If TRUE, then RTEMS allocates the vector table it internally manages.
165 *  If FALSE, then the BSP is assumed to allocate and manage the vector
166 *  table
167 *
168 *  AVR Specific Information:
169 *
170 *  XXX document implementation including references if appropriate
171 */
172#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
173
174/*
175 *  Does the CPU have hardware floating point?
176 *
177 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
178 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
179 *
180 *  If there is a FP coprocessor such as the i387 or mc68881, then
181 *  the answer is TRUE.
182 *
183 *  The macro name "AVR_HAS_FPU" should be made CPU specific.
184 *  It indicates whether or not this CPU model has FP support.  For
185 *  example, it would be possible to have an i386_nofp CPU model
186 *  which set this to false to indicate that you have an i386 without
187 *  an i387 and wish to leave floating point support out of RTEMS.
188 *
189 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
190 *  is software implemented floating point that must be context
191 *  switched.  The determination of whether or not this applies
192 *  is very tool specific and the state saved/restored is also
193 *  compiler specific.
194 *
195 *  AVR Specific Information:
196 *
197 *  XXX document implementation including references if appropriate
198 */
199
200#if ( AVR_HAS_FPU == 1 )
201#define CPU_HARDWARE_FP     TRUE
202#else
203#define CPU_HARDWARE_FP     FALSE
204#endif
205#define CPU_SOFTWARE_FP     FALSE
206
207/*
208 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
209 *
210 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
211 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
212 *
213 *  So far, the only CPUs in which this option has been used are the
214 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
215 *  gcc both implicitly used the floating point registers to perform
216 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
217 *  seen to allocate floating point local variables and touch the FPU
218 *  even when the flow through a subroutine (like vfprintf()) might
219 *  not use floating point formats.
220 *
221 *  If a function which you would not think utilize the FP unit DOES,
222 *  then one can not easily predict which tasks will use the FP hardware.
223 *  In this case, this option should be TRUE.
224 *
225 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
226 *
227 *  AVR Specific Information:
228 *
229 *  XXX document implementation including references if appropriate
230 */
231
232#define CPU_ALL_TASKS_ARE_FP     TRUE
233
234/*
235 *  Should the IDLE task have a floating point context?
236 *
237 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
238 *  and it has a floating point context which is switched in and out.
239 *  If FALSE, then the IDLE task does not have a floating point context.
240 *
241 *  Setting this to TRUE negatively impacts the time required to preempt
242 *  the IDLE task from an interrupt because the floating point context
243 *  must be saved as part of the preemption.
244 *
245 *  AVR Specific Information:
246 *
247 *  XXX document implementation including references if appropriate
248 */
249
250#define CPU_IDLE_TASK_IS_FP      FALSE
251
252/*
253 *  Should the saving of the floating point registers be deferred
254 *  until a context switch is made to another different floating point
255 *  task?
256 *
257 *  If TRUE, then the floating point context will not be stored until
258 *  necessary.  It will remain in the floating point registers and not
259 *  disturned until another floating point task is switched to.
260 *
261 *  If FALSE, then the floating point context is saved when a floating
262 *  point task is switched out and restored when the next floating point
263 *  task is restored.  The state of the floating point registers between
264 *  those two operations is not specified.
265 *
266 *  If the floating point context does NOT have to be saved as part of
267 *  interrupt dispatching, then it should be safe to set this to TRUE.
268 *
269 *  Setting this flag to TRUE results in using a different algorithm
270 *  for deciding when to save and restore the floating point context.
271 *  The deferred FP switch algorithm minimizes the number of times
272 *  the FP context is saved and restored.  The FP context is not saved
273 *  until a context switch is made to another, different FP task.
274 *  Thus in a system with only one FP task, the FP context will never
275 *  be saved or restored.
276 *
277 *  AVR Specific Information:
278 *
279 *  XXX document implementation including references if appropriate
280 */
281
282#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
283
284/*
285 *  Does this port provide a CPU dependent IDLE task implementation?
286 *
287 *  If TRUE, then the routine _CPU_Thread_Idle_body
288 *  must be provided and is the default IDLE thread body instead of
289 *  _CPU_Thread_Idle_body.
290 *
291 *  If FALSE, then use the generic IDLE thread body if the BSP does
292 *  not provide one.
293 *
294 *  This is intended to allow for supporting processors which have
295 *  a low power or idle mode.  When the IDLE thread is executed, then
296 *  the CPU can be powered down.
297 *
298 *  The order of precedence for selecting the IDLE thread body is:
299 *
300 *    1.  BSP provided
301 *    2.  CPU dependent (if provided)
302 *    3.  generic (if no BSP and no CPU dependent)
303 *
304 *  AVR Specific Information:
305 *
306 *  XXX document implementation including references if appropriate
307 */
308
309#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
310
311/*
312 *  Does the stack grow up (toward higher addresses) or down
313 *  (toward lower addresses)?
314 *
315 *  If TRUE, then the grows upward.
316 *  If FALSE, then the grows toward smaller addresses.
317 *
318 *  AVR Specific Information:
319 *
320 *  XXX document implementation including references if appropriate
321 */
322
323#define CPU_STACK_GROWS_UP               FALSE
324
325/*
326 *  The following is the variable attribute used to force alignment
327 *  of critical RTEMS structures.  On some processors it may make
328 *  sense to have these aligned on tighter boundaries than
329 *  the minimum requirements of the compiler in order to have as
330 *  much of the critical data area as possible in a cache line.
331 *
332 *  The placement of this macro in the declaration of the variables
333 *  is based on the syntactically requirements of the GNU C
334 *  "__attribute__" extension.  For example with GNU C, use
335 *  the following to force a structures to a 32 byte boundary.
336 *
337 *      __attribute__ ((aligned (32)))
338 *
339 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
340 *         To benefit from using this, the data must be heavily
341 *         used so it will stay in the cache and used frequently enough
342 *         in the executive to justify turning this on.
343 *
344 *  AVR Specific Information:
345 *
346 *  XXX document implementation including references if appropriate
347 */
348
349#define CPU_STRUCTURE_ALIGNMENT
350
351/*
352 *  Define what is required to specify how the network to host conversion
353 *  routines are handled.
354 *
355 *  AVR Specific Information:
356 *
357 *  XXX document implementation including references if appropriate
358 */
359
360#define CPU_BIG_ENDIAN                           TRUE
361#define CPU_LITTLE_ENDIAN                        FALSE
362
363/*
364 *  The following defines the number of bits actually used in the
365 *  interrupt field of the task mode.  How those bits map to the
366 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
367 *
368 *  AVR Specific Information:
369 *
370 *  XXX document implementation including references if appropriate
371 */
372
373#define CPU_MODES_INTERRUPT_MASK   0x00000001
374
375/*
376 *  Processor defined structures required for cpukit/score.
377 *
378 *  AVR Specific Information:
379 *
380 *  XXX document implementation including references if appropriate
381 */
382
383/* may need to put some structures here.  */
384
385#ifndef ASM
386
387/*
388 * Contexts
389 *
390 *  Generally there are 2 types of context to save.
391 *     1. Interrupt registers to save
392 *     2. Task level registers to save
393 *
394 *  This means we have the following 3 context items:
395 *     1. task level context stuff::  Context_Control
396 *     2. floating point task stuff:: Context_Control_fp
397 *     3. special interrupt level context :: Context_Control_interrupt
398 *
399 *  On some processors, it is cost-effective to save only the callee
400 *  preserved registers during a task context switch.  This means
401 *  that the ISR code needs to save those registers which do not
402 *  persist across function calls.  It is not mandatory to make this
403 *  distinctions between the caller/callee saves registers for the
404 *  purpose of minimizing context saved during task switch and on interrupts.
405 *  If the cost of saving extra registers is minimal, simplicity is the
406 *  choice.  Save the same context on interrupt entry as for tasks in
407 *  this case.
408 *
409 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
410 *  care should be used in designing the context area.
411 *
412 *  On some CPUs with hardware floating point support, the Context_Control_fp
413 *  structure will not be used or it simply consist of an array of a
414 *  fixed number of bytes.   This is done when the floating point context
415 *  is dumped by a "FP save context" type instruction and the format
416 *  is not really defined by the CPU.  In this case, there is no need
417 *  to figure out the exact format -- only the size.  Of course, although
418 *  this is enough information for RTEMS, it is probably not enough for
419 *  a debugger such as gdb.  But that is another problem.
420 *
421 *  AVR Specific Information:
422 *
423 *  XXX document implementation including references if appropriate
424 */
425
426typedef struct {
427        uint16_t        stack_pointer;
428        uint8_t         status; //SREG
429} Context_Control;
430
431#define _CPU_Context_Get_SP( _context ) \
432  (_context)->stack_pointer
433
434
435
436
437typedef struct {
438    double      some_float_register;
439} Context_Control_fp;
440
441typedef struct {
442    uint32_t   special_interrupt_register;
443} CPU_Interrupt_frame;
444
445/*
446 *  This variable is optional.  It is used on CPUs on which it is difficult
447 *  to generate an "uninitialized" FP context.  It is filled in by
448 *  _CPU_Initialize and copied into the task's FP context area during
449 *  _CPU_Context_Initialize.
450 *
451 *  AVR Specific Information:
452 *
453 *  XXX document implementation including references if appropriate
454 */
455
456SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
457
458#endif /* ASM */
459
460/*
461 *  Nothing prevents the porter from declaring more CPU specific variables.
462 *
463 *  AVR Specific Information:
464 *
465 *  XXX document implementation including references if appropriate
466 */
467
468/* XXX: if needed, put more variables here */
469
470/*
471 *  The size of the floating point context area.  On some CPUs this
472 *  will not be a "sizeof" because the format of the floating point
473 *  area is not defined -- only the size is.  This is usually on
474 *  CPUs with a "floating point save context" instruction.
475 *
476 *  AVR Specific Information:
477 *
478 *  XXX document implementation including references if appropriate
479 */
480
481#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
482
483/*
484 *  Amount of extra stack (above minimum stack size) required by
485 *  MPCI receive server thread.  Remember that in a multiprocessor
486 *  system this thread must exist and be able to process all directives.
487 *
488 *  AVR Specific Information:
489 *
490 *  XXX document implementation including references if appropriate
491 */
492
493#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
494
495/*
496 *  This defines the number of entries in the ISR_Vector_table managed
497 *  by RTEMS.
498 *
499 *  AVR Specific Information:
500 *
501 *  XXX document implementation including references if appropriate
502 */
503
504#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
505#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
506
507/*
508 *  This is defined if the port has a special way to report the ISR nesting
509 *  level.  Most ports maintain the variable _ISR_Nest_level.
510 */
511
512#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
513
514/*
515 *  Should be large enough to run all RTEMS tests.  This ensures
516 *  that a "reasonable" small application should not have any problems.
517 *
518 *  AVR Specific Information:
519 *
520 *  XXX document implementation including references if appropriate
521 */
522
523#define CPU_STACK_MINIMUM_SIZE          512
524
525/*
526 *  Maximum priority of a thread. Note based from 0 which is the idle task.
527 */
528#define CPU_PRIORITY_MAXIMUM             15
529
530/*
531 *  CPU's worst alignment requirement for data types on a byte boundary.  This
532 *  alignment does not take into account the requirements for the stack.
533 *
534 *  AVR Specific Information:
535 *
536 *  XXX document implementation including references if appropriate
537 */
538
539#define CPU_ALIGNMENT              4
540
541/*
542 *  This number corresponds to the byte alignment requirement for the
543 *  heap handler.  This alignment requirement may be stricter than that
544 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
545 *  common for the heap to follow the same alignment requirement as
546 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
547 *  then this should be set to CPU_ALIGNMENT.
548 *
549 *  NOTE:  This does not have to be a power of 2 although it should be
550 *         a multiple of 2 greater than or equal to 2.  The requirement
551 *         to be a multiple of 2 is because the heap uses the least
552 *         significant field of the front and back flags to indicate
553 *         that a block is in use or free.  So you do not want any odd
554 *         length blocks really putting length data in that bit.
555 *
556 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
557 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
558 *         elements allocated from the heap meet all restrictions.
559 *
560 *  AVR Specific Information:
561 *
562 *  XXX document implementation including references if appropriate
563 */
564
565#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
566
567/*
568 *  This number corresponds to the byte alignment requirement for memory
569 *  buffers allocated by the partition manager.  This alignment requirement
570 *  may be stricter than that for the data types alignment specified by
571 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
572 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
573 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
574 *
575 *  NOTE:  This does not have to be a power of 2.  It does have to
576 *         be greater or equal to than CPU_ALIGNMENT.
577 *
578 *  AVR Specific Information:
579 *
580 *  XXX document implementation including references if appropriate
581 */
582
583#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
584
585/*
586 *  This number corresponds to the byte alignment requirement for the
587 *  stack.  This alignment requirement may be stricter than that for the
588 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
589 *  is strict enough for the stack, then this should be set to 0.
590 *
591 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
592 *
593 *  AVR Specific Information:
594 *
595 *  XXX document implementation including references if appropriate
596 */
597
598#define CPU_STACK_ALIGNMENT        0
599
600/*
601 *  ISR handler macros
602 */
603
604/*
605 *  Support routine to initialize the RTEMS vector table after it is allocated.
606 *
607 *  AVR Specific Information:
608 *
609 *  XXX document implementation including references if appropriate
610 */
611
612#define _CPU_Initialize_vectors()
613
614/*
615 *  Disable all interrupts for an RTEMS critical section.  The previous
616 *  level is returned in _level.
617 *
618 *  AVR Specific Information:
619 *
620 *  XXX document implementation including references if appropriate
621 */
622
623#define _CPU_ISR_Disable( _isr_cookie ) \
624  do { \
625        (_isr_cookie) = SREG; \
626        asm volatile ("cli"::); \
627  } while (0)
628
629/*
630 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
631 *  This indicates the end of an RTEMS critical section.  The parameter
632 *  _level is not modified.
633 *
634 *  AVR Specific Information:
635 *
636 *  XXX document implementation including references if appropriate
637 */
638
639#define _CPU_ISR_Enable( _isr_cookie )  \
640  do { \
641        SREG  = _isr_cookie; \
642        asm volatile ("sei"::); \
643  } while (0)
644
645/*
646 *  This temporarily restores the interrupt to _level before immediately
647 *  disabling them again.  This is used to divide long RTEMS critical
648 *  sections into two or more parts.  The parameter _level is not
649 * modified.
650 *
651 *  AVR Specific Information:
652 *
653 *  XXX document implementation including references if appropriate
654 */
655
656#define _CPU_ISR_Flash( _isr_cookie ) \
657  do { \
658        SREG=(_isr_cookie); \
659        asm volatile("sei"::); \
660        (_isr_cookie) = SREG; \
661        asm volatile("cli"::); \
662  } while (0)
663
664/*
665 *  Map interrupt level in task mode onto the hardware that the CPU
666 *  actually provides.  Currently, interrupt levels which do not
667 *  map onto the CPU in a generic fashion are undefined.  Someday,
668 *  it would be nice if these were "mapped" by the application
669 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
670 *  8 - 255 would be available for bsp/application specific meaning.
671 *  This could be used to manage a programmable interrupt controller
672 *  via the rtems_task_mode directive.
673 *
674 *  The get routine usually must be implemented as a subroutine.
675 *
676 *  AVR Specific Information:
677 *
678 *  XXX document implementation including references if appropriate
679 */
680
681#define _CPU_ISR_Set_level( new_level ) \
682  { \
683  }
684
685#ifndef ASM
686
687uint32_t   _CPU_ISR_Get_level( void );
688
689/* end of ISR handler macros */
690
691/* Context handler macros */
692
693/*
694 *  Initialize the context to a state suitable for starting a
695 *  task after a context restore operation.  Generally, this
696 *  involves:
697 *
698 *     - setting a starting address
699 *     - preparing the stack
700 *     - preparing the stack and frame pointers
701 *     - setting the proper interrupt level in the context
702 *     - initializing the floating point context
703 *
704 *  This routine generally does not set any unnecessary register
705 *  in the context.  The state of the "general data" registers is
706 *  undefined at task start time.
707 *
708 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
709 *        point thread.  This is typically only used on CPUs where the
710 *        FPU may be easily disabled by software such as on the SPARC
711 *        where the PSR contains an enable FPU bit.
712 *
713 *  AVR Specific Information:
714 *
715 *  XXX document implementation including references if appropriate
716 */
717/*
718#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
719                                 _isr, _entry_point, _is_fp ) \
720  \
721        do { \
722        uint16_t *_stack;\
723        _stack  = (uint16_t) (_stack_base) + (uint16_t)(_size);\
724        (_the_context)->stack_pointer = _stack-1;       \
725        *(_stack) = *(_entry_point);    \
726        printk("the ret address is %x\n", *(uint16_t *)(_stack));\
727        printk("sp = 0x%x\nep = 0x%x\n",_stack, *(_entry_point)); \
728        printk("stack base = 0x%x\n size = 0x%x\n",_stack_base, _size);\
729        printk("struct starting address = 0x%x\n", _the_context);\
730        printk("struct stack pointer address = 0x%x\n",(_the_context)->stack_pointer);\
731        } while ( 0 )
732
733*/
734/*
735 *  This routine is responsible for somehow restarting the currently
736 *  executing task.  If you are lucky, then all that is necessary
737 *  is restoring the context.  Otherwise, there will need to be
738 *  a special assembly routine which does something special in this
739 *  case.  Context_Restore should work most of the time.  It will
740 *  not work if restarting self conflicts with the stack frame
741 *  assumptions of restoring a context.
742 *
743 *  AVR Specific Information:
744 *
745 *  XXX document implementation including references if appropriate
746 */
747
748#define _CPU_Context_Restart_self( _the_context ) \
749   _CPU_Context_restore( _the_context );
750
751/*
752 *  The purpose of this macro is to allow the initial pointer into
753 *  a floating point context area (used to save the floating point
754 *  context) to be at an arbitrary place in the floating point
755 *  context area.
756 *
757 *  This is necessary because some FP units are designed to have
758 *  their context saved as a stack which grows into lower addresses.
759 *  Other FP units can be saved by simply moving registers into offsets
760 *  from the base of the context area.  Finally some FP units provide
761 *  a "dump context" instruction which could fill in from high to low
762 *  or low to high based on the whim of the CPU designers.
763 *
764 *  AVR Specific Information:
765 *
766 *  XXX document implementation including references if appropriate
767 */
768
769#define _CPU_Context_Fp_start( _base, _offset ) \
770   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
771
772/*
773 *  This routine initializes the FP context area passed to it to.
774 *  There are a few standard ways in which to initialize the
775 *  floating point context.  The code included for this macro assumes
776 *  that this is a CPU in which a "initial" FP context was saved into
777 *  _CPU_Null_fp_context and it simply copies it to the destination
778 *  context passed to it.
779 *
780 *  Other models include (1) not doing anything, and (2) putting
781 *  a "null FP status word" in the correct place in the FP context.
782 *
783 *  AVR Specific Information:
784 *
785 *  XXX document implementation including references if appropriate
786 */
787
788#define _CPU_Context_Initialize_fp( _destination ) \
789  { \
790   *(*(_destination)) = _CPU_Null_fp_context; \
791  }
792
793/* end of Context handler macros */
794
795/* Fatal Error manager macros */
796
797/*
798 *  This routine copies _error into a known place -- typically a stack
799 *  location or a register, optionally disables interrupts, and
800 *  halts/stops the CPU.
801 *
802 *  AVR Specific Information:
803 *
804 *  XXX document implementation including references if appropriate
805 */
806
807#define _CPU_Fatal_halt( _error ) \
808  { \
809  }
810
811/* end of Fatal Error manager macros */
812
813/* Bitfield handler macros */
814
815/*
816 *  This routine sets _output to the bit number of the first bit
817 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Control.
818 *  This type may be either 16 or 32 bits wide although only the 16
819 *  least significant bits will be used.
820 *
821 *  There are a number of variables in using a "find first bit" type
822 *  instruction.
823 *
824 *    (1) What happens when run on a value of zero?
825 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
826 *    (3) The numbering may be zero or one based.
827 *    (4) The "find first bit" instruction may search from MSB or LSB.
828 *
829 *  RTEMS guarantees that (1) will never happen so it is not a concern.
830 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
831 *  _CPU_Priority_bits_index().  These three form a set of routines
832 *  which must logically operate together.  Bits in the _value are
833 *  set and cleared based on masks built by _CPU_Priority_mask().
834 *  The basic major and minor values calculated by _Priority_Major()
835 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
836 *  to properly range between the values returned by the "find first bit"
837 *  instruction.  This makes it possible for _Priority_Get_highest() to
838 *  calculate the major and directly index into the minor table.
839 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
840 *  is the first bit found.
841 *
842 *  This entire "find first bit" and mapping process depends heavily
843 *  on the manner in which a priority is broken into a major and minor
844 *  components with the major being the 4 MSB of a priority and minor
845 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
846 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
847 *  to the lowest priority.
848 *
849 *  If your CPU does not have a "find first bit" instruction, then
850 *  there are ways to make do without it.  Here are a handful of ways
851 *  to implement this in software:
852 *
853 *    - a series of 16 bit test instructions
854 *    - a "binary search using if's"
855 *    - _number = 0
856 *      if _value > 0x00ff
857 *        _value >>=8
858 *        _number = 8;
859 *
860 *      if _value > 0x0000f
861 *        _value >=8
862 *        _number += 4
863 *
864 *      _number += bit_set_table[ _value ]
865 *
866 *    where bit_set_table[ 16 ] has values which indicate the first
867 *      bit set
868 *
869 *  AVR Specific Information:
870 *
871 *  XXX document implementation including references if appropriate
872 */
873
874#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
875#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
876
877#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
878
879#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
880  { \
881    (_output) = 0;   /* do something to prevent warnings */ \
882  }
883
884#endif
885
886/* end of Bitfield handler macros */
887
888/*
889 *  This routine builds the mask which corresponds to the bit fields
890 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
891 *  for that routine.
892 *
893 *  AVR Specific Information:
894 *
895 *  XXX document implementation including references if appropriate
896 */
897
898#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
899
900#define _CPU_Priority_Mask( _bit_number ) \
901  ( 1 << (_bit_number) )
902
903#endif
904
905/*
906 *  This routine translates the bit numbers returned by
907 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
908 *  a major or minor component of a priority.  See the discussion
909 *  for that routine.
910 *
911 *  AVR Specific Information:
912 *
913 *  XXX document implementation including references if appropriate
914 */
915
916#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
917
918#define _CPU_Priority_bits_index( _priority ) \
919  (_priority)
920
921#endif
922
923/* end of Priority handler macros */
924
925/* functions */
926
927/*context_initialize asm function*/
928
929void context_initialize(unsigned short* context,
930                unsigned short stack_add,
931                unsigned short entry_point);
932
933/*PAGE
934 *
935 *  _CPU_Context_Initialize
936 *
937 *  This kernel routine initializes the basic non-FP context area associated
938 *  with each thread.
939 *
940 *  Input parameters:
941 *    the_context  - pointer to the context area
942 *    stack_base   - address of memory for the SPARC
943 *    size         - size in bytes of the stack area
944 *    new_level    - interrupt level for this context area
945 *    entry_point  - the starting execution point for this this context
946 *    is_fp        - TRUE if this context is associated with an FP thread
947 *
948 *  Output parameters: NONE
949 */
950
951void _CPU_Context_Initialize(
952  Context_Control  *the_context,
953  uint32_t         *stack_base,
954  uint32_t          size,
955  uint32_t          new_level,
956  void             *entry_point,
957  bool              is_fp
958);
959
960/*
961*
962*  _CPU_Push
963*
964*  this routine pushes 2 bytes onto the stack
965*
966*
967*
968*
969*
970*
971*
972*/
973
974void _CPU_Push(uint16_t _SP_, uint16_t entry_point);
975
976
977
978
979/*
980 *  _CPU_Initialize
981 *
982 *  This routine performs CPU dependent initialization.
983 *
984 *  AVR Specific Information:
985 *
986 *  XXX document implementation including references if appropriate
987 */
988
989void _CPU_Initialize(void);
990
991/*
992 *  _CPU_ISR_install_raw_handler
993 *
994 *  This routine installs a "raw" interrupt handler directly into the
995 *  processor's vector table.
996 *
997 *  AVR Specific Information:
998 *
999 *  XXX document implementation including references if appropriate
1000 */
1001
1002void _CPU_ISR_install_raw_handler(
1003  uint32_t    vector,
1004  proc_ptr    new_handler,
1005  proc_ptr   *old_handler
1006);
1007
1008/*
1009 *  _CPU_ISR_install_vector
1010 *
1011 *  This routine installs an interrupt vector.
1012 *
1013 *  AVR Specific Information:
1014 *
1015 *  XXX document implementation including references if appropriate
1016 */
1017
1018void _CPU_ISR_install_vector(
1019  uint32_t    vector,
1020  proc_ptr    new_handler,
1021  proc_ptr   *old_handler
1022);
1023
1024/*
1025 *  _CPU_Install_interrupt_stack
1026 *
1027 *  This routine installs the hardware interrupt stack pointer.
1028 *
1029 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1030 *         is TRUE.
1031 *
1032 *  AVR Specific Information:
1033 *
1034 *  XXX document implementation including references if appropriate
1035 */
1036
1037void _CPU_Install_interrupt_stack( void );
1038
1039/*
1040 *  _CPU_Thread_Idle_body
1041 *
1042 *  This routine is the CPU dependent IDLE thread body.
1043 *
1044 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1045 *         is TRUE.
1046 *
1047 *  AVR Specific Information:
1048 *
1049 *  XXX document implementation including references if appropriate
1050 */
1051
1052void *_CPU_Thread_Idle_body( uintptr_t ignored );
1053
1054/*
1055 *  _CPU_Context_switch
1056 *
1057 *  This routine switches from the run context to the heir context.
1058 *
1059 *  AVR Specific Information:
1060 *
1061 *  XXX document implementation including references if appropriate
1062 */
1063
1064void _CPU_Context_switch(
1065  Context_Control  *run,
1066  Context_Control  *heir
1067);
1068
1069/*
1070 *  _CPU_Context_restore
1071 *
1072 *  This routine is generally used only to restart self in an
1073 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1074 *
1075 *  NOTE: May be unnecessary to reload some registers.
1076 *
1077 *  AVR Specific Information:
1078 *
1079 *  XXX document implementation including references if appropriate
1080 */
1081
1082void _CPU_Context_restore(
1083  Context_Control *new_context
1084);
1085
1086/*
1087 *  _CPU_Context_save_fp
1088 *
1089 *  This routine saves the floating point context passed to it.
1090 *
1091 *  AVR Specific Information:
1092 *
1093 *  XXX document implementation including references if appropriate
1094 */
1095
1096void _CPU_Context_save_fp(
1097  Context_Control_fp **fp_context_ptr
1098);
1099
1100/*
1101 *  _CPU_Context_restore_fp
1102 *
1103 *  This routine restores the floating point context passed to it.
1104 *
1105 *  AVR Specific Information:
1106 *
1107 *  XXX document implementation including references if appropriate
1108 */
1109
1110void _CPU_Context_restore_fp(
1111  Context_Control_fp **fp_context_ptr
1112);
1113
1114/*  The following routine swaps the endian format of an unsigned int.
1115 *  It must be static because it is referenced indirectly.
1116 *
1117 *  This version will work on any processor, but if there is a better
1118 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1119 *
1120 *     swap least significant two bytes with 16-bit rotate
1121 *     swap upper and lower 16-bits
1122 *     swap most significant two bytes with 16-bit rotate
1123 *
1124 *  Some CPUs have special instructions which swap a 32-bit quantity in
1125 *  a single instruction (e.g. i486).  It is probably best to avoid
1126 *  an "endian swapping control bit" in the CPU.  One good reason is
1127 *  that interrupts would probably have to be disabled to ensure that
1128 *  an interrupt does not try to access the same "chunk" with the wrong
1129 *  endian.  Another good reason is that on some CPUs, the endian bit
1130 *  endianness for ALL fetches -- both code and data -- so the code
1131 *  will be fetched incorrectly.
1132 *
1133 *  AVR Specific Information:
1134 *
1135 *  XXX document implementation including references if appropriate
1136 */
1137
1138static inline uint32_t CPU_swap_u32(
1139  uint32_t value
1140)
1141{
1142  uint32_t   byte1, byte2, byte3, byte4, swapped;
1143
1144  byte4 = (value >> 24) & 0xff;
1145  byte3 = (value >> 16) & 0xff;
1146  byte2 = (value >> 8)  & 0xff;
1147  byte1 =  value        & 0xff;
1148
1149  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1150  return( swapped );
1151}
1152
1153#define CPU_swap_u16( value ) \
1154  (((value&0xff) << 8) | ((value >> 8)&0xff))
1155
1156#endif /* ASM */
1157
1158#ifdef __cplusplus
1159}
1160#endif
1161
1162#endif
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