1 | /* |
---|
2 | * XXX CPU Dependent Source |
---|
3 | * |
---|
4 | * |
---|
5 | * COPYRIGHT (c) 1989-1999. |
---|
6 | * On-Line Applications Research Corporation (OAR). |
---|
7 | * |
---|
8 | * The license and distribution terms for this file may be |
---|
9 | * found in the file LICENSE in this distribution or at |
---|
10 | * http://www.rtems.com/license/LICENSE. |
---|
11 | * |
---|
12 | * $Id$ |
---|
13 | */ |
---|
14 | |
---|
15 | #include <rtems/system.h> |
---|
16 | #include <rtems/score/isr.h> |
---|
17 | #include <rtems/score/wkspace.h> |
---|
18 | |
---|
19 | /* _CPU_Initialize |
---|
20 | * |
---|
21 | * This routine performs processor dependent initialization. |
---|
22 | * |
---|
23 | * INPUT PARAMETERS: |
---|
24 | * thread_dispatch - address of disptaching routine |
---|
25 | * |
---|
26 | * NO_CPU Specific Information: |
---|
27 | * |
---|
28 | * XXX document implementation including references if appropriate |
---|
29 | */ |
---|
30 | |
---|
31 | |
---|
32 | void _CPU_Initialize( |
---|
33 | void (*thread_dispatch) /* ignored on this CPU */ |
---|
34 | ) |
---|
35 | { |
---|
36 | /* |
---|
37 | * The thread_dispatch argument is the address of the entry point |
---|
38 | * for the routine called at the end of an ISR once it has been |
---|
39 | * decided a context switch is necessary. On some compilation |
---|
40 | * systems it is difficult to call a high-level language routine |
---|
41 | * from assembly. This allows us to trick these systems. |
---|
42 | * |
---|
43 | * If you encounter this problem save the entry point in a CPU |
---|
44 | * dependent variable. |
---|
45 | */ |
---|
46 | |
---|
47 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
---|
48 | |
---|
49 | /* |
---|
50 | * If there is not an easy way to initialize the FP context |
---|
51 | * during Context_Initialize, then it is usually easier to |
---|
52 | * save an "uninitialized" FP context here and copy it to |
---|
53 | * the task's during Context_Initialize. |
---|
54 | */ |
---|
55 | |
---|
56 | /* FP context initialization support goes here */ |
---|
57 | } |
---|
58 | |
---|
59 | /*PAGE |
---|
60 | * |
---|
61 | * _CPU_ISR_Get_level |
---|
62 | * |
---|
63 | * NO_CPU Specific Information: |
---|
64 | * |
---|
65 | * XXX document implementation including references if appropriate |
---|
66 | */ |
---|
67 | |
---|
68 | uint32_t _CPU_ISR_Get_level( void ) |
---|
69 | { |
---|
70 | /* |
---|
71 | * This routine returns the current interrupt level. |
---|
72 | */ |
---|
73 | |
---|
74 | return 0; |
---|
75 | } |
---|
76 | |
---|
77 | /*PAGE |
---|
78 | * |
---|
79 | * _CPU_ISR_install_raw_handler |
---|
80 | * |
---|
81 | * NO_CPU Specific Information: |
---|
82 | * |
---|
83 | * XXX document implementation including references if appropriate |
---|
84 | */ |
---|
85 | |
---|
86 | void _CPU_ISR_install_raw_handler( |
---|
87 | uint32_t vector, |
---|
88 | proc_ptr new_handler, |
---|
89 | proc_ptr *old_handler |
---|
90 | ) |
---|
91 | { |
---|
92 | /* |
---|
93 | * This is where we install the interrupt handler into the "raw" interrupt |
---|
94 | * table used by the CPU to dispatch interrupt handlers. |
---|
95 | */ |
---|
96 | } |
---|
97 | |
---|
98 | /*PAGE |
---|
99 | * |
---|
100 | * _CPU_ISR_install_vector |
---|
101 | * |
---|
102 | * This kernel routine installs the RTEMS handler for the |
---|
103 | * specified vector. |
---|
104 | * |
---|
105 | * Input parameters: |
---|
106 | * vector - interrupt vector number |
---|
107 | * old_handler - former ISR for this vector number |
---|
108 | * new_handler - replacement ISR for this vector number |
---|
109 | * |
---|
110 | * Output parameters: NONE |
---|
111 | * |
---|
112 | * |
---|
113 | * NO_CPU Specific Information: |
---|
114 | * |
---|
115 | * XXX document implementation including references if appropriate |
---|
116 | */ |
---|
117 | |
---|
118 | void _CPU_ISR_install_vector( |
---|
119 | uint32_t vector, |
---|
120 | proc_ptr new_handler, |
---|
121 | proc_ptr *old_handler |
---|
122 | ) |
---|
123 | { |
---|
124 | *old_handler = _ISR_Vector_table[ vector ]; |
---|
125 | |
---|
126 | /* |
---|
127 | * If the interrupt vector table is a table of pointer to isr entry |
---|
128 | * points, then we need to install the appropriate RTEMS interrupt |
---|
129 | * handler for this vector number. |
---|
130 | */ |
---|
131 | |
---|
132 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
---|
133 | |
---|
134 | /* |
---|
135 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
---|
136 | * be used by the _ISR_Handler so the user gets control. |
---|
137 | */ |
---|
138 | |
---|
139 | _ISR_Vector_table[ vector ] = new_handler; |
---|
140 | } |
---|
141 | |
---|
142 | /*PAGE |
---|
143 | * |
---|
144 | * _CPU_Install_interrupt_stack |
---|
145 | * |
---|
146 | * NO_CPU Specific Information: |
---|
147 | * |
---|
148 | * XXX document implementation including references if appropriate |
---|
149 | */ |
---|
150 | |
---|
151 | void _CPU_Install_interrupt_stack( void ) |
---|
152 | { |
---|
153 | } |
---|
154 | |
---|
155 | /*PAGE |
---|
156 | * |
---|
157 | * _CPU_Thread_Idle_body |
---|
158 | * |
---|
159 | * NOTES: |
---|
160 | * |
---|
161 | * 1. This is the same as the regular CPU independent algorithm. |
---|
162 | * |
---|
163 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
---|
164 | * instruction, then don't forget to put it in an infinite loop. |
---|
165 | * |
---|
166 | * 3. Be warned. Some processors with onboard DMA have been known |
---|
167 | * to stop the DMA if the CPU were put in IDLE mode. This might |
---|
168 | * also be a problem with other on-chip peripherals. So use this |
---|
169 | * hook with caution. |
---|
170 | * |
---|
171 | * NO_CPU Specific Information: |
---|
172 | * |
---|
173 | * XXX document implementation including references if appropriate |
---|
174 | */ |
---|
175 | |
---|
176 | void *_CPU_Thread_Idle_body( uint32_t ignored ) |
---|
177 | { |
---|
178 | |
---|
179 | for( ; ; ) |
---|
180 | /* insert your "halt" instruction here */ ; |
---|
181 | } |
---|