1 | /* |
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2 | * AVR CPU Dependent Source |
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3 | * |
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4 | * |
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5 | * COPYRIGHT (c) 1989-2008. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | #include <rtems/system.h> |
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16 | #include <rtems/score/isr.h> |
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17 | #include <rtems/score/wkspace.h> |
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18 | |
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19 | #include <rtems/bspIo.h> /* XXX remove me later */ |
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20 | |
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21 | /* _CPU_Initialize |
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22 | * |
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23 | * This routine performs processor dependent initialization. |
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24 | * |
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25 | * INPUT PARAMETERS: NONE |
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26 | * |
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27 | * NO_CPU Specific Information: |
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28 | * |
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29 | * XXX document implementation including references if appropriate |
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30 | */ |
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31 | void _CPU_Initialize(void) |
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32 | { |
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33 | printk( "AVR CPU Initialize\n" ); |
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34 | |
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35 | /* |
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36 | * If there is not an easy way to initialize the FP context |
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37 | * during Context_Initialize, then it is usually easier to |
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38 | * save an "uninitialized" FP context here and copy it to |
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39 | * the task's during Context_Initialize. |
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40 | */ |
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41 | |
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42 | /* FP context initialization support goes here */ |
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43 | } |
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44 | |
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45 | /*PAGE |
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46 | * |
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47 | * _CPU_Context_Initialize |
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48 | * |
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49 | * This kernel routine initializes the basic non-FP context area associated |
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50 | * with each thread. |
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51 | * |
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52 | * Input parameters: |
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53 | * the_context - pointer to the context area |
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54 | * stack_base - address of memory for the SPARC |
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55 | * size - size in bytes of the stack area |
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56 | * new_level - interrupt level for this context area |
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57 | * entry_point - the starting execution point for this this context |
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58 | * is_fp - TRUE if this context is associated with an FP thread |
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59 | * |
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60 | * Output parameters: NONE |
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61 | */ |
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62 | |
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63 | void _CPU_Context_Initialize( |
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64 | Context_Control *the_context, |
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65 | uint32_t *stack_base, |
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66 | uint32_t size, |
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67 | uint32_t new_level, |
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68 | void *entry_point, |
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69 | bool is_fp |
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70 | ) |
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71 | { |
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72 | uint16_t stack; |
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73 | uint16_t start; |
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74 | uint8_t *tmp_sp; |
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75 | uint8_t start_low; |
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76 | uint8_t start_high; |
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77 | |
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78 | /* calc stack high end */ |
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79 | stack = (uint16_t) (stack_base) + (uint16_t) (size); |
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80 | /* calc stack pointer initial value */ |
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81 | the_context->stack_pointer = (stack - 18); |
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82 | /* put the entry point on the stack */ |
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83 | start = (uint16_t) entry_point; |
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84 | start_low = start & 0xff; |
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85 | start_high = start >> 8; |
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86 | tmp_sp = (uint8_t *) (stack+1); |
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87 | tmp_sp[0] = start_high; |
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88 | tmp_sp[1] = start_low; |
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89 | |
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90 | if (new_level) the_context->status = 0x00; //interrupts are enabled |
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91 | else the_context->status = 0x80; //interrupts are disabled |
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92 | |
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93 | /* |
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94 | * JOEL: Why if I comment out these three lines does ticker not run? |
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95 | */ |
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96 | #if 1 |
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97 | printk( "tmp_sp=0x%04x ", ((uint16_t)tmp_sp) ); |
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98 | printk("the_context = 0x%x\n", the_context); |
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99 | printk("entry = 0x%x\n", entry_point); |
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100 | #endif |
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101 | #if 0 |
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102 | printk("sp = 0x%x\n\n",stack); |
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103 | |
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104 | { int i; uint8_t *p; |
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105 | p = (uint8_t *)(stack - 18); |
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106 | for( i=0 ; i<=20 ; i+=8 ) { |
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107 | printk( "0x%04x ", ((uint16_t)&p[i]) ); |
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108 | printk( |
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109 | "0x%02x 0x%02x 0x%02x 0x%02x ", |
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110 | p[i + 0], p[i + 1], p[i + 2], p[i + 3] |
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111 | ); |
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112 | printk( |
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113 | "0x%02x 0x%02x 0x%02x 0x%02x\n", |
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114 | p[i + 4], p[i + 5], p[i + 6], p[i + 7] |
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115 | ); |
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116 | } |
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117 | } |
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118 | #endif |
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119 | } |
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120 | |
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121 | /*PAGE |
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122 | * |
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123 | * _CPU_ISR_Get_level |
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124 | * |
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125 | * NO_CPU Specific Information: |
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126 | * |
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127 | * XXX document implementation including references if appropriate |
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128 | */ |
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129 | |
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130 | uint32_t _CPU_ISR_Get_level( void ) |
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131 | { |
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132 | /* |
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133 | * This routine returns the current interrupt level. |
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134 | */ |
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135 | |
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136 | return 0; |
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137 | } |
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138 | |
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139 | /*PAGE |
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140 | * |
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141 | * _CPU_ISR_install_raw_handler |
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142 | * |
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143 | * NO_CPU Specific Information: |
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144 | * |
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145 | * XXX document implementation including references if appropriate |
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146 | */ |
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147 | |
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148 | void _CPU_ISR_install_raw_handler( |
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149 | uint32_t vector, |
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150 | proc_ptr new_handler, |
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151 | proc_ptr *old_handler |
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152 | ) |
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153 | { |
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154 | /* |
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155 | * This is where we install the interrupt handler into the "raw" interrupt |
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156 | * table used by the CPU to dispatch interrupt handlers. |
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157 | */ |
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158 | } |
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159 | |
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160 | /*PAGE |
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161 | * |
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162 | * _CPU_ISR_install_vector |
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163 | * |
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164 | * This kernel routine installs the RTEMS handler for the |
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165 | * specified vector. |
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166 | * |
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167 | * Input parameters: |
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168 | * vector - interrupt vector number |
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169 | * old_handler - former ISR for this vector number |
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170 | * new_handler - replacement ISR for this vector number |
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171 | * |
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172 | * Output parameters: NONE |
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173 | * |
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174 | * |
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175 | * NO_CPU Specific Information: |
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176 | * |
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177 | * XXX document implementation including references if appropriate |
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178 | */ |
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179 | |
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180 | void _CPU_ISR_install_vector( |
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181 | uint32_t vector, |
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182 | proc_ptr new_handler, |
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183 | proc_ptr *old_handler |
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184 | ) |
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185 | { |
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186 | *old_handler = _ISR_Vector_table[ vector ]; |
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187 | |
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188 | /* |
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189 | * If the interrupt vector table is a table of pointer to isr entry |
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190 | * points, then we need to install the appropriate RTEMS interrupt |
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191 | * handler for this vector number. |
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192 | */ |
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193 | |
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194 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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195 | |
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196 | /* |
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197 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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198 | * be used by the _ISR_Handler so the user gets control. |
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199 | */ |
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200 | |
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201 | _ISR_Vector_table[ vector ] = new_handler; |
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202 | } |
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203 | |
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204 | /*PAGE |
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205 | * |
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206 | * _CPU_Install_interrupt_stack |
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207 | * |
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208 | * NO_CPU Specific Information: |
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209 | * |
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210 | * XXX document implementation including references if appropriate |
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211 | */ |
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212 | |
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213 | void _CPU_Install_interrupt_stack( void ) |
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214 | { |
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215 | } |
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216 | |
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217 | /*PAGE |
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218 | * |
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219 | * _CPU_Thread_Idle_body |
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220 | * |
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221 | * NOTES: |
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222 | * |
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223 | * 1. This is the same as the regular CPU independent algorithm. |
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224 | * |
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225 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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226 | * instruction, then don't forget to put it in an infinite loop. |
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227 | * |
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228 | * 3. Be warned. Some processors with onboard DMA have been known |
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229 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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230 | * also be a problem with other on-chip peripherals. So use this |
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231 | * hook with caution. |
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232 | * |
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233 | * NO_CPU Specific Information: |
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234 | * |
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235 | * XXX document implementation including references if appropriate |
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236 | */ |
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237 | |
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238 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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239 | { |
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240 | |
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241 | for( ; ; ) asm volatile ("sleep"::); |
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242 | /* insert your "halt" instruction here */ ; |
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243 | return (void *) 0; |
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244 | } |
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