[be4a4d2] | 1 | /* |
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| 2 | * XXX CPU Dependent Source |
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| 3 | * |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1989-1999. |
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| 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * |
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| 8 | * The license and distribution terms for this file may be |
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| 9 | * found in the file LICENSE in this distribution or at |
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| 10 | * http://www.rtems.com/license/LICENSE. |
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| 11 | * |
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| 12 | * $Id$ |
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| 13 | */ |
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| 14 | |
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| 15 | #include <rtems/system.h> |
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| 16 | #include <rtems/score/isr.h> |
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| 17 | #include <rtems/score/wkspace.h> |
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| 18 | |
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| 19 | /* _CPU_Initialize |
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| 20 | * |
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| 21 | * This routine performs processor dependent initialization. |
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| 22 | * |
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| 23 | * INPUT PARAMETERS: |
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| 24 | * thread_dispatch - address of disptaching routine |
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| 25 | * |
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| 26 | * NO_CPU Specific Information: |
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| 27 | * |
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| 28 | * XXX document implementation including references if appropriate |
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| 29 | */ |
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| 30 | |
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| 31 | |
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| 32 | void _CPU_Initialize( |
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| 33 | void (*thread_dispatch) /* ignored on this CPU */ |
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| 34 | ) |
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| 35 | { |
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| 36 | /* |
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| 37 | * The thread_dispatch argument is the address of the entry point |
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| 38 | * for the routine called at the end of an ISR once it has been |
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| 39 | * decided a context switch is necessary. On some compilation |
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| 40 | * systems it is difficult to call a high-level language routine |
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| 41 | * from assembly. This allows us to trick these systems. |
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| 42 | * |
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| 43 | * If you encounter this problem save the entry point in a CPU |
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| 44 | * dependent variable. |
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| 45 | */ |
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| 46 | |
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| 47 | _CPU_Thread_dispatch_pointer = thread_dispatch; |
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| 48 | |
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| 49 | /* |
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| 50 | * If there is not an easy way to initialize the FP context |
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| 51 | * during Context_Initialize, then it is usually easier to |
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| 52 | * save an "uninitialized" FP context here and copy it to |
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| 53 | * the task's during Context_Initialize. |
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| 54 | */ |
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| 55 | |
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| 56 | /* FP context initialization support goes here */ |
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| 57 | } |
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| 58 | |
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| 59 | /*PAGE |
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| 60 | * |
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| 61 | * _CPU_ISR_Get_level |
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| 62 | * |
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| 63 | * NO_CPU Specific Information: |
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| 64 | * |
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| 65 | * XXX document implementation including references if appropriate |
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| 66 | */ |
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| 67 | |
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| 68 | uint32_t _CPU_ISR_Get_level( void ) |
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| 69 | { |
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| 70 | /* |
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| 71 | * This routine returns the current interrupt level. |
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| 72 | */ |
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| 73 | |
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| 74 | return 0; |
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| 75 | } |
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| 76 | |
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| 77 | /*PAGE |
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| 78 | * |
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| 79 | * _CPU_ISR_install_raw_handler |
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| 80 | * |
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| 81 | * NO_CPU Specific Information: |
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| 82 | * |
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| 83 | * XXX document implementation including references if appropriate |
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| 84 | */ |
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| 85 | |
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| 86 | void _CPU_ISR_install_raw_handler( |
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| 87 | uint32_t vector, |
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| 88 | proc_ptr new_handler, |
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| 89 | proc_ptr *old_handler |
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| 90 | ) |
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| 91 | { |
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| 92 | /* |
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| 93 | * This is where we install the interrupt handler into the "raw" interrupt |
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| 94 | * table used by the CPU to dispatch interrupt handlers. |
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| 95 | */ |
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| 96 | } |
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| 97 | |
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| 98 | /*PAGE |
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| 99 | * |
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| 100 | * _CPU_ISR_install_vector |
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| 101 | * |
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| 102 | * This kernel routine installs the RTEMS handler for the |
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| 103 | * specified vector. |
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| 104 | * |
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| 105 | * Input parameters: |
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| 106 | * vector - interrupt vector number |
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| 107 | * old_handler - former ISR for this vector number |
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| 108 | * new_handler - replacement ISR for this vector number |
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| 109 | * |
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| 110 | * Output parameters: NONE |
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| 111 | * |
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| 112 | * |
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| 113 | * NO_CPU Specific Information: |
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| 114 | * |
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| 115 | * XXX document implementation including references if appropriate |
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| 116 | */ |
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| 117 | |
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| 118 | void _CPU_ISR_install_vector( |
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| 119 | uint32_t vector, |
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| 120 | proc_ptr new_handler, |
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| 121 | proc_ptr *old_handler |
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| 122 | ) |
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| 123 | { |
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| 124 | *old_handler = _ISR_Vector_table[ vector ]; |
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| 125 | |
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| 126 | /* |
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| 127 | * If the interrupt vector table is a table of pointer to isr entry |
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| 128 | * points, then we need to install the appropriate RTEMS interrupt |
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| 129 | * handler for this vector number. |
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| 130 | */ |
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| 131 | |
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| 132 | _CPU_ISR_install_raw_handler( vector, new_handler, old_handler ); |
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| 133 | |
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| 134 | /* |
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| 135 | * We put the actual user ISR address in '_ISR_vector_table'. This will |
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| 136 | * be used by the _ISR_Handler so the user gets control. |
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| 137 | */ |
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| 138 | |
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| 139 | _ISR_Vector_table[ vector ] = new_handler; |
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| 140 | } |
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| 141 | |
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| 142 | /*PAGE |
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| 143 | * |
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| 144 | * _CPU_Install_interrupt_stack |
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| 145 | * |
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| 146 | * NO_CPU Specific Information: |
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| 147 | * |
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| 148 | * XXX document implementation including references if appropriate |
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| 149 | */ |
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| 150 | |
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| 151 | void _CPU_Install_interrupt_stack( void ) |
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| 152 | { |
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| 153 | } |
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| 154 | |
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| 155 | /*PAGE |
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| 156 | * |
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| 157 | * _CPU_Thread_Idle_body |
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| 158 | * |
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| 159 | * NOTES: |
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| 160 | * |
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| 161 | * 1. This is the same as the regular CPU independent algorithm. |
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| 162 | * |
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| 163 | * 2. If you implement this using a "halt", "idle", or "shutdown" |
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| 164 | * instruction, then don't forget to put it in an infinite loop. |
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| 165 | * |
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| 166 | * 3. Be warned. Some processors with onboard DMA have been known |
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| 167 | * to stop the DMA if the CPU were put in IDLE mode. This might |
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| 168 | * also be a problem with other on-chip peripherals. So use this |
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| 169 | * hook with caution. |
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| 170 | * |
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| 171 | * NO_CPU Specific Information: |
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| 172 | * |
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| 173 | * XXX document implementation including references if appropriate |
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| 174 | */ |
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| 175 | |
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[3c87adba] | 176 | void *_CPU_Thread_Idle_body( uint32_t ignored ) |
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[be4a4d2] | 177 | { |
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| 178 | |
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| 179 | for( ; ; ) |
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| 180 | /* insert your "halt" instruction here */ ; |
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| 181 | } |
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