[04a62dce] | 1 | /* Copyright (c) 2002, 2004 Marek Michalkiewicz |
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| 2 | Copyright (c) 2005, 2006, 2007 Eric B. Weddington |
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| 3 | All rights reserved. |
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| 4 | |
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| 5 | Redistribution and use in source and binary forms, with or without |
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| 6 | modification, are permitted provided that the following conditions are met: |
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| 7 | |
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| 8 | * Redistributions of source code must retain the above copyright |
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| 9 | notice, this list of conditions and the following disclaimer. |
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| 10 | |
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| 11 | * Redistributions in binary form must reproduce the above copyright |
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| 12 | notice, this list of conditions and the following disclaimer in |
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| 13 | the documentation and/or other materials provided with the |
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| 14 | distribution. |
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| 15 | |
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| 16 | * Neither the name of the copyright holders nor the names of |
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| 17 | contributors may be used to endorse or promote products derived |
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| 18 | from this software without specific prior written permission. |
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| 19 | |
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| 20 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 21 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 22 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 23 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 24 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 25 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 26 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 27 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 28 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 29 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 30 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 31 | |
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| 32 | /* $Id$ */ |
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| 33 | |
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| 34 | /* |
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| 35 | avr/wdt.h - macros for AVR watchdog timer |
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| 36 | */ |
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| 37 | |
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| 38 | #ifndef _AVR_WDT_H_ |
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| 39 | #define _AVR_WDT_H_ |
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| 40 | |
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| 41 | #include <avr/io.h> |
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| 42 | #include <stdint.h> |
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| 43 | |
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| 44 | /** \file */ |
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| 45 | /** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling |
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| 46 | \code #include <avr/wdt.h> \endcode |
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| 47 | |
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| 48 | This header file declares the interface to some inline macros |
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| 49 | handling the watchdog timer present in many AVR devices. In order |
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| 50 | to prevent the watchdog timer configuration from being |
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| 51 | accidentally altered by a crashing application, a special timed |
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| 52 | sequence is required in order to change it. The macros within |
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| 53 | this header file handle the required sequence automatically |
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| 54 | before changing any value. Interrupts will be disabled during |
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| 55 | the manipulation. |
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| 56 | |
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| 57 | \note Depending on the fuse configuration of the particular |
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| 58 | device, further restrictions might apply, in particular it might |
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| 59 | be disallowed to turn off the watchdog timer. |
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| 60 | |
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| 61 | Note that for newer devices (ATmega88 and newer, effectively any |
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| 62 | AVR that has the option to also generate interrupts), the watchdog |
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| 63 | timer remains active even after a system reset (except a power-on |
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| 64 | condition), using the fastest prescaler value (approximately 15 |
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| 65 | ms). It is therefore required to turn off the watchdog early |
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| 66 | during program startup, the datasheet recommends a sequence like |
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| 67 | the following: |
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| 68 | |
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| 69 | \code |
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| 70 | #include <stdint.h> |
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| 71 | #include <avr/wdt.h> |
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| 72 | |
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| 73 | uint8_t mcusr_mirror __attribute__ ((section (".noinit"))); |
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| 74 | |
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| 75 | void get_mcusr(void) \ |
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| 76 | __attribute__((naked)) \ |
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| 77 | __attribute__((section(".init3"))); |
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| 78 | void get_mcusr(void) |
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| 79 | { |
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| 80 | mcusr_mirror = MCUSR; |
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| 81 | MCUSR = 0; |
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| 82 | wdt_disable(); |
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| 83 | } |
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| 84 | \endcode |
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| 85 | |
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| 86 | Saving the value of MCUSR in \c mcusr_mirror is only needed if the |
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| 87 | application later wants to examine the reset source, but in particular, |
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| 88 | clearing the watchdog reset flag before disabling the |
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| 89 | watchdog is required, according to the datasheet. |
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| 90 | */ |
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| 91 | |
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| 92 | /** |
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| 93 | \ingroup avr_watchdog |
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| 94 | Reset the watchdog timer. When the watchdog timer is enabled, |
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| 95 | a call to this instruction is required before the timer expires, |
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| 96 | otherwise a watchdog-initiated device reset will occur. |
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| 97 | */ |
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| 98 | |
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| 99 | #define wdt_reset() __asm__ __volatile__ ("wdr") |
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| 100 | |
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| 101 | |
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| 102 | #if defined(WDP3) |
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| 103 | # define _WD_PS3_MASK _BV(WDP3) |
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| 104 | #else |
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| 105 | # define _WD_PS3_MASK 0x00 |
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| 106 | #endif |
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| 107 | |
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| 108 | #if defined(WDTCSR) |
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| 109 | # define _WD_CONTROL_REG WDTCSR |
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| 110 | #else |
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| 111 | # define _WD_CONTROL_REG WDTCR |
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| 112 | #endif |
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| 113 | |
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| 114 | #if defined(WDTOE) |
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| 115 | #define _WD_CHANGE_BIT WDTOE |
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| 116 | #else |
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| 117 | #define _WD_CHANGE_BIT WDCE |
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| 118 | #endif |
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| 119 | |
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| 120 | |
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| 121 | /** |
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| 122 | \ingroup avr_watchdog |
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| 123 | Enable the watchdog timer, configuring it for expiry after |
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| 124 | \c timeout (which is a combination of the \c WDP0 through |
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| 125 | \c WDP2 bits to write into the \c WDTCR register; For those devices |
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| 126 | that have a \c WDTCSR register, it uses the combination of the \c WDP0 |
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| 127 | through \c WDP3 bits). |
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| 128 | |
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| 129 | See also the symbolic constants \c WDTO_15MS et al. |
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| 130 | */ |
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| 131 | |
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| 132 | |
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| 133 | #if defined(__AVR_ATxmega16A4__) \ |
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| 134 | || defined(__AVR_ATxmega16D4__) \ |
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| 135 | || defined(__AVR_ATxmega32A4__) \ |
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| 136 | || defined(__AVR_ATxmega32D4__) \ |
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| 137 | || defined(__AVR_ATxmega64A1__) \ |
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| 138 | || defined(__AVR_ATxmega64A3__) \ |
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| 139 | || defined(__AVR_ATxmega128A1__) \ |
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| 140 | || defined(__AVR_ATxmega128A3__) \ |
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| 141 | || defined(__AVR_ATxmega256A3__) \ |
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| 142 | || defined(__AVR_ATxmega256A3B__) |
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| 143 | |
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| 144 | /* |
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| 145 | wdt_enable(WDT_PER_8KCLK_gc); |
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| 146 | */ |
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| 147 | #define wdt_enable(value) \ |
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| 148 | __asm__ __volatile__ ( \ |
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| 149 | "in __tmp_reg__, %0" "\n\t" \ |
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| 150 | "out %1, %3" "\n\t" \ |
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| 151 | "sts %2, %4" "\n\t" \ |
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| 152 | "wdr" "\n\t" \ |
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| 153 | "out %0, __tmp_reg__" "\n\t" \ |
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| 154 | : \ |
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| 155 | : "M" (_SFR_MEM_ADDR(RAMPD)), \ |
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| 156 | "M" (_SFR_MEM_ADDR(CCP)), \ |
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| 157 | "M" (_SFR_MEM_ADDR(WDT_CTRL)), \ |
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| 158 | "r" ((uint8_t)0xD8), \ |
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| 159 | "r" ((uint8_t)(WDT_CEN_bm | WDT_ENABLE_bm | value)) \ |
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| 160 | : "r0" \ |
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| 161 | ) |
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| 162 | |
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| 163 | |
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| 164 | #elif defined(__AVR_AT90CAN32__) \ |
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| 165 | || defined(__AVR_AT90CAN64__) \ |
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| 166 | || defined(__AVR_AT90CAN128__) \ |
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| 167 | || defined(__AVR_AT90PWM1__) \ |
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| 168 | || defined(__AVR_AT90PWM2__) \ |
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| 169 | || defined(__AVR_AT90PWM216__) \ |
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| 170 | || defined(__AVR_AT90PWM2B__) \ |
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| 171 | || defined(__AVR_AT90PWM3__) \ |
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| 172 | || defined(__AVR_AT90PWM316__) \ |
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| 173 | || defined(__AVR_AT90PWM3B__) \ |
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| 174 | || defined(__AVR_AT90PWM81__) \ |
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| 175 | || defined(__AVR_AT90USB1286__) \ |
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| 176 | || defined(__AVR_AT90USB1287__) \ |
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| 177 | || defined(__AVR_AT90USB162__) \ |
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| 178 | || defined(__AVR_AT90USB646__) \ |
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| 179 | || defined(__AVR_AT90USB647__) \ |
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| 180 | || defined(__AVR_AT90USB82__) \ |
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| 181 | || defined(__AVR_ATmega1280__) \ |
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| 182 | || defined(__AVR_ATmega1281__) \ |
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| 183 | || defined(__AVR_ATmega1284P__) \ |
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| 184 | || defined(__AVR_ATmega128RFA1__) \ |
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| 185 | || defined(__AVR_ATmega164__) \ |
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| 186 | || defined(__AVR_ATmega164P__) \ |
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| 187 | || defined(__AVR_ATmega165__) \ |
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| 188 | || defined(__AVR_ATmega165P__) \ |
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| 189 | || defined(__AVR_ATmega168__) \ |
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| 190 | || defined(__AVR_ATmega168P__) \ |
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| 191 | || defined(__AVR_ATmega169__) \ |
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| 192 | || defined(__AVR_ATmega169P__) \ |
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| 193 | || defined(__AVR_ATmega16HVA__) \ |
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| 194 | || defined(__AVR_ATmega16M1__) \ |
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| 195 | || defined(__AVR_ATmega16U4__) \ |
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| 196 | || defined(__AVR_ATmega2560__) \ |
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| 197 | || defined(__AVR_ATmega2561__) \ |
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| 198 | || defined(__AVR_ATmega324__) \ |
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| 199 | || defined(__AVR_ATmega324P__) \ |
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| 200 | || defined(__AVR_ATmega325__) \ |
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| 201 | || defined(__AVR_ATmega3250__) \ |
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| 202 | || defined(__AVR_ATmega328P__) \ |
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| 203 | || defined(__AVR_ATmega329__) \ |
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| 204 | || defined(__AVR_ATmega329P__) \ |
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| 205 | || defined(__AVR_ATmega3290__) \ |
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| 206 | || defined(__AVR_ATmega3290P__) \ |
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| 207 | || defined(__AVR_ATmega32C1__) \ |
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| 208 | || defined(__AVR_ATmega32HVB__) \ |
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| 209 | || defined(__AVR_ATmega32M1__) \ |
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| 210 | || defined(__AVR_ATmega32U4__) \ |
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| 211 | || defined(__AVR_ATmega32U6__) \ |
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| 212 | || defined(__AVR_ATmega406__) \ |
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| 213 | || defined(__AVR_ATmega48__) \ |
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| 214 | || defined(__AVR_ATmega48P__) \ |
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| 215 | || defined(__AVR_ATmega640__) \ |
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| 216 | || defined(__AVR_ATmega644__) \ |
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| 217 | || defined(__AVR_ATmega644P__) \ |
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| 218 | || defined(__AVR_ATmega645__) \ |
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| 219 | || defined(__AVR_ATmega6450__) \ |
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| 220 | || defined(__AVR_ATmega649__) \ |
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| 221 | || defined(__AVR_ATmega6490__) \ |
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| 222 | || defined(__AVR_ATmega64C1__) \ |
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| 223 | || defined(__AVR_ATmega64M1__) \ |
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| 224 | || defined(__AVR_ATmega8HVA__) \ |
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| 225 | || defined(__AVR_ATmega88__) \ |
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| 226 | || defined(__AVR_ATmega88P__) \ |
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| 227 | || defined(__AVR_ATtiny48__) \ |
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| 228 | || defined(__AVR_ATtiny88__) \ |
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| 229 | || defined(__AVR_ATtiny87__) \ |
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| 230 | || defined(__AVR_ATtiny167__) \ |
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| 231 | || defined(__AVR_AT90SCR100__) \ |
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| 232 | || defined(__AVR_ATA6289__) |
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| 233 | |
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| 234 | /* Use STS instruction. */ |
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| 235 | |
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| 236 | #define wdt_enable(value) \ |
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| 237 | __asm__ __volatile__ ( \ |
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| 238 | "in __tmp_reg__,__SREG__" "\n\t" \ |
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| 239 | "cli" "\n\t" \ |
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| 240 | "wdr" "\n\t" \ |
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| 241 | "sts %0,%1" "\n\t" \ |
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| 242 | "out __SREG__,__tmp_reg__" "\n\t" \ |
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| 243 | "sts %0,%2" "\n\t" \ |
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| 244 | : /* no outputs */ \ |
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| 245 | : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \ |
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| 246 | "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \ |
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| 247 | "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \ |
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| 248 | _BV(WDE) | (value & 0x07)) ) \ |
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| 249 | : "r0" \ |
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| 250 | ) |
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| 251 | |
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| 252 | #define wdt_disable() \ |
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| 253 | __asm__ __volatile__ ( \ |
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| 254 | "in __tmp_reg__, __SREG__" "\n\t" \ |
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| 255 | "cli" "\n\t" \ |
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| 256 | "sts %0, %1" "\n\t" \ |
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| 257 | "sts %0, __zero_reg__" "\n\t" \ |
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| 258 | "out __SREG__,__tmp_reg__" "\n\t" \ |
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| 259 | : /* no outputs */ \ |
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| 260 | : "M" (_SFR_MEM_ADDR(_WD_CONTROL_REG)), \ |
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| 261 | "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \ |
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| 262 | : "r0" \ |
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| 263 | ) |
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| 264 | |
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| 265 | |
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| 266 | |
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| 267 | #else |
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| 268 | |
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| 269 | /* Use OUT instruction. */ |
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| 270 | |
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| 271 | #define wdt_enable(value) \ |
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| 272 | __asm__ __volatile__ ( \ |
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| 273 | "in __tmp_reg__,__SREG__" "\n\t" \ |
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| 274 | "cli" "\n\t" \ |
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| 275 | "wdr" "\n\t" \ |
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| 276 | "out %0,%1" "\n\t" \ |
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| 277 | "out __SREG__,__tmp_reg__" "\n\t" \ |
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| 278 | "out %0,%2" \ |
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| 279 | : /* no outputs */ \ |
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| 280 | : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ |
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| 281 | "r" (_BV(_WD_CHANGE_BIT) | _BV(WDE)), \ |
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| 282 | "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) | \ |
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| 283 | _BV(WDE) | (value & 0x07)) ) \ |
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| 284 | : "r0" \ |
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| 285 | ) |
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| 286 | |
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| 287 | /** |
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| 288 | \ingroup avr_watchdog |
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| 289 | Disable the watchdog timer, if possible. This attempts to turn off the |
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| 290 | Enable bit in the watchdog control register. See the datasheet for |
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| 291 | details. |
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| 292 | */ |
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| 293 | #define wdt_disable() \ |
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| 294 | __asm__ __volatile__ ( \ |
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| 295 | "in __tmp_reg__, __SREG__" "\n\t" \ |
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| 296 | "cli" "\n\t" \ |
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| 297 | "out %0, %1" "\n\t" \ |
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| 298 | "out %0, __zero_reg__" "\n\t" \ |
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| 299 | "out __SREG__,__tmp_reg__" "\n\t" \ |
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| 300 | : /* no outputs */ \ |
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| 301 | : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)), \ |
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| 302 | "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))) \ |
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| 303 | : "r0" \ |
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| 304 | ) |
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| 305 | |
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| 306 | #endif |
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| 307 | |
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| 308 | |
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| 309 | |
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| 310 | /** |
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| 311 | \ingroup avr_watchdog |
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| 312 | Symbolic constants for the watchdog timeout. Since the watchdog |
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| 313 | timer is based on a free-running RC oscillator, the times are |
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| 314 | approximate only and apply to a supply voltage of 5 V. At lower |
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| 315 | supply voltages, the times will increase. For older devices, the |
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| 316 | times will be as large as three times when operating at Vcc = 3 V, |
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| 317 | while the newer devices (e. g. ATmega128, ATmega8) only experience |
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| 318 | a negligible change. |
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| 319 | |
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| 320 | Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, |
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| 321 | 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) |
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| 322 | Symbolic constants are formed by the prefix |
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| 323 | \c WDTO_, followed by the time. |
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| 324 | |
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| 325 | Example that would select a watchdog timer expiry of approximately |
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| 326 | 500 ms: |
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| 327 | \code |
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| 328 | wdt_enable(WDTO_500MS); |
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| 329 | \endcode |
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| 330 | */ |
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| 331 | #define WDTO_15MS 0 |
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| 332 | |
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| 333 | /** \ingroup avr_watchdog |
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| 334 | See \c WDT0_15MS */ |
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| 335 | #define WDTO_30MS 1 |
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| 336 | |
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| 337 | /** \ingroup avr_watchdog See |
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| 338 | \c WDT0_15MS */ |
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| 339 | #define WDTO_60MS 2 |
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| 340 | |
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| 341 | /** \ingroup avr_watchdog |
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| 342 | See \c WDT0_15MS */ |
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| 343 | #define WDTO_120MS 3 |
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| 344 | |
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| 345 | /** \ingroup avr_watchdog |
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| 346 | See \c WDT0_15MS */ |
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| 347 | #define WDTO_250MS 4 |
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| 348 | |
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| 349 | /** \ingroup avr_watchdog |
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| 350 | See \c WDT0_15MS */ |
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| 351 | #define WDTO_500MS 5 |
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| 352 | |
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| 353 | /** \ingroup avr_watchdog |
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| 354 | See \c WDT0_15MS */ |
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| 355 | #define WDTO_1S 6 |
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| 356 | |
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| 357 | /** \ingroup avr_watchdog |
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| 358 | See \c WDT0_15MS */ |
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| 359 | #define WDTO_2S 7 |
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| 360 | |
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| 361 | #if defined(__DOXYGEN__) || defined(WDP3) |
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| 362 | |
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| 363 | /** \ingroup avr_watchdog |
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| 364 | See \c WDT0_15MS |
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| 365 | Note: This is only available on the |
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| 366 | ATtiny2313, |
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| 367 | ATtiny24, ATtiny44, ATtiny84, |
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| 368 | ATtiny25, ATtiny45, ATtiny85, |
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| 369 | ATtiny261, ATtiny461, ATtiny861, |
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| 370 | ATmega48, ATmega88, ATmega168, |
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| 371 | ATmega48P, ATmega88P, ATmega168P, ATmega328P, |
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| 372 | ATmega164P, ATmega324P, ATmega644P, ATmega644, |
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| 373 | ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, |
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| 374 | ATmega8HVA, ATmega16HVA, ATmega32HVB, |
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| 375 | ATmega406, ATmega1284P, |
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| 376 | AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, |
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| 377 | AT90PWM81, |
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| 378 | AT90USB82, AT90USB162, |
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| 379 | AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, |
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| 380 | ATtiny48, ATtiny88. |
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| 381 | */ |
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| 382 | #define WDTO_4S 8 |
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| 383 | |
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| 384 | /** \ingroup avr_watchdog |
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| 385 | See \c WDT0_15MS |
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| 386 | Note: This is only available on the |
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| 387 | ATtiny2313, |
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| 388 | ATtiny24, ATtiny44, ATtiny84, |
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| 389 | ATtiny25, ATtiny45, ATtiny85, |
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| 390 | ATtiny261, ATtiny461, ATtiny861, |
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| 391 | ATmega48, ATmega88, ATmega168, |
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| 392 | ATmega48P, ATmega88P, ATmega168P, ATmega328P, |
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| 393 | ATmega164P, ATmega324P, ATmega644P, ATmega644, |
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| 394 | ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, |
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| 395 | ATmega8HVA, ATmega16HVA, ATmega32HVB, |
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| 396 | ATmega406, ATmega1284P, |
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| 397 | AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, |
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| 398 | AT90PWM81, |
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| 399 | AT90USB82, AT90USB162, |
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| 400 | AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, |
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| 401 | ATtiny48, ATtiny88. |
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| 402 | */ |
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| 403 | #define WDTO_8S 9 |
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| 404 | |
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| 405 | #endif /* defined(__DOXYGEN__) || defined(WDP3) */ |
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| 406 | |
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| 407 | |
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| 408 | #endif /* _AVR_WDT_H_ */ |
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