source: rtems/cpukit/score/cpu/avr/avr/sleep.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 16.3 KB
Line 
1/* Copyright (c) 2002, 2004 Theodore A. Roth
2   Copyright (c) 2004, 2007, 2008 Eric B. Weddington
3   Copyright (c) 2005, 2006, 2007 Joerg Wunsch
4   All rights reserved.
5
6   Redistribution and use in source and binary forms, with or without
7   modification, are permitted provided that the following conditions are met:
8
9   * Redistributions of source code must retain the above copyright
10     notice, this list of conditions and the following disclaimer.
11
12   * Redistributions in binary form must reproduce the above copyright
13     notice, this list of conditions and the following disclaimer in
14     the documentation and/or other materials provided with the
15     distribution.
16
17   * Neither the name of the copyright holders nor the names of
18     contributors may be used to endorse or promote products derived
19     from this software without specific prior written permission.
20
21   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31   POSSIBILITY OF SUCH DAMAGE. */
32
33/* $Id$ */
34
35#ifndef _AVR_SLEEP_H_
36#define _AVR_SLEEP_H_ 1
37
38#include <avr/io.h>
39#include <stdint.h>
40
41
42/** \file */
43
44/** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
45
46    \code #include <avr/sleep.h>\endcode
47
48    Use of the \c SLEEP instruction can allow an application to reduce its
49    power comsumption considerably. AVR devices can be put into different
50    sleep modes. Refer to the datasheet for the details relating to the device
51    you are using.
52
53    There are several macros provided in this header file to actually
54    put the device into sleep mode.  The simplest way is to optionally
55    set the desired sleep mode using \c set_sleep_mode() (it usually
56    defaults to idle mode where the CPU is put on sleep but all
57    peripheral clocks are still running), and then call
58    \c sleep_mode(). This macro automatically sets the sleep enable bit, goes
59    to sleep, and clears the sleep enable bit.
60   
61    Example:
62    \code
63    #include <avr/sleep.h>
64
65    ...
66      set_sleep_mode(<mode>);
67      sleep_mode();
68    \endcode
69   
70    Note that unless your purpose is to completely lock the CPU (until a
71    hardware reset), interrupts need to be enabled before going to sleep.
72
73    As the \c sleep_mode() macro might cause race conditions in some
74    situations, the individual steps of manipulating the sleep enable
75    (SE) bit, and actually issuing the \c SLEEP instruction, are provided
76    in the macros \c sleep_enable(), \c sleep_disable(), and
77    \c sleep_cpu().  This also allows for test-and-sleep scenarios that
78    take care of not missing the interrupt that will awake the device
79    from sleep.
80
81    Example:
82    \code
83    #include <avr/interrupt.h>
84    #include <avr/sleep.h>
85
86    ...
87      set_sleep_mode(<mode>);
88      cli();
89      if (some_condition)
90      {
91        sleep_enable();
92        sei();
93        sleep_cpu();
94        sleep_disable();
95      }
96      sei();
97    \endcode
98
99    This sequence ensures an atomic test of \c some_condition with
100    interrupts being disabled.  If the condition is met, sleep mode
101    will be prepared, and the \c SLEEP instruction will be scheduled
102    immediately after an \c SEI instruction.  As the intruction right
103    after the \c SEI is guaranteed to be executed before an interrupt
104    could trigger, it is sure the device will really be put to sleep.
105
106    Some devices have the ability to disable the Brown Out Detector (BOD) before
107    going to sleep. This will also reduce power while sleeping. If the
108    specific AVR device has this ability then an additional macro is defined:
109    \c sleep_bod_disable(). This macro generates inlined assembly code
110    that will correctly implement the timed sequence for disabling the BOD
111    before sleeping. However, there is a limited number of cycles after the
112    BOD has been disabled that the device can be put into sleep mode, otherwise
113    the BOD will not truly be disabled. Recommended practice is to disable
114    the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
115    put the device to sleep (\c sleep_cpu()), like so:
116
117    \code
118    #include <avr/interrupt.h>
119    #include <avr/sleep.h>
120
121    ...
122      set_sleep_mode(<mode>);
123      cli();
124      if (some_condition)
125      {
126        sleep_enable();
127        sleep_bod_disable();
128        sei();
129        sleep_cpu();
130        sleep_disable();
131      }
132      sei();
133    \endcode
134*/
135
136
137/* Define an internal sleep control register and an internal sleep enable bit mask. */
138#if defined(SLEEP_CTRL)
139
140    /* XMEGA devices */
141    #define _SLEEP_CONTROL_REG  SLEEP_CTRL
142    #define _SLEEP_ENABLE_MASK  SLEEP_SEN_bm
143
144#elif defined(SMCR)
145
146    #define _SLEEP_CONTROL_REG  SMCR
147    #define _SLEEP_ENABLE_MASK  _BV(SE)
148
149#elif defined(__AVR_AT94K__)
150
151    #define _SLEEP_CONTROL_REG  MCUR
152    #define _SLEEP_ENABLE_MASK  _BV(SE)
153
154#else
155
156    #define _SLEEP_CONTROL_REG  MCUCR
157    #define _SLEEP_ENABLE_MASK  _BV(SE)
158
159#endif
160
161
162/* Define set_sleep_mode() and sleep mode values per device. */
163#if defined(__AVR_ATmega161__)
164
165    #define SLEEP_MODE_IDLE         0
166    #define SLEEP_MODE_PWR_DOWN     1
167    #define SLEEP_MODE_PWR_SAVE     2
168
169    #define set_sleep_mode(mode) \
170    do { \
171        MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
172        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
173    } while(0)
174
175
176#elif defined(__AVR_ATmega162__) \
177|| defined(__AVR_ATmega8515__)
178
179    #define SLEEP_MODE_IDLE         0
180    #define SLEEP_MODE_PWR_DOWN     1
181    #define SLEEP_MODE_PWR_SAVE     2
182    #define SLEEP_MODE_ADC          3
183    #define SLEEP_MODE_STANDBY      4
184    #define SLEEP_MODE_EXT_STANDBY  5
185
186    #define set_sleep_mode(mode) \
187    do { \
188        MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
189        MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
190        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
191    } while(0)
192
193#elif defined(__AVR_AT90S2313__) \
194|| defined(__AVR_AT90S2323__) \
195|| defined(__AVR_AT90S2333__) \
196|| defined(__AVR_AT90S2343__) \
197|| defined(__AVR_AT43USB320__) \
198|| defined(__AVR_AT43USB355__) \
199|| defined(__AVR_AT90S4414__) \
200|| defined(__AVR_AT90S4433__) \
201|| defined(__AVR_AT90S8515__) \
202|| defined(__AVR_ATtiny22__)
203
204    #define SLEEP_MODE_IDLE         0
205    #define SLEEP_MODE_PWR_DOWN     _BV(SM)
206
207    #define set_sleep_mode(mode) \
208    do { \
209        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~__BV(SM)) | (mode)); \
210    } while(0)
211
212#elif defined(__AVR_ATtiny167__) \
213|| defined(__AVR_ATtiny87__)
214
215    #define SLEEP_MODE_IDLE         0
216    #define SLEEP_MODE_ADC          _BV(SM0)
217    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
218
219    #define set_sleep_mode(mode) \
220    do { \
221        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
222    } while(0)
223
224#elif defined(__AVR_AT90S4434__) \
225|| defined(__AVR_AT76C711__) \
226|| defined(__AVR_AT90S8535__) \
227|| defined(__AVR_ATmega103__) \
228|| defined(__AVR_ATmega161__) \
229|| defined(__AVR_ATmega163__) \
230|| defined(__AVR_ATtiny13__) \
231|| defined(__AVR_ATtiny13A__) \
232|| defined(__AVR_ATtiny15__) \
233|| defined(__AVR_ATtiny24__) \
234|| defined(__AVR_ATtiny44__) \
235|| defined(__AVR_ATtiny84__) \
236|| defined(__AVR_ATtiny25__) \
237|| defined(__AVR_ATtiny45__) \
238|| defined(__AVR_ATtiny48__) \
239|| defined(__AVR_ATtiny85__) \
240|| defined(__AVR_ATtiny261__) \
241|| defined(__AVR_ATtiny461__) \
242|| defined(__AVR_ATtiny861__) \
243|| defined(__AVR_ATtiny88__)
244
245    #define SLEEP_MODE_IDLE         0
246    #define SLEEP_MODE_ADC          _BV(SM0)
247    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
248    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
249
250    #define set_sleep_mode(mode) \
251    do { \
252        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
253    } while(0)
254
255#elif defined(__AVR_ATtiny2313__)
256
257    #define SLEEP_MODE_IDLE         0
258    #define SLEEP_MODE_PWR_DOWN     (_BV(SM0) | _BV(SM1))
259    #define SLEEP_MODE_STANDBY      _BV(SM1)
260
261    #define set_sleep_mode(mode) \
262    do { \
263        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
264    } while(0)
265
266#elif defined(__AVR_AT94K__)
267
268    #define SLEEP_MODE_IDLE         0
269    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
270    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
271
272    #define set_sleep_mode(mode) \
273    do { \
274        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
275    } while(0)
276
277#elif defined(__AVR_ATtiny26__) \
278|| defined(__AVR_ATtiny43U__)
279
280    #define SLEEP_MODE_IDLE         0
281    #define SLEEP_MODE_ADC          _BV(SM0)
282    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
283    #define SLEEP_MODE_STANDBY      (_BV(SM0) | _BV(SM1))
284
285    #define set_sleep_mode(mode) \
286    do { \
287        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
288    } while(0)
289
290#elif defined(__AVR_AT90PWM216__) \
291|| defined(__AVR_AT90PWM316__) \
292|| defined(__AVR_AT90PWM81__)
293
294    #define SLEEP_MODE_IDLE         0
295    #define SLEEP_MODE_ADC          _BV(SM0)
296    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
297    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
298
299    #define set_sleep_mode(mode) \
300    do { \
301        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
302    } while(0)
303
304#elif \
305defined(__AVR_AT90PWM1__) \
306|| defined(__AVR_AT90PWM2__) \
307|| defined(__AVR_AT90PWM2B__) \
308|| defined(__AVR_AT90PWM3__) \
309|| defined(__AVR_AT90PWM3B__) \
310|| defined(__AVR_ATmega128__) \
311|| defined(__AVR_ATmega16__) \
312|| defined(__AVR_ATmega162__) \
313|| defined(__AVR_ATmega165__) \
314|| defined(__AVR_ATmega165P__) \
315|| defined(__AVR_ATmega169__) \
316|| defined(__AVR_ATmega169P__) \
317|| defined(__AVR_ATmega32__) \
318|| defined(__AVR_ATmega323__) \
319|| defined(__AVR_ATmega325__) \
320|| defined(__AVR_ATmega3250__) \
321|| defined(__AVR_ATmega329__) \
322|| defined(__AVR_ATmega329P__) \
323|| defined(__AVR_ATmega3290__) \
324|| defined(__AVR_ATmega3290P__) \
325|| defined(__AVR_ATmega406__) \
326|| defined(__AVR_ATmega64__) \
327|| defined(__AVR_ATmega645__) \
328|| defined(__AVR_ATmega6450__) \
329|| defined(__AVR_ATmega649__) \
330|| defined(__AVR_ATmega6490__) \
331|| defined(__AVR_ATmega8__) \
332|| defined(__AVR_ATmega8515__) \
333|| defined(__AVR_ATmega8535__) \
334|| defined(__AVR_AT90CAN128__) \
335|| defined(__AVR_AT90CAN32__) \
336|| defined(__AVR_AT90CAN64__) \
337|| defined(__AVR_ATmega1280__) \
338|| defined(__AVR_ATmega1281__) \
339|| defined(__AVR_ATmega1284P__) \
340|| defined(__AVR_ATmega128RFA1__) \
341|| defined(__AVR_ATmega2560__) \
342|| defined(__AVR_ATmega2561__) \
343|| defined(__AVR_ATmega640__) \
344|| defined(__AVR_ATmega164P__) \
345|| defined(__AVR_ATmega324P__) \
346|| defined(__AVR_ATmega644__) \
347|| defined(__AVR_ATmega644P__) \
348|| defined(__AVR_ATmega16HVA__) \
349|| defined(__AVR_ATmega8HVA__) \
350|| defined(__AVR_ATmega32HVB__) \
351|| defined(__AVR_AT90USB162__) \
352|| defined(__AVR_AT90USB82__) \
353|| defined(__AVR_AT90USB1286__) \
354|| defined(__AVR_AT90USB1287__) \
355|| defined(__AVR_AT90USB646__) \
356|| defined(__AVR_AT90USB647__) \
357|| defined(__AVR_ATmega168__) \
358|| defined(__AVR_ATmega48__) \
359|| defined(__AVR_ATmega88__) \
360|| defined(__AVR_ATmega16M1__) \
361|| defined(__AVR_ATmega16U4__) \
362|| defined(__AVR_ATmega32C1__) \
363|| defined(__AVR_ATmega32M1__) \
364|| defined(__AVR_ATmega32U4__) \
365|| defined(__AVR_ATmega32U6__) \
366|| defined(__AVR_ATmega64C1__) \
367|| defined(__AVR_ATmega64M1__) \
368|| defined(__AVR_ATmega48P__) \
369|| defined(__AVR_ATmega88P__) \
370|| defined(__AVR_ATmega168P__) \
371|| defined(__AVR_ATmega328P__)
372
373    #define SLEEP_MODE_IDLE         (0)
374    #define SLEEP_MODE_ADC          _BV(SM0)
375    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
376    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
377    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
378    #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
379
380
381    #define set_sleep_mode(mode) \
382    do { \
383        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
384    } while(0)
385
386#elif defined(__AVR_ATxmega16A4__) \
387|| defined(__AVR_ATxmega16D4__) \
388|| defined(__AVR_ATxmega32A4__) \
389|| defined(__AVR_ATxmega32D4__) \
390|| defined(__AVR_ATxmega64A1__) \
391|| defined(__AVR_ATxmega64A3__) \
392|| defined(__AVR_ATxmega128A1__) \
393|| defined(__AVR_ATxmega128A3__) \
394|| defined(__AVR_ATxmega256A3__) \
395|| defined(__AVR_ATxmega256A3B__)
396
397    #define SLEEP_MODE_IDLE         (0)
398    #define SLEEP_MODE_PWR_DOWN     (SLEEP_SMODE1_bm)
399    #define SLEEP_MODE_PWR_SAVE     (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
400    #define SLEEP_MODE_STANDBY      (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
401    #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
402
403    #define set_sleep_mode(mode) \
404    do { \
405        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
406    } while(0)
407
408#elif defined(__AVR_AT90SCR100__)
409
410    #define SLEEP_MODE_IDLE         (0)
411    #define SLEEP_MODE_PWR_DOWN     _BV(SM1)
412    #define SLEEP_MODE_PWR_SAVE     (_BV(SM0) | _BV(SM1))
413    #define SLEEP_MODE_STANDBY      (_BV(SM1) | _BV(SM2))
414    #define SLEEP_MODE_EXT_STANDBY  (_BV(SM0) | _BV(SM1) | _BV(SM2))
415
416    #define set_sleep_mode(mode) \
417    do { \
418        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
419    } while(0)
420
421#elif defined(__AVR_ATA6289__)
422
423    #define SLEEP_MODE_IDLE                     (0)
424    #define SLEEP_MODE_SENSOR_NOISE_REDUCTION   (_BV(SM0))
425    #define SLEEP_MODE_PWR_DOWN                 (_BV(SM1))
426
427    #define set_sleep_mode(mode) \
428    do { \
429        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
430    } while(0)
431
432#else
433
434    #error "No SLEEP mode defined for this device."
435
436#endif
437
438
439
440/** \ingroup avr_sleep
441
442    Put the device in sleep mode. How the device is brought out of sleep mode
443    depends on the specific mode selected with the set_sleep_mode() function.
444    See the data sheet for your device for more details. */
445
446
447#if defined(__DOXYGEN__)
448
449/** \ingroup avr_sleep
450
451    Set the SE (sleep enable) bit.
452*/
453extern void sleep_enable (void);
454
455#else
456
457#define sleep_enable()             \
458do {                               \
459  _SLEEP_CONTROL_REG |= (uint8_t)_SLEEP_ENABLE_MASK;   \
460} while(0)
461
462#endif
463
464
465#if defined(__DOXYGEN__)
466
467/** \ingroup avr_sleep
468
469    Clear the SE (sleep enable) bit.
470*/
471extern void sleep_disable (void);
472
473#else
474
475#define sleep_disable()            \
476do {                               \
477  _SLEEP_CONTROL_REG &= (uint8_t)(~_SLEEP_ENABLE_MASK);  \
478} while(0)
479
480#endif
481
482
483/** \ingroup avr_sleep
484
485    Put the device into sleep mode.  The SE bit must be set
486    beforehand, and it is recommended to clear it afterwards.
487*/
488#if defined(__DOXYGEN__)
489
490extern void sleep_cpu (void);
491
492#else
493
494#define sleep_cpu()                              \
495do {                                             \
496  __asm__ __volatile__ ( "sleep" "\n\t" :: );    \
497} while(0)
498
499#endif
500
501
502#if defined(__DOXYGEN__)
503
504extern void sleep_mode (void);
505
506#else
507
508#define sleep_mode() \
509do {                 \
510    sleep_enable();  \
511    sleep_cpu();     \
512    sleep_disable(); \
513} while (0)
514
515#endif
516
517
518#if defined(__DOXYGEN__)
519
520extern void sleep_bod_disable (void);
521
522#else
523
524#if defined(BODS) && defined(BODSE)
525
526#define sleep_bod_disable() \
527{ \
528  uint8_t tempreg; \
529  __asm__ __volatile__("in %[tempreg], %[mcucr]" "\n\t" \
530                       "ori %[tempreg], %[bods_bodse]" "\n\t" \
531                       "out %[mcucr], %[tempreg]" "\n\t" \
532                       "andi %[tempreg], %[not_bodse]" "\n\t" \
533                       "out %[mcucr], %[tempreg]" \
534                       : [tempreg] "=&d" (tempreg) \
535                       : [mcucr] "I" _SFR_IO_ADDR(MCUCR), \
536                         [bods_bodse] "i" (_BV(BODS) | _BV(BODSE)), \
537                         [not_bodse] "i" (~_BV(BODSE))); \
538}
539
540#endif
541
542#endif
543
544
545/*@}*/
546
547#endif /* _AVR_SLEEP_H_ */
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