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source: rtems/cpukit/score/cpu/avr/avr/iox32d4.h @ 04a62dce

4.104.115

Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on 08/06/09 at 14:52:07

2009-08-05 Josh Switnicki <josh.switnicki@…>

Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
preinstall.am: Regenerated.

Property mode set to 100644

File size: 231.4 KB

Line
1	/* Copyright (c) 2009 Atmel Corporation
2	All rights reserved.
3
4	Redistribution and use in source and binary forms, with or without
5	modification, are permitted provided that the following conditions are met:
6
7	* Redistributions of source code must retain the above copyright
8	notice, this list of conditions and the following disclaimer.
9
10	* Redistributions in binary form must reproduce the above copyright
11	notice, this list of conditions and the following disclaimer in
12	the documentation and/or other materials provided with the
13	distribution.
14
15	* Neither the name of the copyright holders nor the names of
16	contributors may be used to endorse or promote products derived
17	from this software without specific prior written permission.
18
19	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29	POSSIBILITY OF SUCH DAMAGE. */
30
31	/* $Id$ */
32
33	/* avr/iox32d4.h - definitions for ATxmega32D4 */
34
35	/* This file should only be included from <avr/io.h>, never directly. */
36
37	#ifndef _AVR_IO_H_
38	# error "Include <avr/io.h> instead of this file."
39	#endif
40
41	#ifndef _AVR_IOXXX_H_
42	# define _AVR_IOXXX_H_ "iox32d4.h"
43	#else
44	# error "Attempt to include more than one <avr/ioXXX.h> file."
45	#endif
46
47
48	#ifndef _AVR_ATxmega32D4_H_
49	#define _AVR_ATxmega32D4_H_ 1
50
51
52	/* Ungrouped common registers */
53	#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
54	#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
55	#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
56	#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
57	#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
58	#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
59	#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
60	#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
61	#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
62	#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
63	#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
64	#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
65	#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
66	#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
67	#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
68	#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
69
70	#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
71	#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
72	#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
73	#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
74	#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
75	#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
76	#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
77	#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
78	#define SREG _SFR_MEM8(0x003F) /* Status Register */
79
80
81	/* C Language Only */
82	#if !defined (__ASSEMBLER__)
83
84	#include <stdint.h>
85
86	typedef volatile uint8_t register8_t;
87	typedef volatile uint16_t register16_t;
88	typedef volatile uint32_t register32_t;
89
90
91	#ifdef _WORDREGISTER
92	#undef _WORDREGISTER
93	#endif
94	#define _WORDREGISTER(regname) \
95	union \
96	{ \
97	register16_t regname; \
98	struct \
99	{ \
100	register8_t regname ## L; \
101	register8_t regname ## H; \
102	}; \
103	}
104
105	#ifdef _DWORDREGISTER
106	#undef _DWORDREGISTER
107	#endif
108	#define _DWORDREGISTER(regname) \
109	union \
110	{ \
111	register32_t regname; \
112	struct \
113	{ \
114	register8_t regname ## 0; \
115	register8_t regname ## 1; \
116	register8_t regname ## 2; \
117	register8_t regname ## 3; \
118	}; \
119	}
120
121
122	/*
123	==========================================================================
124	IO Module Structures
125	==========================================================================
126	*/
127
128
129	/*
130	--------------------------------------------------------------------------
131	XOCD - On-Chip Debug System
132	--------------------------------------------------------------------------
133	*/
134
135	/* On-Chip Debug System */
136	typedef struct OCD_struct
137	{
138	register8_t OCDR0; /* OCD Register 0 */
139	register8_t OCDR1; /* OCD Register 1 */
140	} OCD_t;
141
142
143	/* CCP signatures */
144	typedef enum CCP_enum
145	{
146	CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
147	CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
148	} CCP_t;
149
150
151	/*
152	--------------------------------------------------------------------------
153	CLK - Clock System
154	--------------------------------------------------------------------------
155	*/
156
157	/* Clock System */
158	typedef struct CLK_struct
159	{
160	register8_t CTRL; /* Control Register */
161	register8_t PSCTRL; /* Prescaler Control Register */
162	register8_t LOCK; /* Lock register */
163	register8_t RTCCTRL; /* RTC Control Register */
164	} CLK_t;
165
166	/*
167	--------------------------------------------------------------------------
168	CLK - Clock System
169	--------------------------------------------------------------------------
170	*/
171
172	/* Power Reduction */
173	typedef struct PR_struct
174	{
175	register8_t PRGEN; /* General Power Reduction */
176	register8_t PRPA; /* Power Reduction Port A */
177	register8_t PRPB; /* Power Reduction Port B */
178	register8_t PRPC; /* Power Reduction Port C */
179	register8_t PRPD; /* Power Reduction Port D */
180	register8_t PRPE; /* Power Reduction Port E */
181	register8_t PRPF; /* Power Reduction Port F */
182	} PR_t;
183
184	/* System Clock Selection */
185	typedef enum CLK_SCLKSEL_enum
186	{
187	CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
188	CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
189	CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
190	CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
191	CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
192	} CLK_SCLKSEL_t;
193
194	/* Prescaler A Division Factor */
195	typedef enum CLK_PSADIV_enum
196	{
197	CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
198	CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
199	CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
200	CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
201	CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
202	CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
203	CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
204	CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
205	CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
206	CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
207	} CLK_PSADIV_t;
208
209	/* Prescaler B and C Division Factor */
210	typedef enum CLK_PSBCDIV_enum
211	{
212	CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
213	CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
214	CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
215	CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
216	} CLK_PSBCDIV_t;
217
218	/* RTC Clock Source */
219	typedef enum CLK_RTCSRC_enum
220	{
221	CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
222	CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
223	CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
224	CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
225	} CLK_RTCSRC_t;
226
227
228	/*
229	--------------------------------------------------------------------------
230	SLEEP - Sleep Controller
231	--------------------------------------------------------------------------
232	*/
233
234	/* Sleep Controller */
235	typedef struct SLEEP_struct
236	{
237	register8_t CTRL; /* Control Register */
238	} SLEEP_t;
239
240	/* Sleep Mode */
241	typedef enum SLEEP_SMODE_enum
242	{
243	SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
244	SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
245	SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
246	SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
247	SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
248	} SLEEP_SMODE_t;
249
250
251	/*
252	--------------------------------------------------------------------------
253	OSC - Oscillator
254	--------------------------------------------------------------------------
255	*/
256
257	/* Oscillator */
258	typedef struct OSC_struct
259	{
260	register8_t CTRL; /* Control Register */
261	register8_t STATUS; /* Status Register */
262	register8_t XOSCCTRL; /* External Oscillator Control Register */
263	register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
264	register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
265	register8_t PLLCTRL; /* PLL Control REgister */
266	register8_t DFLLCTRL; /* DFLL Control Register */
267	} OSC_t;
268
269	/* Oscillator Frequency Range */
270	typedef enum OSC_FRQRANGE_enum
271	{
272	OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
273	OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
274	OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
275	OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
276	} OSC_FRQRANGE_t;
277
278	/* External Oscillator Selection and Startup Time */
279	typedef enum OSC_XOSCSEL_enum
280	{
281	OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
282	OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
283	OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
284	OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
285	OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
286	} OSC_XOSCSEL_t;
287
288	/* PLL Clock Source */
289	typedef enum OSC_PLLSRC_enum
290	{
291	OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
292	OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
293	OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
294	} OSC_PLLSRC_t;
295
296
297	/*
298	--------------------------------------------------------------------------
299	DFLL - DFLL
300	--------------------------------------------------------------------------
301	*/
302
303	/* DFLL */
304	typedef struct DFLL_struct
305	{
306	register8_t CTRL; /* Control Register */
307	register8_t reserved_0x01;
308	register8_t CALA; /* Calibration Register A */
309	register8_t CALB; /* Calibration Register B */
310	register8_t COMP0; /* Oscillator Compare Register 0 */
311	register8_t COMP1; /* Oscillator Compare Register 1 */
312	register8_t COMP2; /* Oscillator Compare Register 2 */
313	register8_t reserved_0x07;
314	} DFLL_t;
315
316
317	/*
318	--------------------------------------------------------------------------
319	RST - Reset
320	--------------------------------------------------------------------------
321	*/
322
323	/* Reset */
324	typedef struct RST_struct
325	{
326	register8_t STATUS; /* Status Register */
327	register8_t CTRL; /* Control Register */
328	} RST_t;
329
330
331	/*
332	--------------------------------------------------------------------------
333	WDT - Watch-Dog Timer
334	--------------------------------------------------------------------------
335	*/
336
337	/* Watch-Dog Timer */
338	typedef struct WDT_struct
339	{
340	register8_t CTRL; /* Control */
341	register8_t WINCTRL; /* Windowed Mode Control */
342	register8_t STATUS; /* Status */
343	} WDT_t;
344
345	/* Period setting */
346	typedef enum WDT_PER_enum
347	{
348	WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
349	WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
350	WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
351	WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
352	WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
353	WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
354	WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
355	WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
356	WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
357	WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
358	WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
359	} WDT_PER_t;
360
361	/* Closed window period */
362	typedef enum WDT_WPER_enum
363	{
364	WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
365	WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
366	WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
367	WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
368	WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */
369	WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */
370	WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */
371	WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
372	WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
373	WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
374	WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
375	} WDT_WPER_t;
376
377
378	/*
379	--------------------------------------------------------------------------
380	MCU - MCU Control
381	--------------------------------------------------------------------------
382	*/
383
384	/* MCU Control */
385	typedef struct MCU_struct
386	{
387	register8_t DEVID0; /* Device ID byte 0 */
388	register8_t DEVID1; /* Device ID byte 1 */
389	register8_t DEVID2; /* Device ID byte 2 */
390	register8_t REVID; /* Revision ID */
391	register8_t JTAGUID; /* JTAG User ID */
392	register8_t reserved_0x05;
393	register8_t MCUCR; /* MCU Control */
394	register8_t reserved_0x07;
395	register8_t EVSYSLOCK; /* Event System Lock */
396	register8_t AWEXLOCK; /* AWEX Lock */
397	register8_t reserved_0x0A;
398	register8_t reserved_0x0B;
399	} MCU_t;
400
401
402	/*
403	--------------------------------------------------------------------------
404	PMIC - Programmable Multi-level Interrupt Controller
405	--------------------------------------------------------------------------
406	*/
407
408	/* Programmable Multi-level Interrupt Controller */
409	typedef struct PMIC_struct
410	{
411	register8_t STATUS; /* Status Register */
412	register8_t INTPRI; /* Interrupt Priority */
413	register8_t CTRL; /* Control Register */
414	} PMIC_t;
415
416
417	/*
418	--------------------------------------------------------------------------
419	EVSYS - Event System
420	--------------------------------------------------------------------------
421	*/
422
423	/* Event System */
424	typedef struct EVSYS_struct
425	{
426	register8_t CH0MUX; /* Event Channel 0 Multiplexer */
427	register8_t CH1MUX; /* Event Channel 1 Multiplexer */
428	register8_t CH2MUX; /* Event Channel 2 Multiplexer */
429	register8_t CH3MUX; /* Event Channel 3 Multiplexer */
430	register8_t CH0CTRL; /* Channel 0 Control Register */
431	register8_t CH1CTRL; /* Channel 1 Control Register */
432	register8_t CH2CTRL; /* Channel 2 Control Register */
433	register8_t CH3CTRL; /* Channel 3 Control Register */
434	register8_t STROBE; /* Event Strobe */
435	register8_t DATA; /* Event Data */
436	} EVSYS_t;
437
438	/* Quadrature Decoder Index Recognition Mode */
439	typedef enum EVSYS_QDIRM_enum
440	{
441	EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
442	EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
443	EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
444	EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
445	} EVSYS_QDIRM_t;
446
447	/* Digital filter coefficient */
448	typedef enum EVSYS_DIGFILT_enum
449	{
450	EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
451	EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
452	EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
453	EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
454	EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
455	EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
456	EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
457	EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
458	} EVSYS_DIGFILT_t;
459
460	/* Event Channel multiplexer input selection */
461	typedef enum EVSYS_CHMUX_enum
462	{
463	EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
464	EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
465	EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
466	EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
467	EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
468	EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
469	EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
470	EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
471	EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
472	EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
473	EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
474	EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
475	EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
476	EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
477	EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
478	EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
479	EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
480	EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
481	EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
482	EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
483	EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
484	EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
485	EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
486	EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
487	EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
488	EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
489	EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
490	EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
491	EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
492	EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
493	EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
494	EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
495	EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
496	EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
497	EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
498	EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
499	EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
500	EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
501	EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
502	EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
503	EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
504	EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
505	EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
506	EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
507	EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
508	EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
509	EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
510	EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
511	EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
512	EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
513	EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
514	EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
515	EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
516	EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
517	EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
518	EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
519	EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
520	EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
521	EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
522	EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
523	EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
524	EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
525	EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
526	EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
527	EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
528	EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
529	EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
530	EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
531	EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
532	EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
533	EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
534	EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
535	EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
536	EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
537	EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
538	EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
539	EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
540	EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
541	EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
542	EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
543	EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
544	EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
545	EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
546	EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
547	EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
548	EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
549	EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
550	EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
551	EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
552	EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
553	EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
554	EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
555	EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
556	EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
557	EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
558	EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
559	EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
560	EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
561	EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
562	EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
563	EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
564	EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
565	EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
566	EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
567	EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
568	EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
569	EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
570	EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
571	EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
572	EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
573	EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
574	} EVSYS_CHMUX_t;
575
576
577	/*
578	--------------------------------------------------------------------------
579	NVM - Non Volatile Memory Controller
580	--------------------------------------------------------------------------
581	*/
582
583	/* Non-volatile Memory Controller */
584	typedef struct NVM_struct
585	{
586	register8_t ADDR0; /* Address Register 0 */
587	register8_t ADDR1; /* Address Register 1 */
588	register8_t ADDR2; /* Address Register 2 */
589	register8_t reserved_0x03;
590	register8_t DATA0; /* Data Register 0 */
591	register8_t DATA1; /* Data Register 1 */
592	register8_t DATA2; /* Data Register 2 */
593	register8_t reserved_0x07;
594	register8_t reserved_0x08;
595	register8_t reserved_0x09;
596	register8_t CMD; /* Command */
597	register8_t CTRLA; /* Control Register A */
598	register8_t CTRLB; /* Control Register B */
599	register8_t INTCTRL; /* Interrupt Control */
600	register8_t reserved_0x0E;
601	register8_t STATUS; /* Status */
602	register8_t LOCKBITS; /* Lock Bits */
603	} NVM_t;
604
605	/*
606	--------------------------------------------------------------------------
607	NVM - Non Volatile Memory Controller
608	--------------------------------------------------------------------------
609	*/
610
611	/* Lock Bits */
612	typedef struct NVM_LOCKBITS_struct
613	{
614	register8_t LOCKBITS; /* Lock Bits */
615	} NVM_LOCKBITS_t;
616
617	/*
618	--------------------------------------------------------------------------
619	NVM - Non Volatile Memory Controller
620	--------------------------------------------------------------------------
621	*/
622
623	/* Fuses */
624	typedef struct NVM_FUSES_struct
625	{
626	register8_t FUSEBYTE0; /* User ID */
627	register8_t FUSEBYTE1; /* Watchdog Configuration */
628	register8_t FUSEBYTE2; /* Reset Configuration */
629	register8_t reserved_0x03;
630	register8_t FUSEBYTE4; /* Start-up Configuration */
631	register8_t FUSEBYTE5; /* EESAVE and BOD Level */
632	} NVM_FUSES_t;
633
634	/*
635	--------------------------------------------------------------------------
636	NVM - Non Volatile Memory Controller
637	--------------------------------------------------------------------------
638	*/
639
640	/* Production Signatures */
641	typedef struct NVM_PROD_SIGNATURES_struct
642	{
643	register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
644	register8_t reserved_0x01;
645	register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
646	register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
647	register8_t reserved_0x04;
648	register8_t reserved_0x05;
649	register8_t reserved_0x06;
650	register8_t reserved_0x07;
651	register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
652	register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
653	register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
654	register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
655	register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
656	register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
657	register8_t reserved_0x0E;
658	register8_t reserved_0x0F;
659	register8_t WAFNUM; /* Wafer Number */
660	register8_t reserved_0x11;
661	register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
662	register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
663	register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
664	register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
665	register8_t reserved_0x16;
666	register8_t reserved_0x17;
667	register8_t reserved_0x18;
668	register8_t reserved_0x19;
669	register8_t reserved_0x1A;
670	register8_t reserved_0x1B;
671	register8_t reserved_0x1C;
672	register8_t reserved_0x1D;
673	register8_t reserved_0x1E;
674	register8_t reserved_0x1F;
675	register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
676	register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
677	register8_t reserved_0x22;
678	register8_t reserved_0x23;
679	register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
680	register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
681	register8_t reserved_0x26;
682	register8_t reserved_0x27;
683	register8_t reserved_0x28;
684	register8_t reserved_0x29;
685	register8_t reserved_0x2A;
686	register8_t reserved_0x2B;
687	register8_t reserved_0x2C;
688	register8_t reserved_0x2D;
689	register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
690	register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
691	register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
692	register8_t DACACAINCAL; /* DACA Calibration Byte 1 */
693	register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
694	register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
695	register8_t reserved_0x34;
696	register8_t reserved_0x35;
697	register8_t reserved_0x36;
698	register8_t reserved_0x37;
699	register8_t reserved_0x38;
700	register8_t reserved_0x39;
701	register8_t reserved_0x3A;
702	register8_t reserved_0x3B;
703	register8_t reserved_0x3C;
704	register8_t reserved_0x3D;
705	register8_t reserved_0x3E;
706	} NVM_PROD_SIGNATURES_t;
707
708	/* NVM Command */
709	typedef enum NVM_CMD_enum
710	{
711	NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
712	NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
713	NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
714	NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
715	NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
716	NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
717	NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
718	NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
719	NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
720	NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
721	NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
722	NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
723	NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
724	NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
725	NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
726	NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
727	NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
728	NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
729	NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
730	NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
731	NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
732	NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
733	NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
734	NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
735	NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
736	NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
737	} NVM_CMD_t;
738
739	/* SPM ready interrupt level */
740	typedef enum NVM_SPMLVL_enum
741	{
742	NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
743	NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
744	NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
745	NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
746	} NVM_SPMLVL_t;
747
748	/* EEPROM ready interrupt level */
749	typedef enum NVM_EELVL_enum
750	{
751	NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
752	NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
753	NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
754	NVM_EELVL_HI_gc = (0x03<<0), /* High level */
755	} NVM_EELVL_t;
756
757	/* Boot lock bits - boot setcion */
758	typedef enum NVM_BLBB_enum
759	{
760	NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
761	NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
762	NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
763	NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
764	} NVM_BLBB_t;
765
766	/* Boot lock bits - application section */
767	typedef enum NVM_BLBA_enum
768	{
769	NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
770	NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
771	NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
772	NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
773	} NVM_BLBA_t;
774
775	/* Boot lock bits - application table section */
776	typedef enum NVM_BLBAT_enum
777	{
778	NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
779	NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
780	NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
781	NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
782	} NVM_BLBAT_t;
783
784	/* Lock bits */
785	typedef enum NVM_LB_enum
786	{
787	NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
788	NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
789	NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
790	} NVM_LB_t;
791
792	/* Boot Loader Section Reset Vector */
793	typedef enum BOOTRST_enum
794	{
795	BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
796	BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
797	} BOOTRST_t;
798
799	/* BOD operation */
800	typedef enum BOD_enum
801	{
802	BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
803	BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
804	BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
805	} BOD_t;
806
807	/* Watchdog (Window) Timeout Period */
808	typedef enum WD_enum
809	{
810	WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
811	WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
812	WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
813	WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
814	WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
815	WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
816	WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
817	WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
818	WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
819	WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
820	WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
821	} WD_t;
822
823	/* Start-up Time */
824	typedef enum SUT_enum
825	{
826	SUT_0MS_gc = (0x03<<2), /* 0 ms */
827	SUT_4MS_gc = (0x01<<2), /* 4 ms */
828	SUT_64MS_gc = (0x00<<2), /* 64 ms */
829	} SUT_t;
830
831	/* Brown Out Detection Voltage Level */
832	typedef enum BODLVL_enum
833	{
834	BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
835	BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */
836	BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */
837	BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */
838	BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */
839	BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */
840	BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */
841	} BODLVL_t;
842
843
844	/*
845	--------------------------------------------------------------------------
846	AC - Analog Comparator
847	--------------------------------------------------------------------------
848	*/
849
850	/* Analog Comparator */
851	typedef struct AC_struct
852	{
853	register8_t AC0CTRL; /* Comparator 0 Control */
854	register8_t AC1CTRL; /* Comparator 1 Control */
855	register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
856	register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
857	register8_t CTRLA; /* Control Register A */
858	register8_t CTRLB; /* Control Register B */
859	register8_t WINCTRL; /* Window Mode Control */
860	register8_t STATUS; /* Status */
861	} AC_t;
862
863	/* Interrupt mode */
864	typedef enum AC_INTMODE_enum
865	{
866	AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
867	AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
868	AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
869	} AC_INTMODE_t;
870
871	/* Interrupt level */
872	typedef enum AC_INTLVL_enum
873	{
874	AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
875	AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
876	AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
877	AC_INTLVL_HI_gc = (0x03<<4), /* High level */
878	} AC_INTLVL_t;
879
880	/* Hysteresis mode selection */
881	typedef enum AC_HYSMODE_enum
882	{
883	AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
884	AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
885	AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
886	} AC_HYSMODE_t;
887
888	/* Positive input multiplexer selection */
889	typedef enum AC_MUXPOS_enum
890	{
891	AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
892	AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
893	AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
894	AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
895	AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
896	AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
897	AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
898	AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
899	} AC_MUXPOS_t;
900
901	/* Negative input multiplexer selection */
902	typedef enum AC_MUXNEG_enum
903	{
904	AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
905	AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
906	AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
907	AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
908	AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
909	AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
910	AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
911	AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
912	} AC_MUXNEG_t;
913
914	/* Windows interrupt mode */
915	typedef enum AC_WINTMODE_enum
916	{
917	AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
918	AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
919	AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
920	AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
921	} AC_WINTMODE_t;
922
923	/* Window interrupt level */
924	typedef enum AC_WINTLVL_enum
925	{
926	AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
927	AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
928	AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
929	AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
930	} AC_WINTLVL_t;
931
932	/* Window mode state */
933	typedef enum AC_WSTATE_enum
934	{
935	AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
936	AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
937	AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
938	} AC_WSTATE_t;
939
940
941	/*
942	--------------------------------------------------------------------------
943	ADC - Analog/Digital Converter
944	--------------------------------------------------------------------------
945	*/
946
947	/* ADC Channel */
948	typedef struct ADC_CH_struct
949	{
950	register8_t CTRL; /* Control Register */
951	register8_t MUXCTRL; /* MUX Control */
952	register8_t INTCTRL; /* Channel Interrupt Control */
953	register8_t INTFLAGS; /* Interrupt Flags */
954	_WORDREGISTER(RES); /* Channel Result */
955	register8_t reserved_0x6;
956	register8_t reserved_0x7;
957	} ADC_CH_t;
958
959	/*
960	--------------------------------------------------------------------------
961	ADC - Analog/Digital Converter
962	--------------------------------------------------------------------------
963	*/
964
965	/* Analog-to-Digital Converter */
966	typedef struct ADC_struct
967	{
968	register8_t CTRLA; /* Control Register A */
969	register8_t CTRLB; /* Control Register B */
970	register8_t REFCTRL; /* Reference Control */
971	register8_t EVCTRL; /* Event Control */
972	register8_t PRESCALER; /* Clock Prescaler */
973	register8_t CALCTRL; /* Calibration Control Register */
974	register8_t INTFLAGS; /* Interrupt Flags */
975	register8_t reserved_0x07;
976	register8_t reserved_0x08;
977	register8_t reserved_0x09;
978	register8_t reserved_0x0A;
979	register8_t reserved_0x0B;
980	_WORDREGISTER(CAL); /* Calibration Value */
981	register8_t reserved_0x0E;
982	register8_t reserved_0x0F;
983	_WORDREGISTER(CH0RES); /* Channel 0 Result */
984	_WORDREGISTER(CMP); /* Compare Value */
985	register8_t reserved_0x1A;
986	register8_t reserved_0x1B;
987	register8_t reserved_0x1C;
988	register8_t reserved_0x1D;
989	register8_t reserved_0x1E;
990	register8_t reserved_0x1F;
991	ADC_CH_t CH0; /* ADC Channel 0 */
992	} ADC_t;
993
994	/* Positive input multiplexer selection */
995	typedef enum ADC_CH_MUXPOS_enum
996	{
997	ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
998	ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
999	ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
1000	ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
1001	ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
1002	ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
1003	ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
1004	ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
1005	} ADC_CH_MUXPOS_t;
1006
1007	/* Internal input multiplexer selections */
1008	typedef enum ADC_CH_MUXINT_enum
1009	{
1010	ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
1011	ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
1012	ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
1013	ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
1014	} ADC_CH_MUXINT_t;
1015
1016	/* Negative input multiplexer selection */
1017	typedef enum ADC_CH_MUXNEG_enum
1018	{
1019	ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
1020	ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
1021	ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
1022	ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
1023	ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
1024	ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
1025	ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
1026	ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
1027	} ADC_CH_MUXNEG_t;
1028
1029	/* Input mode */
1030	typedef enum ADC_CH_INPUTMODE_enum
1031	{
1032	ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1033	ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1034	ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1035	ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1036	} ADC_CH_INPUTMODE_t;
1037
1038	/* Gain factor */
1039	typedef enum ADC_CH_GAIN_enum
1040	{
1041	ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1042	ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1043	ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1044	ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1045	ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1046	ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1047	ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1048	} ADC_CH_GAIN_t;
1049
1050	/* Conversion result resolution */
1051	typedef enum ADC_RESOLUTION_enum
1052	{
1053	ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1054	ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1055	ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1056	} ADC_RESOLUTION_t;
1057
1058	/* Voltage reference selection */
1059	typedef enum ADC_REFSEL_enum
1060	{
1061	ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1062	ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
1063	ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1064	ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1065	} ADC_REFSEL_t;
1066
1067	/* Channel sweep selection */
1068	typedef enum ADC_SWEEP_enum
1069	{
1070	ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
1071	} ADC_SWEEP_t;
1072
1073	/* Event channel input selection */
1074	typedef enum ADC_EVSEL_enum
1075	{
1076	ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1077	ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1078	ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1079	ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1080	ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1081	ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1082	ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1083	ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1084	} ADC_EVSEL_t;
1085
1086	/* Event action selection */
1087	typedef enum ADC_EVACT_enum
1088	{
1089	ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1090	ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1091	} ADC_EVACT_t;
1092
1093	/* Interupt mode */
1094	typedef enum ADC_CH_INTMODE_enum
1095	{
1096	ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1097	ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1098	ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1099	} ADC_CH_INTMODE_t;
1100
1101	/* Interrupt level */
1102	typedef enum ADC_CH_INTLVL_enum
1103	{
1104	ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1105	ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1106	ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1107	ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1108	} ADC_CH_INTLVL_t;
1109
1110	/* Clock prescaler */
1111	typedef enum ADC_PRESCALER_enum
1112	{
1113	ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1114	ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1115	ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1116	ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1117	ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1118	ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1119	ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1120	ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1121	} ADC_PRESCALER_t;
1122
1123
1124	/*
1125	--------------------------------------------------------------------------
1126	RTC - Real-Time Clounter
1127	--------------------------------------------------------------------------
1128	*/
1129
1130	/* Real-Time Counter */
1131	typedef struct RTC_struct
1132	{
1133	register8_t CTRL; /* Control Register */
1134	register8_t STATUS; /* Status Register */
1135	register8_t INTCTRL; /* Interrupt Control Register */
1136	register8_t INTFLAGS; /* Interrupt Flags */
1137	register8_t TEMP; /* Temporary register */
1138	register8_t reserved_0x05;
1139	register8_t reserved_0x06;
1140	register8_t reserved_0x07;
1141	_WORDREGISTER(CNT); /* Count Register */
1142	_WORDREGISTER(PER); /* Period Register */
1143	_WORDREGISTER(COMP); /* Compare Register */
1144	} RTC_t;
1145
1146	/* Prescaler Factor */
1147	typedef enum RTC_PRESCALER_enum
1148	{
1149	RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1150	RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1151	RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1152	RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1153	RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1154	RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1155	RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1156	RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1157	} RTC_PRESCALER_t;
1158
1159	/* Compare Interrupt level */
1160	typedef enum RTC_COMPINTLVL_enum
1161	{
1162	RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1163	RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1164	RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1165	RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1166	} RTC_COMPINTLVL_t;
1167
1168	/* Overflow Interrupt level */
1169	typedef enum RTC_OVFINTLVL_enum
1170	{
1171	RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1172	RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1173	RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1174	RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1175	} RTC_OVFINTLVL_t;
1176
1177
1178	/*
1179	--------------------------------------------------------------------------
1180	EBI - External Bus Interface
1181	--------------------------------------------------------------------------
1182	*/
1183
1184	/* EBI Chip Select Module */
1185	typedef struct EBI_CS_struct
1186	{
1187	register8_t CTRLA; /* Chip Select Control Register A */
1188	register8_t CTRLB; /* Chip Select Control Register B */
1189	_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1190	} EBI_CS_t;
1191
1192	/*
1193	--------------------------------------------------------------------------
1194	EBI - External Bus Interface
1195	--------------------------------------------------------------------------
1196	*/
1197
1198	/* External Bus Interface */
1199	typedef struct EBI_struct
1200	{
1201	register8_t CTRL; /* Control */
1202	register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1203	register8_t reserved_0x02;
1204	register8_t reserved_0x03;
1205	_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1206	_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1207	register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1208	register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1209	register8_t reserved_0x0A;
1210	register8_t reserved_0x0B;
1211	register8_t reserved_0x0C;
1212	register8_t reserved_0x0D;
1213	register8_t reserved_0x0E;
1214	register8_t reserved_0x0F;
1215	EBI_CS_t CS0; /* Chip Select 0 */
1216	EBI_CS_t CS1; /* Chip Select 1 */
1217	EBI_CS_t CS2; /* Chip Select 2 */
1218	EBI_CS_t CS3; /* Chip Select 3 */
1219	} EBI_t;
1220
1221	/* Chip Select adress space */
1222	typedef enum EBI_CS_ASPACE_enum
1223	{
1224	EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
1225	EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
1226	EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
1227	EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
1228	EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
1229	EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
1230	EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
1231	EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
1232	EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
1233	EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
1234	EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
1235	EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
1236	EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
1237	EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
1238	EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
1239	EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
1240	EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
1241	} EBI_CS_ASPACE_t;
1242
1243	/* */
1244	typedef enum EBI_CS_SRWS_enum
1245	{
1246	EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1247	EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1248	EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1249	EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1250	EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1251	EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1252	EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1253	EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1254	} EBI_CS_SRWS_t;
1255
1256	/* Chip Select address mode */
1257	typedef enum EBI_CS_MODE_enum
1258	{
1259	EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1260	EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1261	EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1262	EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1263	} EBI_CS_MODE_t;
1264
1265	/* Chip Select SDRAM mode */
1266	typedef enum EBI_CS_SDMODE_enum
1267	{
1268	EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1269	EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1270	} EBI_CS_SDMODE_t;
1271
1272	/* */
1273	typedef enum EBI_SDDATAW_enum
1274	{
1275	EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1276	EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1277	} EBI_SDDATAW_t;
1278
1279	/* */
1280	typedef enum EBI_LPCMODE_enum
1281	{
1282	EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1283	EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1284	} EBI_LPCMODE_t;
1285
1286	/* */
1287	typedef enum EBI_SRMODE_enum
1288	{
1289	EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1290	EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1291	EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1292	EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1293	} EBI_SRMODE_t;
1294
1295	/* */
1296	typedef enum EBI_IFMODE_enum
1297	{
1298	EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1299	EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1300	EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1301	EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1302	} EBI_IFMODE_t;
1303
1304	/* */
1305	typedef enum EBI_SDCOL_enum
1306	{
1307	EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1308	EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1309	EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1310	EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1311	} EBI_SDCOL_t;
1312
1313	/* */
1314	typedef enum EBI_MRDLY_enum
1315	{
1316	EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1317	EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1318	EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1319	EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1320	} EBI_MRDLY_t;
1321
1322	/* */
1323	typedef enum EBI_ROWCYCDLY_enum
1324	{
1325	EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1326	EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1327	EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1328	EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1329	EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1330	EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1331	EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1332	EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1333	} EBI_ROWCYCDLY_t;
1334
1335	/* */
1336	typedef enum EBI_RPDLY_enum
1337	{
1338	EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1339	EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1340	EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1341	EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1342	EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1343	EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1344	EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1345	EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1346	} EBI_RPDLY_t;
1347
1348	/* */
1349	typedef enum EBI_WRDLY_enum
1350	{
1351	EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1352	EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1353	EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1354	EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1355	} EBI_WRDLY_t;
1356
1357	/* */
1358	typedef enum EBI_ESRDLY_enum
1359	{
1360	EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1361	EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1362	EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1363	EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1364	EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1365	EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1366	EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1367	EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1368	} EBI_ESRDLY_t;
1369
1370	/* */
1371	typedef enum EBI_ROWCOLDLY_enum
1372	{
1373	EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1374	EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1375	EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1376	EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1377	EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1378	EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1379	EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1380	EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1381	} EBI_ROWCOLDLY_t;
1382
1383
1384	/*
1385	--------------------------------------------------------------------------
1386	TWI - Two-Wire Interface
1387	--------------------------------------------------------------------------
1388	*/
1389
1390	/* */
1391	typedef struct TWI_MASTER_struct
1392	{
1393	register8_t CTRLA; /* Control Register A */
1394	register8_t CTRLB; /* Control Register B */
1395	register8_t CTRLC; /* Control Register C */
1396	register8_t STATUS; /* Status Register */
1397	register8_t BAUD; /* Baurd Rate Control Register */
1398	register8_t ADDR; /* Address Register */
1399	register8_t DATA; /* Data Register */
1400	} TWI_MASTER_t;
1401
1402	/*
1403	--------------------------------------------------------------------------
1404	TWI - Two-Wire Interface
1405	--------------------------------------------------------------------------
1406	*/
1407
1408	/* */
1409	typedef struct TWI_SLAVE_struct
1410	{
1411	register8_t CTRLA; /* Control Register A */
1412	register8_t CTRLB; /* Control Register B */
1413	register8_t STATUS; /* Status Register */
1414	register8_t ADDR; /* Address Register */
1415	register8_t DATA; /* Data Register */
1416	register8_t ADDRMASK; /* Address Mask Register */
1417	} TWI_SLAVE_t;
1418
1419	/*
1420	--------------------------------------------------------------------------
1421	TWI - Two-Wire Interface
1422	--------------------------------------------------------------------------
1423	*/
1424
1425	/* Two-Wire Interface */
1426	typedef struct TWI_struct
1427	{
1428	register8_t CTRL; /* TWI Common Control Register */
1429	TWI_MASTER_t MASTER; /* TWI master module */
1430	TWI_SLAVE_t SLAVE; /* TWI slave module */
1431	} TWI_t;
1432
1433	/* Master Interrupt Level */
1434	typedef enum TWI_MASTER_INTLVL_enum
1435	{
1436	TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1437	TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1438	TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1439	TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1440	} TWI_MASTER_INTLVL_t;
1441
1442	/* Inactive Timeout */
1443	typedef enum TWI_MASTER_TIMEOUT_enum
1444	{
1445	TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1446	TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1447	TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1448	TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1449	} TWI_MASTER_TIMEOUT_t;
1450
1451	/* Master Command */
1452	typedef enum TWI_MASTER_CMD_enum
1453	{
1454	TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1455	TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1456	TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1457	TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1458	} TWI_MASTER_CMD_t;
1459
1460	/* Master Bus State */
1461	typedef enum TWI_MASTER_BUSSTATE_enum
1462	{
1463	TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1464	TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1465	TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1466	TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1467	} TWI_MASTER_BUSSTATE_t;
1468
1469	/* Slave Interrupt Level */
1470	typedef enum TWI_SLAVE_INTLVL_enum
1471	{
1472	TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1473	TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1474	TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1475	TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1476	} TWI_SLAVE_INTLVL_t;
1477
1478	/* Slave Command */
1479	typedef enum TWI_SLAVE_CMD_enum
1480	{
1481	TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1482	TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1483	TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1484	} TWI_SLAVE_CMD_t;
1485
1486
1487	/*
1488	--------------------------------------------------------------------------
1489	PORT - Port Configuration
1490	--------------------------------------------------------------------------
1491	*/
1492
1493	/* I/O port Configuration */
1494	typedef struct PORTCFG_struct
1495	{
1496	register8_t MPCMASK; /* Multi-pin Configuration Mask */
1497	register8_t reserved_0x01;
1498	register8_t VPCTRLA; /* Virtual Port Control Register A */
1499	register8_t VPCTRLB; /* Virtual Port Control Register B */
1500	register8_t CLKEVOUT; /* Clock and Event Out Register */
1501	} PORTCFG_t;
1502
1503	/*
1504	--------------------------------------------------------------------------
1505	PORT - Port Configuration
1506	--------------------------------------------------------------------------
1507	*/
1508
1509	/* Virtual Port */
1510	typedef struct VPORT_struct
1511	{
1512	register8_t DIR; /* I/O Port Data Direction */
1513	register8_t OUT; /* I/O Port Output */
1514	register8_t IN; /* I/O Port Input */
1515	register8_t INTFLAGS; /* Interrupt Flag Register */
1516	} VPORT_t;
1517
1518	/*
1519	--------------------------------------------------------------------------
1520	PORT - Port Configuration
1521	--------------------------------------------------------------------------
1522	*/
1523
1524	/* I/O Ports */
1525	typedef struct PORT_struct
1526	{
1527	register8_t DIR; /* I/O Port Data Direction */
1528	register8_t DIRSET; /* I/O Port Data Direction Set */
1529	register8_t DIRCLR; /* I/O Port Data Direction Clear */
1530	register8_t DIRTGL; /* I/O Port Data Direction Toggle */
1531	register8_t OUT; /* I/O Port Output */
1532	register8_t OUTSET; /* I/O Port Output Set */
1533	register8_t OUTCLR; /* I/O Port Output Clear */
1534	register8_t OUTTGL; /* I/O Port Output Toggle */
1535	register8_t IN; /* I/O port Input */
1536	register8_t INTCTRL; /* Interrupt Control Register */
1537	register8_t INT0MASK; /* Port Interrupt 0 Mask */
1538	register8_t INT1MASK; /* Port Interrupt 1 Mask */
1539	register8_t INTFLAGS; /* Interrupt Flag Register */
1540	register8_t reserved_0x0D;
1541	register8_t reserved_0x0E;
1542	register8_t reserved_0x0F;
1543	register8_t PIN0CTRL; /* Pin 0 Control Register */
1544	register8_t PIN1CTRL; /* Pin 1 Control Register */
1545	register8_t PIN2CTRL; /* Pin 2 Control Register */
1546	register8_t PIN3CTRL; /* Pin 3 Control Register */
1547	register8_t PIN4CTRL; /* Pin 4 Control Register */
1548	register8_t PIN5CTRL; /* Pin 5 Control Register */
1549	register8_t PIN6CTRL; /* Pin 6 Control Register */
1550	register8_t PIN7CTRL; /* Pin 7 Control Register */
1551	} PORT_t;
1552
1553	/* Virtual Port 0 Mapping */
1554	typedef enum PORTCFG_VP0MAP_enum
1555	{
1556	PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1557	PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1558	PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1559	PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1560	PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1561	PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1562	PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1563	PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1564	PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1565	PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1566	PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1567	PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1568	PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1569	PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1570	PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1571	PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1572	} PORTCFG_VP0MAP_t;
1573
1574	/* Virtual Port 1 Mapping */
1575	typedef enum PORTCFG_VP1MAP_enum
1576	{
1577	PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1578	PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1579	PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1580	PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1581	PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1582	PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1583	PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1584	PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1585	PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1586	PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1587	PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1588	PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1589	PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1590	PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1591	PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1592	PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1593	} PORTCFG_VP1MAP_t;
1594
1595	/* Virtual Port 2 Mapping */
1596	typedef enum PORTCFG_VP2MAP_enum
1597	{
1598	PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1599	PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1600	PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1601	PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1602	PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1603	PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1604	PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1605	PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1606	PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1607	PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1608	PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1609	PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1610	PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1611	PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1612	PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1613	PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1614	} PORTCFG_VP2MAP_t;
1615
1616	/* Virtual Port 3 Mapping */
1617	typedef enum PORTCFG_VP3MAP_enum
1618	{
1619	PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1620	PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1621	PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1622	PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1623	PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1624	PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1625	PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1626	PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1627	PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1628	PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1629	PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1630	PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1631	PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1632	PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1633	PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1634	PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1635	} PORTCFG_VP3MAP_t;
1636
1637	/* Clock Output Port */
1638	typedef enum PORTCFG_CLKOUT_enum
1639	{
1640	PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
1641	PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
1642	PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
1643	PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
1644	} PORTCFG_CLKOUT_t;
1645
1646	/* Event Output Port */
1647	typedef enum PORTCFG_EVOUT_enum
1648	{
1649	PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
1650	PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
1651	PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
1652	PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
1653	} PORTCFG_EVOUT_t;
1654
1655	/* Port Interrupt 0 Level */
1656	typedef enum PORT_INT0LVL_enum
1657	{
1658	PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1659	PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
1660	PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
1661	PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
1662	} PORT_INT0LVL_t;
1663
1664	/* Port Interrupt 1 Level */
1665	typedef enum PORT_INT1LVL_enum
1666	{
1667	PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1668	PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
1669	PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
1670	PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
1671	} PORT_INT1LVL_t;
1672
1673	/* Output/Pull Configuration */
1674	typedef enum PORT_OPC_enum
1675	{
1676	PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
1677	PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
1678	PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
1679	PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
1680	PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
1681	PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
1682	PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
1683	PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
1684	} PORT_OPC_t;
1685
1686	/* Input/Sense Configuration */
1687	typedef enum PORT_ISC_enum
1688	{
1689	PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
1690	PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
1691	PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
1692	PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
1693	PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
1694	} PORT_ISC_t;
1695
1696
1697	/*
1698	--------------------------------------------------------------------------
1699	TC - 16-bit Timer/Counter With PWM
1700	--------------------------------------------------------------------------
1701	*/
1702
1703	/* 16-bit Timer/Counter 0 */
1704	typedef struct TC0_struct
1705	{
1706	register8_t CTRLA; /* Control Register A */
1707	register8_t CTRLB; /* Control Register B */
1708	register8_t CTRLC; /* Control register C */
1709	register8_t CTRLD; /* Control Register D */
1710	register8_t CTRLE; /* Control Register E */
1711	register8_t reserved_0x05;
1712	register8_t INTCTRLA; /* Interrupt Control Register A */
1713	register8_t INTCTRLB; /* Interrupt Control Register B */
1714	register8_t CTRLFCLR; /* Control Register F Clear */
1715	register8_t CTRLFSET; /* Control Register F Set */
1716	register8_t CTRLGCLR; /* Control Register G Clear */
1717	register8_t CTRLGSET; /* Control Register G Set */
1718	register8_t INTFLAGS; /* Interrupt Flag Register */
1719	register8_t reserved_0x0D;
1720	register8_t reserved_0x0E;
1721	register8_t TEMP; /* Temporary Register For 16-bit Access */
1722	register8_t reserved_0x10;
1723	register8_t reserved_0x11;
1724	register8_t reserved_0x12;
1725	register8_t reserved_0x13;
1726	register8_t reserved_0x14;
1727	register8_t reserved_0x15;
1728	register8_t reserved_0x16;
1729	register8_t reserved_0x17;
1730	register8_t reserved_0x18;
1731	register8_t reserved_0x19;
1732	register8_t reserved_0x1A;
1733	register8_t reserved_0x1B;
1734	register8_t reserved_0x1C;
1735	register8_t reserved_0x1D;
1736	register8_t reserved_0x1E;
1737	register8_t reserved_0x1F;
1738	_WORDREGISTER(CNT); /* Count */
1739	register8_t reserved_0x22;
1740	register8_t reserved_0x23;
1741	register8_t reserved_0x24;
1742	register8_t reserved_0x25;
1743	_WORDREGISTER(PER); /* Period */
1744	_WORDREGISTER(CCA); /* Compare or Capture A */
1745	_WORDREGISTER(CCB); /* Compare or Capture B */
1746	_WORDREGISTER(CCC); /* Compare or Capture C */
1747	_WORDREGISTER(CCD); /* Compare or Capture D */
1748	register8_t reserved_0x30;
1749	register8_t reserved_0x31;
1750	register8_t reserved_0x32;
1751	register8_t reserved_0x33;
1752	register8_t reserved_0x34;
1753	register8_t reserved_0x35;
1754	_WORDREGISTER(PERBUF); /* Period Buffer */
1755	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1756	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1757	_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
1758	_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
1759	} TC0_t;
1760
1761	/*
1762	--------------------------------------------------------------------------
1763	TC - 16-bit Timer/Counter With PWM
1764	--------------------------------------------------------------------------
1765	*/
1766
1767	/* 16-bit Timer/Counter 1 */
1768	typedef struct TC1_struct
1769	{
1770	register8_t CTRLA; /* Control Register A */
1771	register8_t CTRLB; /* Control Register B */
1772	register8_t CTRLC; /* Control register C */
1773	register8_t CTRLD; /* Control Register D */
1774	register8_t CTRLE; /* Control Register E */
1775	register8_t reserved_0x05;
1776	register8_t INTCTRLA; /* Interrupt Control Register A */
1777	register8_t INTCTRLB; /* Interrupt Control Register B */
1778	register8_t CTRLFCLR; /* Control Register F Clear */
1779	register8_t CTRLFSET; /* Control Register F Set */
1780	register8_t CTRLGCLR; /* Control Register G Clear */
1781	register8_t CTRLGSET; /* Control Register G Set */
1782	register8_t INTFLAGS; /* Interrupt Flag Register */
1783	register8_t reserved_0x0D;
1784	register8_t reserved_0x0E;
1785	register8_t TEMP; /* Temporary Register For 16-bit Access */
1786	register8_t reserved_0x10;
1787	register8_t reserved_0x11;
1788	register8_t reserved_0x12;
1789	register8_t reserved_0x13;
1790	register8_t reserved_0x14;
1791	register8_t reserved_0x15;
1792	register8_t reserved_0x16;
1793	register8_t reserved_0x17;
1794	register8_t reserved_0x18;
1795	register8_t reserved_0x19;
1796	register8_t reserved_0x1A;
1797	register8_t reserved_0x1B;
1798	register8_t reserved_0x1C;
1799	register8_t reserved_0x1D;
1800	register8_t reserved_0x1E;
1801	register8_t reserved_0x1F;
1802	_WORDREGISTER(CNT); /* Count */
1803	register8_t reserved_0x22;
1804	register8_t reserved_0x23;
1805	register8_t reserved_0x24;
1806	register8_t reserved_0x25;
1807	_WORDREGISTER(PER); /* Period */
1808	_WORDREGISTER(CCA); /* Compare or Capture A */
1809	_WORDREGISTER(CCB); /* Compare or Capture B */
1810	register8_t reserved_0x2C;
1811	register8_t reserved_0x2D;
1812	register8_t reserved_0x2E;
1813	register8_t reserved_0x2F;
1814	register8_t reserved_0x30;
1815	register8_t reserved_0x31;
1816	register8_t reserved_0x32;
1817	register8_t reserved_0x33;
1818	register8_t reserved_0x34;
1819	register8_t reserved_0x35;
1820	_WORDREGISTER(PERBUF); /* Period Buffer */
1821	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1822	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1823	} TC1_t;
1824
1825	/*
1826	--------------------------------------------------------------------------
1827	TC - 16-bit Timer/Counter With PWM
1828	--------------------------------------------------------------------------
1829	*/
1830
1831	/* Advanced Waveform Extension */
1832	typedef struct AWEX_struct
1833	{
1834	register8_t CTRL; /* Control Register */
1835	register8_t reserved_0x01;
1836	register8_t FDEVMASK; /* Fault Detection Event Mask */
1837	register8_t FDCTRL; /* Fault Detection Control Register */
1838	register8_t STATUS; /* Status Register */
1839	register8_t reserved_0x05;
1840	register8_t DTBOTH; /* Dead Time Both Sides */
1841	register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
1842	register8_t DTLS; /* Dead Time Low Side */
1843	register8_t DTHS; /* Dead Time High Side */
1844	register8_t DTLSBUF; /* Dead Time Low Side Buffer */
1845	register8_t DTHSBUF; /* Dead Time High Side Buffer */
1846	register8_t OUTOVEN; /* Output Override Enable */
1847	} AWEX_t;
1848
1849	/*
1850	--------------------------------------------------------------------------
1851	TC - 16-bit Timer/Counter With PWM
1852	--------------------------------------------------------------------------
1853	*/
1854
1855	/* High-Resolution Extension */
1856	typedef struct HIRES_struct
1857	{
1858	register8_t CTRL; /* Control Register */
1859	} HIRES_t;
1860
1861	/* Clock Selection */
1862	typedef enum TC_CLKSEL_enum
1863	{
1864	TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
1865	TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
1866	TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
1867	TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
1868	TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
1869	TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
1870	TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
1871	TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
1872	TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
1873	TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
1874	TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
1875	TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
1876	TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
1877	TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
1878	TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
1879	TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
1880	} TC_CLKSEL_t;
1881
1882	/* Waveform Generation Mode */
1883	typedef enum TC_WGMODE_enum
1884	{
1885	TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
1886	TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
1887	TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
1888	TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
1889	TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
1890	TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
1891	} TC_WGMODE_t;
1892
1893	/* Event Action */
1894	typedef enum TC_EVACT_enum
1895	{
1896	TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
1897	TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
1898	TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
1899	TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
1900	TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
1901	TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */
1902	TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
1903	} TC_EVACT_t;
1904
1905	/* Event Selection */
1906	typedef enum TC_EVSEL_enum
1907	{
1908	TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
1909	TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
1910	TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
1911	TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
1912	TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
1913	TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
1914	TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
1915	TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
1916	TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
1917	} TC_EVSEL_t;
1918
1919	/* Error Interrupt Level */
1920	typedef enum TC_ERRINTLVL_enum
1921	{
1922	TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1923	TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
1924	TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1925	TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
1926	} TC_ERRINTLVL_t;
1927
1928	/* Overflow Interrupt Level */
1929	typedef enum TC_OVFINTLVL_enum
1930	{
1931	TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1932	TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1933	TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1934	TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1935	} TC_OVFINTLVL_t;
1936
1937	/* Compare or Capture D Interrupt Level */
1938	typedef enum TC_CCDINTLVL_enum
1939	{
1940	TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1941	TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
1942	TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
1943	TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
1944	} TC_CCDINTLVL_t;
1945
1946	/* Compare or Capture C Interrupt Level */
1947	typedef enum TC_CCCINTLVL_enum
1948	{
1949	TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
1950	TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
1951	TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
1952	TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
1953	} TC_CCCINTLVL_t;
1954
1955	/* Compare or Capture B Interrupt Level */
1956	typedef enum TC_CCBINTLVL_enum
1957	{
1958	TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1959	TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
1960	TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1961	TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
1962	} TC_CCBINTLVL_t;
1963
1964	/* Compare or Capture A Interrupt Level */
1965	typedef enum TC_CCAINTLVL_enum
1966	{
1967	TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1968	TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
1969	TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1970	TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
1971	} TC_CCAINTLVL_t;
1972
1973	/* Timer/Counter Command */
1974	typedef enum TC_CMD_enum
1975	{
1976	TC_CMD_NONE_gc = (0x00<<2), /* No Command */
1977	TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
1978	TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
1979	TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
1980	} TC_CMD_t;
1981
1982	/* Fault Detect Action */
1983	typedef enum AWEX_FDACT_enum
1984	{
1985	AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
1986	AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
1987	AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
1988	} AWEX_FDACT_t;
1989
1990	/* High Resolution Enable */
1991	typedef enum HIRES_HREN_enum
1992	{
1993	HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
1994	HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
1995	HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
1996	HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
1997	} HIRES_HREN_t;
1998
1999
2000	/*
2001	--------------------------------------------------------------------------
2002	USART - Universal Asynchronous Receiver-Transmitter
2003	--------------------------------------------------------------------------
2004	*/
2005
2006	/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2007	typedef struct USART_struct
2008	{
2009	register8_t DATA; /* Data Register */
2010	register8_t STATUS; /* Status Register */
2011	register8_t reserved_0x02;
2012	register8_t CTRLA; /* Control Register A */
2013	register8_t CTRLB; /* Control Register B */
2014	register8_t CTRLC; /* Control Register C */
2015	register8_t BAUDCTRLA; /* Baud Rate Control Register A */
2016	register8_t BAUDCTRLB; /* Baud Rate Control Register B */
2017	} USART_t;
2018
2019	/* Receive Complete Interrupt level */
2020	typedef enum USART_RXCINTLVL_enum
2021	{
2022	USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2023	USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2024	USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2025	USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
2026	} USART_RXCINTLVL_t;
2027
2028	/* Transmit Complete Interrupt level */
2029	typedef enum USART_TXCINTLVL_enum
2030	{
2031	USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2032	USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2033	USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2034	USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2035	} USART_TXCINTLVL_t;
2036
2037	/* Data Register Empty Interrupt level */
2038	typedef enum USART_DREINTLVL_enum
2039	{
2040	USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2041	USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2042	USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2043	USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2044	} USART_DREINTLVL_t;
2045
2046	/* Character Size */
2047	typedef enum USART_CHSIZE_enum
2048	{
2049	USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2050	USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2051	USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2052	USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2053	USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2054	} USART_CHSIZE_t;
2055
2056	/* Communication Mode */
2057	typedef enum USART_CMODE_enum
2058	{
2059	USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2060	USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2061	USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2062	USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2063	} USART_CMODE_t;
2064
2065	/* Parity Mode */
2066	typedef enum USART_PMODE_enum
2067	{
2068	USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2069	USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2070	USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2071	} USART_PMODE_t;
2072
2073
2074	/*
2075	--------------------------------------------------------------------------
2076	SPI - Serial Peripheral Interface
2077	--------------------------------------------------------------------------
2078	*/
2079
2080	/* Serial Peripheral Interface */
2081	typedef struct SPI_struct
2082	{
2083	register8_t CTRL; /* Control Register */
2084	register8_t INTCTRL; /* Interrupt Control Register */
2085	register8_t STATUS; /* Status Register */
2086	register8_t DATA; /* Data Register */
2087	} SPI_t;
2088
2089	/* SPI Mode */
2090	typedef enum SPI_MODE_enum
2091	{
2092	SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2093	SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2094	SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2095	SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2096	} SPI_MODE_t;
2097
2098	/* Prescaler setting */
2099	typedef enum SPI_PRESCALER_enum
2100	{
2101	SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2102	SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2103	SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2104	SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2105	} SPI_PRESCALER_t;
2106
2107	/* Interrupt level */
2108	typedef enum SPI_INTLVL_enum
2109	{
2110	SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2111	SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2112	SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2113	SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2114	} SPI_INTLVL_t;
2115
2116
2117	/*
2118	--------------------------------------------------------------------------
2119	IRCOM - IR Communication Module
2120	--------------------------------------------------------------------------
2121	*/
2122
2123	/* IR Communication Module */
2124	typedef struct IRCOM_struct
2125	{
2126	register8_t CTRL; /* Control Register */
2127	register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2128	register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2129	} IRCOM_t;
2130
2131	/* Event channel selection */
2132	typedef enum IRDA_EVSEL_enum
2133	{
2134	IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2135	IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2136	IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2137	IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2138	IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2139	IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2140	IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2141	IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2142	IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2143	} IRDA_EVSEL_t;
2144
2145
2146
2147	/*
2148	==========================================================================
2149	IO Module Instances. Mapped to memory.
2150	==========================================================================
2151	*/
2152
2153	#define GPIO ((GPIO_t ) 0x0000) /* General Purpose IO Registers */
2154	#define VPORT0 ((VPORT_t ) 0x0010) /* Virtual Port 0 */
2155	#define VPORT1 ((VPORT_t ) 0x0014) /* Virtual Port 1 */
2156	#define VPORT2 ((VPORT_t ) 0x0018) /* Virtual Port 2 */
2157	#define VPORT3 ((VPORT_t ) 0x001C) /* Virtual Port 3 */
2158	#define OCD ((OCD_t ) 0x002E) /* On-Chip Debug System */
2159	#define CPU ((CPU_t ) 0x0030) /* CPU Registers */
2160	#define CLK ((CLK_t ) 0x0040) /* Clock System */
2161	#define SLEEP ((SLEEP_t ) 0x0048) /* Sleep Controller */
2162	#define OSC ((OSC_t ) 0x0050) /* Oscillator Control */
2163	#define DFLLRC32M ((DFLL_t ) 0x0060) /* DFLL for 32MHz RC Oscillator */
2164	#define DFLLRC2M ((DFLL_t ) 0x0068) /* DFLL for 2MHz RC Oscillator */
2165	#define PR ((PR_t ) 0x0070) /* Power Reduction */
2166	#define RST ((RST_t ) 0x0078) /* Reset Controller */
2167	#define WDT ((WDT_t ) 0x0080) /* Watch-Dog Timer */
2168	#define MCU ((MCU_t ) 0x0090) /* MCU Control */
2169	#define PMIC ((PMIC_t ) 0x00A0) /* Programmable Interrupt Controller */
2170	#define PORTCFG ((PORTCFG_t ) 0x00B0) /* Port Configuration */
2171	#define EVSYS ((EVSYS_t ) 0x0180) /* Event System */
2172	#define NVM ((NVM_t ) 0x01C0) /* Non Volatile Memory Controller */
2173	#define ADCA ((ADC_t ) 0x0200) /* Analog to Digital Converter A */
2174	#define DACB ((DAC_t ) 0x0320) /* Digital to Analog Converter B */
2175	#define ACA ((AC_t ) 0x0380) /* Analog Comparator A */
2176	#define RTC ((RTC_t ) 0x0400) /* Real-Time Counter */
2177	#define TWIC ((TWI_t ) 0x0480) /* Two-Wire Interface C */
2178	#define PORTA ((PORT_t ) 0x0600) /* Port A */
2179	#define PORTB ((PORT_t ) 0x0620) /* Port B */
2180	#define PORTC ((PORT_t ) 0x0640) /* Port C */
2181	#define PORTD ((PORT_t ) 0x0660) /* Port D */
2182	#define PORTE ((PORT_t ) 0x0680) /* Port E */
2183	#define PORTR ((PORT_t ) 0x07E0) /* Port R */
2184	#define TCC0 ((TC0_t ) 0x0800) /* Timer/Counter C0 */
2185	#define TCC1 ((TC1_t ) 0x0840) /* Timer/Counter C1 */
2186	#define AWEXC ((AWEX_t ) 0x0880) /* Advanced Waveform Extension C */
2187	#define HIRESC ((HIRES_t ) 0x0890) /* High-Resolution Extension C */
2188	#define USARTC0 ((USART_t ) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2189	#define SPIC ((SPI_t ) 0x08C0) /* Serial Peripheral Interface C */
2190	#define IRCOM ((IRCOM_t ) 0x08F8) /* IR Communication Module */
2191	#define TCD0 ((TC0_t ) 0x0900) /* Timer/Counter D0 */
2192	#define USARTD0 ((USART_t ) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2193	#define SPID ((SPI_t ) 0x09C0) /* Serial Peripheral Interface D */
2194	#define TCE0 ((TC0_t ) 0x0A00) /* Timer/Counter E0 */
2195
2196
2197	#endif /* !defined (__ASSEMBLER__) */
2198
2199
2200	/* ========== Flattened fully qualified IO register names ========== */
2201
2202	/* GPIO - General Purpose IO Registers */
2203	#define GPIO_GPIO0 _SFR_MEM8(0x0000)
2204	#define GPIO_GPIO1 _SFR_MEM8(0x0001)
2205	#define GPIO_GPIO2 _SFR_MEM8(0x0002)
2206	#define GPIO_GPIO3 _SFR_MEM8(0x0003)
2207	#define GPIO_GPIO4 _SFR_MEM8(0x0004)
2208	#define GPIO_GPIO5 _SFR_MEM8(0x0005)
2209	#define GPIO_GPIO6 _SFR_MEM8(0x0006)
2210	#define GPIO_GPIO7 _SFR_MEM8(0x0007)
2211	#define GPIO_GPIO8 _SFR_MEM8(0x0008)
2212	#define GPIO_GPIO9 _SFR_MEM8(0x0009)
2213	#define GPIO_GPIOA _SFR_MEM8(0x000A)
2214	#define GPIO_GPIOB _SFR_MEM8(0x000B)
2215	#define GPIO_GPIOC _SFR_MEM8(0x000C)
2216	#define GPIO_GPIOD _SFR_MEM8(0x000D)
2217	#define GPIO_GPIOE _SFR_MEM8(0x000E)
2218	#define GPIO_GPIOF _SFR_MEM8(0x000F)
2219
2220	/* VPORT0 - Virtual Port 0 */
2221	#define VPORT0_DIR _SFR_MEM8(0x0010)
2222	#define VPORT0_OUT _SFR_MEM8(0x0011)
2223	#define VPORT0_IN _SFR_MEM8(0x0012)
2224	#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2225
2226	/* VPORT1 - Virtual Port 1 */
2227	#define VPORT1_DIR _SFR_MEM8(0x0014)
2228	#define VPORT1_OUT _SFR_MEM8(0x0015)
2229	#define VPORT1_IN _SFR_MEM8(0x0016)
2230	#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2231
2232	/* VPORT2 - Virtual Port 2 */
2233	#define VPORT2_DIR _SFR_MEM8(0x0018)
2234	#define VPORT2_OUT _SFR_MEM8(0x0019)
2235	#define VPORT2_IN _SFR_MEM8(0x001A)
2236	#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2237
2238	/* VPORT3 - Virtual Port 3 */
2239	#define VPORT3_DIR _SFR_MEM8(0x001C)
2240	#define VPORT3_OUT _SFR_MEM8(0x001D)
2241	#define VPORT3_IN _SFR_MEM8(0x001E)
2242	#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2243
2244	/* OCD - On-Chip Debug System */
2245	#define OCD_OCDR0 _SFR_MEM8(0x002E)
2246	#define OCD_OCDR1 _SFR_MEM8(0x002F)
2247
2248	/* CPU - CPU Registers */
2249	#define CPU_CCP _SFR_MEM8(0x0034)
2250	#define CPU_RAMPD _SFR_MEM8(0x0038)
2251	#define CPU_RAMPX _SFR_MEM8(0x0039)
2252	#define CPU_RAMPY _SFR_MEM8(0x003A)
2253	#define CPU_RAMPZ _SFR_MEM8(0x003B)
2254	#define CPU_EIND _SFR_MEM8(0x003C)
2255	#define CPU_SPL _SFR_MEM8(0x003D)
2256	#define CPU_SPH _SFR_MEM8(0x003E)
2257	#define CPU_SREG _SFR_MEM8(0x003F)
2258
2259	/* CLK - Clock System */
2260	#define CLK_CTRL _SFR_MEM8(0x0040)
2261	#define CLK_PSCTRL _SFR_MEM8(0x0041)
2262	#define CLK_LOCK _SFR_MEM8(0x0042)
2263	#define CLK_RTCCTRL _SFR_MEM8(0x0043)
2264
2265	/* SLEEP - Sleep Controller */
2266	#define SLEEP_CTRL _SFR_MEM8(0x0048)
2267
2268	/* OSC - Oscillator Control */
2269	#define OSC_CTRL _SFR_MEM8(0x0050)
2270	#define OSC_STATUS _SFR_MEM8(0x0051)
2271	#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2272	#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
2273	#define OSC_RC32KCAL _SFR_MEM8(0x0054)
2274	#define OSC_PLLCTRL _SFR_MEM8(0x0055)
2275	#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2276
2277	/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2278	#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2279	#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2280	#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2281	#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2282	#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2283	#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2284
2285	/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2286	#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2287	#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2288	#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2289	#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2290	#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2291	#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2292
2293	/* PR - Power Reduction */
2294	#define PR_PRGEN _SFR_MEM8(0x0070)
2295	#define PR_PRPA _SFR_MEM8(0x0071)
2296	#define PR_PRPB _SFR_MEM8(0x0072)
2297	#define PR_PRPC _SFR_MEM8(0x0073)
2298	#define PR_PRPD _SFR_MEM8(0x0074)
2299	#define PR_PRPE _SFR_MEM8(0x0075)
2300	#define PR_PRPF _SFR_MEM8(0x0076)
2301
2302	/* RST - Reset Controller */
2303	#define RST_STATUS _SFR_MEM8(0x0078)
2304	#define RST_CTRL _SFR_MEM8(0x0079)
2305
2306	/* WDT - Watch-Dog Timer */
2307	#define WDT_CTRL _SFR_MEM8(0x0080)
2308	#define WDT_WINCTRL _SFR_MEM8(0x0081)
2309	#define WDT_STATUS _SFR_MEM8(0x0082)
2310
2311	/* MCU - MCU Control */
2312	#define MCU_DEVID0 _SFR_MEM8(0x0090)
2313	#define MCU_DEVID1 _SFR_MEM8(0x0091)
2314	#define MCU_DEVID2 _SFR_MEM8(0x0092)
2315	#define MCU_REVID _SFR_MEM8(0x0093)
2316	#define MCU_JTAGUID _SFR_MEM8(0x0094)
2317	#define MCU_MCUCR _SFR_MEM8(0x0096)
2318	#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2319	#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2320
2321	/* PMIC - Programmable Interrupt Controller */
2322	#define PMIC_STATUS _SFR_MEM8(0x00A0)
2323	#define PMIC_INTPRI _SFR_MEM8(0x00A1)
2324	#define PMIC_CTRL _SFR_MEM8(0x00A2)
2325
2326	/* PORTCFG - Port Configuration */
2327	#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2328	#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2329	#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2330	#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2331
2332	/* EVSYS - Event System */
2333	#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2334	#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2335	#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2336	#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2337	#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2338	#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2339	#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2340	#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2341	#define EVSYS_STROBE _SFR_MEM8(0x0190)
2342	#define EVSYS_DATA _SFR_MEM8(0x0191)
2343
2344	/* NVM - Non Volatile Memory Controller */
2345	#define NVM_ADDR0 _SFR_MEM8(0x01C0)
2346	#define NVM_ADDR1 _SFR_MEM8(0x01C1)
2347	#define NVM_ADDR2 _SFR_MEM8(0x01C2)
2348	#define NVM_DATA0 _SFR_MEM8(0x01C4)
2349	#define NVM_DATA1 _SFR_MEM8(0x01C5)
2350	#define NVM_DATA2 _SFR_MEM8(0x01C6)
2351	#define NVM_CMD _SFR_MEM8(0x01CA)
2352	#define NVM_CTRLA _SFR_MEM8(0x01CB)
2353	#define NVM_CTRLB _SFR_MEM8(0x01CC)
2354	#define NVM_INTCTRL _SFR_MEM8(0x01CD)
2355	#define NVM_STATUS _SFR_MEM8(0x01CF)
2356	#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2357
2358	/* ADCA - Analog to Digital Converter A */
2359	#define ADCA_CTRLA _SFR_MEM8(0x0200)
2360	#define ADCA_CTRLB _SFR_MEM8(0x0201)
2361	#define ADCA_REFCTRL _SFR_MEM8(0x0202)
2362	#define ADCA_EVCTRL _SFR_MEM8(0x0203)
2363	#define ADCA_PRESCALER _SFR_MEM8(0x0204)
2364	#define ADCA_CALCTRL _SFR_MEM8(0x0205)
2365	#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2366	#define ADCA_CAL _SFR_MEM16(0x020C)
2367	#define ADCA_CH0RES _SFR_MEM16(0x0210)
2368	#define ADCA_CMP _SFR_MEM16(0x0218)
2369	#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2370	#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2371	#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2372	#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2373	#define ADCA_CH0_RES _SFR_MEM16(0x0224)
2374
2375	/* DACB - Digital to Analog Converter B */
2376
2377	/* ACA - Analog Comparator A */
2378	#define ACA_AC0CTRL _SFR_MEM8(0x0380)
2379	#define ACA_AC1CTRL _SFR_MEM8(0x0381)
2380	#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
2381	#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
2382	#define ACA_CTRLA _SFR_MEM8(0x0384)
2383	#define ACA_CTRLB _SFR_MEM8(0x0385)
2384	#define ACA_WINCTRL _SFR_MEM8(0x0386)
2385	#define ACA_STATUS _SFR_MEM8(0x0387)
2386
2387	/* RTC - Real-Time Counter */
2388	#define RTC_CTRL _SFR_MEM8(0x0400)
2389	#define RTC_STATUS _SFR_MEM8(0x0401)
2390	#define RTC_INTCTRL _SFR_MEM8(0x0402)
2391	#define RTC_INTFLAGS _SFR_MEM8(0x0403)
2392	#define RTC_TEMP _SFR_MEM8(0x0404)
2393	#define RTC_CNT _SFR_MEM16(0x0408)
2394	#define RTC_PER _SFR_MEM16(0x040A)
2395	#define RTC_COMP _SFR_MEM16(0x040C)
2396
2397	/* TWIC - Two-Wire Interface C */
2398	#define TWIC_CTRL _SFR_MEM8(0x0480)
2399	#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
2400	#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
2401	#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
2402	#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
2403	#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
2404	#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
2405	#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
2406	#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
2407	#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
2408	#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
2409	#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
2410	#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
2411	#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
2412
2413	/* PORTA - Port A */
2414	#define PORTA_DIR _SFR_MEM8(0x0600)
2415	#define PORTA_DIRSET _SFR_MEM8(0x0601)
2416	#define PORTA_DIRCLR _SFR_MEM8(0x0602)
2417	#define PORTA_DIRTGL _SFR_MEM8(0x0603)
2418	#define PORTA_OUT _SFR_MEM8(0x0604)
2419	#define PORTA_OUTSET _SFR_MEM8(0x0605)
2420	#define PORTA_OUTCLR _SFR_MEM8(0x0606)
2421	#define PORTA_OUTTGL _SFR_MEM8(0x0607)
2422	#define PORTA_IN _SFR_MEM8(0x0608)
2423	#define PORTA_INTCTRL _SFR_MEM8(0x0609)
2424	#define PORTA_INT0MASK _SFR_MEM8(0x060A)
2425	#define PORTA_INT1MASK _SFR_MEM8(0x060B)
2426	#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
2427	#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
2428	#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
2429	#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
2430	#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
2431	#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
2432	#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
2433	#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
2434	#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
2435
2436	/* PORTB - Port B */
2437	#define PORTB_DIR _SFR_MEM8(0x0620)
2438	#define PORTB_DIRSET _SFR_MEM8(0x0621)
2439	#define PORTB_DIRCLR _SFR_MEM8(0x0622)
2440	#define PORTB_DIRTGL _SFR_MEM8(0x0623)
2441	#define PORTB_OUT _SFR_MEM8(0x0624)
2442	#define PORTB_OUTSET _SFR_MEM8(0x0625)
2443	#define PORTB_OUTCLR _SFR_MEM8(0x0626)
2444	#define PORTB_OUTTGL _SFR_MEM8(0x0627)
2445	#define PORTB_IN _SFR_MEM8(0x0628)
2446	#define PORTB_INTCTRL _SFR_MEM8(0x0629)
2447	#define PORTB_INT0MASK _SFR_MEM8(0x062A)
2448	#define PORTB_INT1MASK _SFR_MEM8(0x062B)
2449	#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
2450	#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
2451	#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
2452	#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
2453	#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
2454	#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
2455	#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
2456	#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
2457	#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
2458
2459	/* PORTC - Port C */
2460	#define PORTC_DIR _SFR_MEM8(0x0640)
2461	#define PORTC_DIRSET _SFR_MEM8(0x0641)
2462	#define PORTC_DIRCLR _SFR_MEM8(0x0642)
2463	#define PORTC_DIRTGL _SFR_MEM8(0x0643)
2464	#define PORTC_OUT _SFR_MEM8(0x0644)
2465	#define PORTC_OUTSET _SFR_MEM8(0x0645)
2466	#define PORTC_OUTCLR _SFR_MEM8(0x0646)
2467	#define PORTC_OUTTGL _SFR_MEM8(0x0647)
2468	#define PORTC_IN _SFR_MEM8(0x0648)
2469	#define PORTC_INTCTRL _SFR_MEM8(0x0649)
2470	#define PORTC_INT0MASK _SFR_MEM8(0x064A)
2471	#define PORTC_INT1MASK _SFR_MEM8(0x064B)
2472	#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
2473	#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
2474	#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
2475	#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
2476	#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
2477	#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
2478	#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
2479	#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
2480	#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
2481
2482	/* PORTD - Port D */
2483	#define PORTD_DIR _SFR_MEM8(0x0660)
2484	#define PORTD_DIRSET _SFR_MEM8(0x0661)
2485	#define PORTD_DIRCLR _SFR_MEM8(0x0662)
2486	#define PORTD_DIRTGL _SFR_MEM8(0x0663)
2487	#define PORTD_OUT _SFR_MEM8(0x0664)
2488	#define PORTD_OUTSET _SFR_MEM8(0x0665)
2489	#define PORTD_OUTCLR _SFR_MEM8(0x0666)
2490	#define PORTD_OUTTGL _SFR_MEM8(0x0667)
2491	#define PORTD_IN _SFR_MEM8(0x0668)
2492	#define PORTD_INTCTRL _SFR_MEM8(0x0669)
2493	#define PORTD_INT0MASK _SFR_MEM8(0x066A)
2494	#define PORTD_INT1MASK _SFR_MEM8(0x066B)
2495	#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
2496	#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
2497	#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
2498	#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
2499	#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
2500	#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
2501	#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
2502	#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
2503	#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
2504
2505	/* PORTE - Port E */
2506	#define PORTE_DIR _SFR_MEM8(0x0680)
2507	#define PORTE_DIRSET _SFR_MEM8(0x0681)
2508	#define PORTE_DIRCLR _SFR_MEM8(0x0682)
2509	#define PORTE_DIRTGL _SFR_MEM8(0x0683)
2510	#define PORTE_OUT _SFR_MEM8(0x0684)
2511	#define PORTE_OUTSET _SFR_MEM8(0x0685)
2512	#define PORTE_OUTCLR _SFR_MEM8(0x0686)
2513	#define PORTE_OUTTGL _SFR_MEM8(0x0687)
2514	#define PORTE_IN _SFR_MEM8(0x0688)
2515	#define PORTE_INTCTRL _SFR_MEM8(0x0689)
2516	#define PORTE_INT0MASK _SFR_MEM8(0x068A)
2517	#define PORTE_INT1MASK _SFR_MEM8(0x068B)
2518	#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
2519	#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
2520	#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
2521	#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
2522	#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
2523	#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
2524	#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
2525	#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
2526	#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
2527
2528	/* PORTR - Port R */
2529	#define PORTR_DIR _SFR_MEM8(0x07E0)
2530	#define PORTR_DIRSET _SFR_MEM8(0x07E1)
2531	#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
2532	#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
2533	#define PORTR_OUT _SFR_MEM8(0x07E4)
2534	#define PORTR_OUTSET _SFR_MEM8(0x07E5)
2535	#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
2536	#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
2537	#define PORTR_IN _SFR_MEM8(0x07E8)
2538	#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
2539	#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
2540	#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
2541	#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
2542	#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
2543	#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
2544	#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
2545	#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
2546	#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
2547	#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
2548	#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
2549	#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
2550
2551	/* TCC0 - Timer/Counter C0 */
2552	#define TCC0_CTRLA _SFR_MEM8(0x0800)
2553	#define TCC0_CTRLB _SFR_MEM8(0x0801)
2554	#define TCC0_CTRLC _SFR_MEM8(0x0802)
2555	#define TCC0_CTRLD _SFR_MEM8(0x0803)
2556	#define TCC0_CTRLE _SFR_MEM8(0x0804)
2557	#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
2558	#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
2559	#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
2560	#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
2561	#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
2562	#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
2563	#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
2564	#define TCC0_TEMP _SFR_MEM8(0x080F)
2565	#define TCC0_CNT _SFR_MEM16(0x0820)
2566	#define TCC0_PER _SFR_MEM16(0x0826)
2567	#define TCC0_CCA _SFR_MEM16(0x0828)
2568	#define TCC0_CCB _SFR_MEM16(0x082A)
2569	#define TCC0_CCC _SFR_MEM16(0x082C)
2570	#define TCC0_CCD _SFR_MEM16(0x082E)
2571	#define TCC0_PERBUF _SFR_MEM16(0x0836)
2572	#define TCC0_CCABUF _SFR_MEM16(0x0838)
2573	#define TCC0_CCBBUF _SFR_MEM16(0x083A)
2574	#define TCC0_CCCBUF _SFR_MEM16(0x083C)
2575	#define TCC0_CCDBUF _SFR_MEM16(0x083E)
2576
2577	/* TCC1 - Timer/Counter C1 */
2578	#define TCC1_CTRLA _SFR_MEM8(0x0840)
2579	#define TCC1_CTRLB _SFR_MEM8(0x0841)
2580	#define TCC1_CTRLC _SFR_MEM8(0x0842)
2581	#define TCC1_CTRLD _SFR_MEM8(0x0843)
2582	#define TCC1_CTRLE _SFR_MEM8(0x0844)
2583	#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
2584	#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
2585	#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
2586	#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
2587	#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
2588	#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
2589	#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
2590	#define TCC1_TEMP _SFR_MEM8(0x084F)
2591	#define TCC1_CNT _SFR_MEM16(0x0860)
2592	#define TCC1_PER _SFR_MEM16(0x0866)
2593	#define TCC1_CCA _SFR_MEM16(0x0868)
2594	#define TCC1_CCB _SFR_MEM16(0x086A)
2595	#define TCC1_PERBUF _SFR_MEM16(0x0876)
2596	#define TCC1_CCABUF _SFR_MEM16(0x0878)
2597	#define TCC1_CCBBUF _SFR_MEM16(0x087A)
2598
2599	/* AWEXC - Advanced Waveform Extension C */
2600	#define AWEXC_CTRL _SFR_MEM8(0x0880)
2601	#define AWEXC_FDEVMASK _SFR_MEM8(0x0882)
2602	#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
2603	#define AWEXC_STATUS _SFR_MEM8(0x0884)
2604	#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
2605	#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
2606	#define AWEXC_DTLS _SFR_MEM8(0x0888)
2607	#define AWEXC_DTHS _SFR_MEM8(0x0889)
2608	#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
2609	#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
2610	#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
2611
2612	/* HIRESC - High-Resolution Extension C */
2613	#define HIRESC_CTRL _SFR_MEM8(0x0890)
2614
2615	/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2616	#define USARTC0_DATA _SFR_MEM8(0x08A0)
2617	#define USARTC0_STATUS _SFR_MEM8(0x08A1)
2618	#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
2619	#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
2620	#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
2621	#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
2622	#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
2623
2624	/* SPIC - Serial Peripheral Interface C */
2625	#define SPIC_CTRL _SFR_MEM8(0x08C0)
2626	#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
2627	#define SPIC_STATUS _SFR_MEM8(0x08C2)
2628	#define SPIC_DATA _SFR_MEM8(0x08C3)
2629
2630	/* IRCOM - IR Communication Module */
2631	#define IRCOM_CTRL _SFR_MEM8(0x08F8)
2632	#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
2633	#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
2634
2635	/* TCD0 - Timer/Counter D0 */
2636	#define TCD0_CTRLA _SFR_MEM8(0x0900)
2637	#define TCD0_CTRLB _SFR_MEM8(0x0901)
2638	#define TCD0_CTRLC _SFR_MEM8(0x0902)
2639	#define TCD0_CTRLD _SFR_MEM8(0x0903)
2640	#define TCD0_CTRLE _SFR_MEM8(0x0904)
2641	#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
2642	#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
2643	#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
2644	#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
2645	#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
2646	#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
2647	#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
2648	#define TCD0_TEMP _SFR_MEM8(0x090F)
2649	#define TCD0_CNT _SFR_MEM16(0x0920)
2650	#define TCD0_PER _SFR_MEM16(0x0926)
2651	#define TCD0_CCA _SFR_MEM16(0x0928)
2652	#define TCD0_CCB _SFR_MEM16(0x092A)
2653	#define TCD0_CCC _SFR_MEM16(0x092C)
2654	#define TCD0_CCD _SFR_MEM16(0x092E)
2655	#define TCD0_PERBUF _SFR_MEM16(0x0936)
2656	#define TCD0_CCABUF _SFR_MEM16(0x0938)
2657	#define TCD0_CCBBUF _SFR_MEM16(0x093A)
2658	#define TCD0_CCCBUF _SFR_MEM16(0x093C)
2659	#define TCD0_CCDBUF _SFR_MEM16(0x093E)
2660
2661	/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2662	#define USARTD0_DATA _SFR_MEM8(0x09A0)
2663	#define USARTD0_STATUS _SFR_MEM8(0x09A1)
2664	#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
2665	#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
2666	#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
2667	#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
2668	#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
2669
2670	/* SPID - Serial Peripheral Interface D */
2671	#define SPID_CTRL _SFR_MEM8(0x09C0)
2672	#define SPID_INTCTRL _SFR_MEM8(0x09C1)
2673	#define SPID_STATUS _SFR_MEM8(0x09C2)
2674	#define SPID_DATA _SFR_MEM8(0x09C3)
2675
2676	/* TCE0 - Timer/Counter E0 */
2677	#define TCE0_CTRLA _SFR_MEM8(0x0A00)
2678	#define TCE0_CTRLB _SFR_MEM8(0x0A01)
2679	#define TCE0_CTRLC _SFR_MEM8(0x0A02)
2680	#define TCE0_CTRLD _SFR_MEM8(0x0A03)
2681	#define TCE0_CTRLE _SFR_MEM8(0x0A04)
2682	#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
2683	#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
2684	#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
2685	#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
2686	#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
2687	#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
2688	#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
2689	#define TCE0_TEMP _SFR_MEM8(0x0A0F)
2690	#define TCE0_CNT _SFR_MEM16(0x0A20)
2691	#define TCE0_PER _SFR_MEM16(0x0A26)
2692	#define TCE0_CCA _SFR_MEM16(0x0A28)
2693	#define TCE0_CCB _SFR_MEM16(0x0A2A)
2694	#define TCE0_CCC _SFR_MEM16(0x0A2C)
2695	#define TCE0_CCD _SFR_MEM16(0x0A2E)
2696	#define TCE0_PERBUF _SFR_MEM16(0x0A36)
2697	#define TCE0_CCABUF _SFR_MEM16(0x0A38)
2698	#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
2699	#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
2700	#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
2701
2702
2703
2704	/================== Bitfield Definitions ================== /
2705
2706	/* XOCD - On-Chip Debug System */
2707	/* OCD.OCDR1 bit masks and bit positions */
2708	#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
2709	#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
2710
2711
2712	/* CPU - CPU */
2713	/* CPU.CCP bit masks and bit positions */
2714	#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
2715	#define CPU_CCP_gp 0 /* CCP signature group position. */
2716	#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
2717	#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
2718	#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
2719	#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
2720	#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
2721	#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
2722	#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
2723	#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
2724	#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
2725	#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
2726	#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
2727	#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
2728	#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
2729	#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
2730	#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
2731	#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
2732
2733
2734	/* CPU.SREG bit masks and bit positions */
2735	#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
2736	#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
2737
2738	#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
2739	#define CPU_T_bp 6 /* Transfer Bit bit position. */
2740
2741	#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
2742	#define CPU_H_bp 5 /* Half Carry Flag bit position. */
2743
2744	#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
2745	#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
2746
2747	#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
2748	#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
2749
2750	#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
2751	#define CPU_N_bp 2 /* Negative Flag bit position. */
2752
2753	#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
2754	#define CPU_Z_bp 1 /* Zero Flag bit position. */
2755
2756	#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
2757	#define CPU_C_bp 0 /* Carry Flag bit position. */
2758
2759
2760	/* CLK - Clock System */
2761	/* CLK.CTRL bit masks and bit positions */
2762	#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
2763	#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
2764	#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
2765	#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
2766	#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
2767	#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
2768	#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
2769	#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
2770
2771
2772	/* CLK.PSCTRL bit masks and bit positions */
2773	#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
2774	#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
2775	#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
2776	#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
2777	#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
2778	#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
2779	#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
2780	#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
2781	#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
2782	#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
2783	#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
2784	#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
2785
2786	#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
2787	#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
2788	#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
2789	#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
2790	#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
2791	#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
2792
2793
2794	/* CLK.LOCK bit masks and bit positions */
2795	#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
2796	#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
2797
2798
2799	/* CLK.RTCCTRL bit masks and bit positions */
2800	#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
2801	#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
2802	#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
2803	#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
2804	#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
2805	#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
2806	#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
2807	#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
2808
2809	#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
2810	#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
2811
2812
2813	/* PR.PRGEN bit masks and bit positions */
2814	#define PR_AES_bm 0x10 /* AES bit mask. */
2815	#define PR_AES_bp 4 /* AES bit position. */
2816
2817	#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
2818	#define PR_EBI_bp 3 /* External Bus Interface bit position. */
2819
2820	#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
2821	#define PR_RTC_bp 2 /* Real-time Counter bit position. */
2822
2823	#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
2824	#define PR_EVSYS_bp 1 /* Event System bit position. */
2825
2826	#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
2827	#define PR_DMA_bp 0 /* DMA-Controller bit position. */
2828
2829
2830	/* PR.PRPA bit masks and bit positions */
2831	#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
2832	#define PR_DAC_bp 2 /* Port A DAC bit position. */
2833
2834	#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
2835	#define PR_ADC_bp 1 /* Port A ADC bit position. */
2836
2837	#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
2838	#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
2839
2840
2841	/* PR.PRPB bit masks and bit positions */
2842	/* PR_DAC_bm Predefined. */
2843	/* PR_DAC_bp Predefined. */
2844
2845	/* PR_ADC_bm Predefined. */
2846	/* PR_ADC_bp Predefined. */
2847
2848	/* PR_AC_bm Predefined. */
2849	/* PR_AC_bp Predefined. */
2850
2851
2852	/* PR.PRPC bit masks and bit positions */
2853	#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
2854	#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
2855
2856	#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
2857	#define PR_USART1_bp 5 /* Port C USART1 bit position. */
2858
2859	#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
2860	#define PR_USART0_bp 4 /* Port C USART0 bit position. */
2861
2862	#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
2863	#define PR_SPI_bp 3 /* Port C SPI bit position. */
2864
2865	#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
2866	#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
2867
2868	#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
2869	#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
2870
2871	#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
2872	#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
2873
2874
2875	/* PR.PRPD bit masks and bit positions */
2876	/* PR_TWI_bm Predefined. */
2877	/* PR_TWI_bp Predefined. */
2878
2879	/* PR_USART1_bm Predefined. */
2880	/* PR_USART1_bp Predefined. */
2881
2882	/* PR_USART0_bm Predefined. */
2883	/* PR_USART0_bp Predefined. */
2884
2885	/* PR_SPI_bm Predefined. */
2886	/* PR_SPI_bp Predefined. */
2887
2888	/* PR_HIRES_bm Predefined. */
2889	/* PR_HIRES_bp Predefined. */
2890
2891	/* PR_TC1_bm Predefined. */
2892	/* PR_TC1_bp Predefined. */
2893
2894	/* PR_TC0_bm Predefined. */
2895	/* PR_TC0_bp Predefined. */
2896
2897
2898	/* PR.PRPE bit masks and bit positions */
2899	/* PR_TWI_bm Predefined. */
2900	/* PR_TWI_bp Predefined. */
2901
2902	/* PR_USART1_bm Predefined. */
2903	/* PR_USART1_bp Predefined. */
2904
2905	/* PR_USART0_bm Predefined. */
2906	/* PR_USART0_bp Predefined. */
2907
2908	/* PR_SPI_bm Predefined. */
2909	/* PR_SPI_bp Predefined. */
2910
2911	/* PR_HIRES_bm Predefined. */
2912	/* PR_HIRES_bp Predefined. */
2913
2914	/* PR_TC1_bm Predefined. */
2915	/* PR_TC1_bp Predefined. */
2916
2917	/* PR_TC0_bm Predefined. */
2918	/* PR_TC0_bp Predefined. */
2919
2920
2921	/* PR.PRPF bit masks and bit positions */
2922	/* PR_TWI_bm Predefined. */
2923	/* PR_TWI_bp Predefined. */
2924
2925	/* PR_USART1_bm Predefined. */
2926	/* PR_USART1_bp Predefined. */
2927
2928	/* PR_USART0_bm Predefined. */
2929	/* PR_USART0_bp Predefined. */
2930
2931	/* PR_SPI_bm Predefined. */
2932	/* PR_SPI_bp Predefined. */
2933
2934	/* PR_HIRES_bm Predefined. */
2935	/* PR_HIRES_bp Predefined. */
2936
2937	/* PR_TC1_bm Predefined. */
2938	/* PR_TC1_bp Predefined. */
2939
2940	/* PR_TC0_bm Predefined. */
2941	/* PR_TC0_bp Predefined. */
2942
2943
2944	/* SLEEP - Sleep Controller */
2945	/* SLEEP.CTRL bit masks and bit positions */
2946	#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
2947	#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
2948	#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
2949	#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
2950	#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
2951	#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
2952	#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
2953	#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
2954
2955	#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
2956	#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
2957
2958
2959	/* OSC - Oscillator */
2960	/* OSC.CTRL bit masks and bit positions */
2961	#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
2962	#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
2963
2964	#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
2965	#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
2966
2967	#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
2968	#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
2969
2970	#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
2971	#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
2972
2973	#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
2974	#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
2975
2976
2977	/* OSC.STATUS bit masks and bit positions */
2978	#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
2979	#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
2980
2981	#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
2982	#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
2983
2984	#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
2985	#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
2986
2987	#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
2988	#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
2989
2990	#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
2991	#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
2992
2993
2994	/* OSC.XOSCCTRL bit masks and bit positions */
2995	#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
2996	#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
2997	#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
2998	#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
2999	#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
3000	#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
3001
3002	#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
3003	#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
3004
3005	#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
3006	#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
3007	#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
3008	#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
3009	#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
3010	#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
3011	#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
3012	#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
3013	#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
3014	#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
3015
3016
3017	/* OSC.XOSCFAIL bit masks and bit positions */
3018	#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
3019	#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
3020
3021	#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
3022	#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
3023
3024
3025	/* OSC.PLLCTRL bit masks and bit positions */
3026	#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
3027	#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
3028	#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
3029	#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
3030	#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
3031	#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
3032
3033	#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
3034	#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
3035	#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
3036	#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
3037	#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
3038	#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
3039	#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
3040	#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
3041	#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
3042	#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
3043	#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
3044	#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
3045
3046
3047	/* OSC.DFLLCTRL bit masks and bit positions */
3048	#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
3049	#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
3050
3051	#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
3052	#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
3053
3054
3055	/* DFLL - DFLL */
3056	/* DFLL.CTRL bit masks and bit positions */
3057	#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
3058	#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
3059
3060
3061	/* DFLL.CALA bit masks and bit positions */
3062	#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
3063	#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
3064	#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
3065	#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
3066	#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
3067	#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
3068	#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
3069	#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
3070	#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
3071	#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
3072	#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
3073	#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
3074	#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
3075	#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
3076	#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
3077	#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
3078
3079
3080	/* DFLL.CALB bit masks and bit positions */
3081	#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
3082	#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
3083	#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
3084	#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
3085	#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
3086	#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
3087	#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
3088	#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
3089	#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
3090	#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
3091	#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
3092	#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
3093	#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
3094	#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
3095
3096
3097	/* RST - Reset */
3098	/* RST.STATUS bit masks and bit positions */
3099	#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
3100	#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
3101
3102	#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
3103	#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
3104
3105	#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
3106	#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
3107
3108	#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
3109	#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
3110
3111	#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
3112	#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
3113
3114	#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
3115	#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
3116
3117	#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
3118	#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
3119
3120
3121	/* RST.CTRL bit masks and bit positions */
3122	#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
3123	#define RST_SWRST_bp 0 /* Software Reset bit position. */
3124
3125
3126	/* WDT - Watch-Dog Timer */
3127	/* WDT.CTRL bit masks and bit positions */
3128	#define WDT_PER_gm 0x3C /* Period group mask. */
3129	#define WDT_PER_gp 2 /* Period group position. */
3130	#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
3131	#define WDT_PER0_bp 2 /* Period bit 0 position. */
3132	#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
3133	#define WDT_PER1_bp 3 /* Period bit 1 position. */
3134	#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
3135	#define WDT_PER2_bp 4 /* Period bit 2 position. */
3136	#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
3137	#define WDT_PER3_bp 5 /* Period bit 3 position. */
3138
3139	#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
3140	#define WDT_ENABLE_bp 1 /* Enable bit position. */
3141
3142	#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
3143	#define WDT_CEN_bp 0 /* Change Enable bit position. */
3144
3145
3146	/* WDT.WINCTRL bit masks and bit positions */
3147	#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
3148	#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
3149	#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
3150	#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
3151	#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
3152	#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
3153	#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
3154	#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
3155	#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
3156	#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
3157
3158	#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
3159	#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
3160
3161	#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
3162	#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
3163
3164
3165	/* WDT.STATUS bit masks and bit positions */
3166	#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
3167	#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
3168
3169
3170	/* MCU - MCU Control */
3171	/* MCU.MCUCR bit masks and bit positions */
3172	#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
3173	#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
3174
3175
3176	/* MCU.EVSYSLOCK bit masks and bit positions */
3177	#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
3178	#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
3179
3180	#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
3181	#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
3182
3183
3184	/* MCU.AWEXLOCK bit masks and bit positions */
3185	#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
3186	#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
3187
3188	#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
3189	#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
3190
3191
3192	/* PMIC - Programmable Multi-level Interrupt Controller */
3193	/* PMIC.STATUS bit masks and bit positions */
3194	#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
3195	#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
3196
3197	#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
3198	#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
3199
3200	#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
3201	#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
3202
3203	#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
3204	#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
3205
3206
3207	/* PMIC.CTRL bit masks and bit positions */
3208	#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
3209	#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
3210
3211	#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
3212	#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
3213
3214	#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
3215	#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
3216
3217	#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
3218	#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
3219
3220	#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
3221	#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
3222
3223
3224	/* EVSYS - Event System */
3225	/* EVSYS.CH0MUX bit masks and bit positions */
3226	#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
3227	#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
3228	#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
3229	#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
3230	#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
3231	#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
3232	#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
3233	#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
3234	#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
3235	#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
3236	#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
3237	#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
3238	#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
3239	#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
3240	#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
3241	#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
3242	#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
3243	#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
3244
3245
3246	/* EVSYS.CH1MUX bit masks and bit positions */
3247	/* EVSYS_CHMUX_gm Predefined. */
3248	/* EVSYS_CHMUX_gp Predefined. */
3249	/* EVSYS_CHMUX0_bm Predefined. */
3250	/* EVSYS_CHMUX0_bp Predefined. */
3251	/* EVSYS_CHMUX1_bm Predefined. */
3252	/* EVSYS_CHMUX1_bp Predefined. */
3253	/* EVSYS_CHMUX2_bm Predefined. */
3254	/* EVSYS_CHMUX2_bp Predefined. */
3255	/* EVSYS_CHMUX3_bm Predefined. */
3256	/* EVSYS_CHMUX3_bp Predefined. */
3257	/* EVSYS_CHMUX4_bm Predefined. */
3258	/* EVSYS_CHMUX4_bp Predefined. */
3259	/* EVSYS_CHMUX5_bm Predefined. */
3260	/* EVSYS_CHMUX5_bp Predefined. */
3261	/* EVSYS_CHMUX6_bm Predefined. */
3262	/* EVSYS_CHMUX6_bp Predefined. */
3263	/* EVSYS_CHMUX7_bm Predefined. */
3264	/* EVSYS_CHMUX7_bp Predefined. */
3265
3266
3267	/* EVSYS.CH2MUX bit masks and bit positions */
3268	/* EVSYS_CHMUX_gm Predefined. */
3269	/* EVSYS_CHMUX_gp Predefined. */
3270	/* EVSYS_CHMUX0_bm Predefined. */
3271	/* EVSYS_CHMUX0_bp Predefined. */
3272	/* EVSYS_CHMUX1_bm Predefined. */
3273	/* EVSYS_CHMUX1_bp Predefined. */
3274	/* EVSYS_CHMUX2_bm Predefined. */
3275	/* EVSYS_CHMUX2_bp Predefined. */
3276	/* EVSYS_CHMUX3_bm Predefined. */
3277	/* EVSYS_CHMUX3_bp Predefined. */
3278	/* EVSYS_CHMUX4_bm Predefined. */
3279	/* EVSYS_CHMUX4_bp Predefined. */
3280	/* EVSYS_CHMUX5_bm Predefined. */
3281	/* EVSYS_CHMUX5_bp Predefined. */
3282	/* EVSYS_CHMUX6_bm Predefined. */
3283	/* EVSYS_CHMUX6_bp Predefined. */
3284	/* EVSYS_CHMUX7_bm Predefined. */
3285	/* EVSYS_CHMUX7_bp Predefined. */
3286
3287
3288	/* EVSYS.CH3MUX bit masks and bit positions */
3289	/* EVSYS_CHMUX_gm Predefined. */
3290	/* EVSYS_CHMUX_gp Predefined. */
3291	/* EVSYS_CHMUX0_bm Predefined. */
3292	/* EVSYS_CHMUX0_bp Predefined. */
3293	/* EVSYS_CHMUX1_bm Predefined. */
3294	/* EVSYS_CHMUX1_bp Predefined. */
3295	/* EVSYS_CHMUX2_bm Predefined. */
3296	/* EVSYS_CHMUX2_bp Predefined. */
3297	/* EVSYS_CHMUX3_bm Predefined. */
3298	/* EVSYS_CHMUX3_bp Predefined. */
3299	/* EVSYS_CHMUX4_bm Predefined. */
3300	/* EVSYS_CHMUX4_bp Predefined. */
3301	/* EVSYS_CHMUX5_bm Predefined. */
3302	/* EVSYS_CHMUX5_bp Predefined. */
3303	/* EVSYS_CHMUX6_bm Predefined. */
3304	/* EVSYS_CHMUX6_bp Predefined. */
3305	/* EVSYS_CHMUX7_bm Predefined. */
3306	/* EVSYS_CHMUX7_bp Predefined. */
3307
3308
3309	/* EVSYS.CH0CTRL bit masks and bit positions */
3310	#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
3311	#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
3312	#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3313	#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3314	#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3315	#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3316
3317	#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
3318	#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
3319
3320	#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
3321	#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
3322
3323	#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
3324	#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
3325	#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
3326	#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
3327	#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
3328	#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
3329	#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
3330	#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
3331
3332
3333	/* EVSYS.CH1CTRL bit masks and bit positions */
3334	/* EVSYS_DIGFILT_gm Predefined. */
3335	/* EVSYS_DIGFILT_gp Predefined. */
3336	/* EVSYS_DIGFILT0_bm Predefined. */
3337	/* EVSYS_DIGFILT0_bp Predefined. */
3338	/* EVSYS_DIGFILT1_bm Predefined. */
3339	/* EVSYS_DIGFILT1_bp Predefined. */
3340	/* EVSYS_DIGFILT2_bm Predefined. */
3341	/* EVSYS_DIGFILT2_bp Predefined. */
3342
3343
3344	/* EVSYS.CH2CTRL bit masks and bit positions */
3345	/* EVSYS_QDIRM_gm Predefined. */
3346	/* EVSYS_QDIRM_gp Predefined. */
3347	/* EVSYS_QDIRM0_bm Predefined. */
3348	/* EVSYS_QDIRM0_bp Predefined. */
3349	/* EVSYS_QDIRM1_bm Predefined. */
3350	/* EVSYS_QDIRM1_bp Predefined. */
3351
3352	/* EVSYS_QDIEN_bm Predefined. */
3353	/* EVSYS_QDIEN_bp Predefined. */
3354
3355	/* EVSYS_QDEN_bm Predefined. */
3356	/* EVSYS_QDEN_bp Predefined. */
3357
3358	/* EVSYS_DIGFILT_gm Predefined. */
3359	/* EVSYS_DIGFILT_gp Predefined. */
3360	/* EVSYS_DIGFILT0_bm Predefined. */
3361	/* EVSYS_DIGFILT0_bp Predefined. */
3362	/* EVSYS_DIGFILT1_bm Predefined. */
3363	/* EVSYS_DIGFILT1_bp Predefined. */
3364	/* EVSYS_DIGFILT2_bm Predefined. */
3365	/* EVSYS_DIGFILT2_bp Predefined. */
3366
3367
3368	/* EVSYS.CH3CTRL bit masks and bit positions */
3369	/* EVSYS_DIGFILT_gm Predefined. */
3370	/* EVSYS_DIGFILT_gp Predefined. */
3371	/* EVSYS_DIGFILT0_bm Predefined. */
3372	/* EVSYS_DIGFILT0_bp Predefined. */
3373	/* EVSYS_DIGFILT1_bm Predefined. */
3374	/* EVSYS_DIGFILT1_bp Predefined. */
3375	/* EVSYS_DIGFILT2_bm Predefined. */
3376	/* EVSYS_DIGFILT2_bp Predefined. */
3377
3378
3379	/* NVM - Non Volatile Memory Controller */
3380	/* NVM.CMD bit masks and bit positions */
3381	#define NVM_CMD_gm 0xFF /* Command group mask. */
3382	#define NVM_CMD_gp 0 /* Command group position. */
3383	#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
3384	#define NVM_CMD0_bp 0 /* Command bit 0 position. */
3385	#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
3386	#define NVM_CMD1_bp 1 /* Command bit 1 position. */
3387	#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
3388	#define NVM_CMD2_bp 2 /* Command bit 2 position. */
3389	#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
3390	#define NVM_CMD3_bp 3 /* Command bit 3 position. */
3391	#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
3392	#define NVM_CMD4_bp 4 /* Command bit 4 position. */
3393	#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
3394	#define NVM_CMD5_bp 5 /* Command bit 5 position. */
3395	#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
3396	#define NVM_CMD6_bp 6 /* Command bit 6 position. */
3397	#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
3398	#define NVM_CMD7_bp 7 /* Command bit 7 position. */
3399
3400
3401	/* NVM.CTRLA bit masks and bit positions */
3402	#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
3403	#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
3404
3405
3406	/* NVM.CTRLB bit masks and bit positions */
3407	#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
3408	#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
3409
3410	#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
3411	#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
3412
3413	#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
3414	#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
3415
3416	#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
3417	#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
3418
3419
3420	/* NVM.INTCTRL bit masks and bit positions */
3421	#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
3422	#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
3423	#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
3424	#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
3425	#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
3426	#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
3427
3428	#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
3429	#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
3430	#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
3431	#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
3432	#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
3433	#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
3434
3435
3436	/* NVM.STATUS bit masks and bit positions */
3437	#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
3438	#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
3439
3440	#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
3441	#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
3442
3443	#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
3444	#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
3445
3446	#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
3447	#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
3448
3449
3450	/* NVM.LOCKBITS bit masks and bit positions */
3451	#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3452	#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3453	#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3454	#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3455	#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3456	#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3457
3458	#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3459	#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3460	#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3461	#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3462	#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3463	#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3464
3465	#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3466	#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3467	#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3468	#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3469	#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3470	#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3471
3472	#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
3473	#define NVM_LB_gp 0 /* Lock Bits group position. */
3474	#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3475	#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
3476	#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3477	#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
3478
3479
3480	/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
3481	#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3482	#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3483	#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3484	#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3485	#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3486	#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3487
3488	#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3489	#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3490	#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3491	#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3492	#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3493	#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3494
3495	#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3496	#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3497	#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3498	#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3499	#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3500	#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3501
3502	#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
3503	#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
3504	#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3505	#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
3506	#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3507	#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
3508
3509
3510	/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
3511	#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
3512	#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
3513	#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
3514	#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
3515	#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
3516	#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
3517	#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
3518	#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
3519	#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
3520	#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
3521	#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
3522	#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
3523	#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
3524	#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
3525	#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
3526	#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
3527	#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
3528	#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
3529
3530
3531	/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
3532	#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
3533	#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
3534	#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
3535	#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
3536	#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
3537	#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
3538	#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
3539	#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
3540	#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
3541	#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
3542
3543	#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
3544	#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
3545	#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
3546	#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
3547	#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
3548	#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
3549	#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
3550	#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
3551	#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
3552	#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
3553
3554
3555	/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
3556	#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
3557	#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
3558
3559	#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
3560	#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
3561
3562	#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
3563	#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
3564	#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
3565	#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
3566	#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
3567	#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
3568
3569
3570	/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
3571	#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
3572	#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
3573	#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
3574	#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
3575	#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
3576	#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
3577
3578	#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
3579	#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
3580
3581
3582	/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
3583	#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
3584	#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
3585	#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
3586	#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
3587	#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
3588	#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
3589
3590	#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
3591	#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
3592
3593	#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
3594	#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
3595	#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
3596	#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
3597	#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
3598	#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
3599	#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
3600	#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
3601
3602
3603	/* AC - Analog Comparator */
3604	/* AC.AC0CTRL bit masks and bit positions */
3605	#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
3606	#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
3607	#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
3608	#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
3609	#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
3610	#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
3611
3612	#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
3613	#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
3614	#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
3615	#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
3616	#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
3617	#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
3618
3619	#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
3620	#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
3621
3622	#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
3623	#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
3624	#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
3625	#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
3626	#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
3627	#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
3628
3629	#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
3630	#define AC_ENABLE_bp 0 /* Enable bit position. */
3631
3632
3633	/* AC.AC1CTRL bit masks and bit positions */
3634	/* AC_INTMODE_gm Predefined. */
3635	/* AC_INTMODE_gp Predefined. */
3636	/* AC_INTMODE0_bm Predefined. */
3637	/* AC_INTMODE0_bp Predefined. */
3638	/* AC_INTMODE1_bm Predefined. */
3639	/* AC_INTMODE1_bp Predefined. */
3640
3641	/* AC_INTLVL_gm Predefined. */
3642	/* AC_INTLVL_gp Predefined. */
3643	/* AC_INTLVL0_bm Predefined. */
3644	/* AC_INTLVL0_bp Predefined. */
3645	/* AC_INTLVL1_bm Predefined. */
3646	/* AC_INTLVL1_bp Predefined. */
3647
3648	/* AC_HSMODE_bm Predefined. */
3649	/* AC_HSMODE_bp Predefined. */
3650
3651	/* AC_HYSMODE_gm Predefined. */
3652	/* AC_HYSMODE_gp Predefined. */
3653	/* AC_HYSMODE0_bm Predefined. */
3654	/* AC_HYSMODE0_bp Predefined. */
3655	/* AC_HYSMODE1_bm Predefined. */
3656	/* AC_HYSMODE1_bp Predefined. */
3657
3658	/* AC_ENABLE_bm Predefined. */
3659	/* AC_ENABLE_bp Predefined. */
3660
3661
3662	/* AC.AC0MUXCTRL bit masks and bit positions */
3663	#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
3664	#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
3665	#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
3666	#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
3667	#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
3668	#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
3669	#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
3670	#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
3671
3672	#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
3673	#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
3674	#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
3675	#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
3676	#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
3677	#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
3678	#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
3679	#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
3680
3681
3682	/* AC.AC1MUXCTRL bit masks and bit positions */
3683	/* AC_MUXPOS_gm Predefined. */
3684	/* AC_MUXPOS_gp Predefined. */
3685	/* AC_MUXPOS0_bm Predefined. */
3686	/* AC_MUXPOS0_bp Predefined. */
3687	/* AC_MUXPOS1_bm Predefined. */
3688	/* AC_MUXPOS1_bp Predefined. */
3689	/* AC_MUXPOS2_bm Predefined. */
3690	/* AC_MUXPOS2_bp Predefined. */
3691
3692	/* AC_MUXNEG_gm Predefined. */
3693	/* AC_MUXNEG_gp Predefined. */
3694	/* AC_MUXNEG0_bm Predefined. */
3695	/* AC_MUXNEG0_bp Predefined. */
3696	/* AC_MUXNEG1_bm Predefined. */
3697	/* AC_MUXNEG1_bp Predefined. */
3698	/* AC_MUXNEG2_bm Predefined. */
3699	/* AC_MUXNEG2_bp Predefined. */
3700
3701
3702	/* AC.CTRLA bit masks and bit positions */
3703	#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
3704	#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
3705
3706
3707	/* AC.CTRLB bit masks and bit positions */
3708	#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
3709	#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
3710	#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
3711	#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
3712	#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
3713	#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
3714	#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
3715	#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
3716	#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
3717	#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
3718	#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
3719	#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
3720	#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
3721	#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
3722
3723
3724	/* AC.WINCTRL bit masks and bit positions */
3725	#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
3726	#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
3727
3728	#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
3729	#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
3730	#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
3731	#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
3732	#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
3733	#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
3734
3735	#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
3736	#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
3737	#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
3738	#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
3739	#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
3740	#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
3741
3742
3743	/* AC.STATUS bit masks and bit positions */
3744	#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
3745	#define AC_WSTATE_gp 6 /* Window Mode State group position. */
3746	#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
3747	#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
3748	#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
3749	#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
3750
3751	#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
3752	#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
3753
3754	#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
3755	#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
3756
3757	#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
3758	#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
3759
3760	#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
3761	#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
3762
3763	#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
3764	#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
3765
3766
3767	/* ADC - Analog/Digital Converter */
3768	/* ADC_CH.CTRL bit masks and bit positions */
3769	#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
3770	#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
3771
3772	#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
3773	#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
3774	#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
3775	#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
3776	#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
3777	#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
3778	#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
3779	#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
3780
3781	#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
3782	#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
3783	#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
3784	#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
3785	#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
3786	#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
3787
3788
3789	/* ADC_CH.MUXCTRL bit masks and bit positions */
3790	#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
3791	#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
3792	#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
3793	#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
3794	#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
3795	#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
3796	#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
3797	#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
3798	#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
3799	#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
3800
3801	#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
3802	#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
3803	#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
3804	#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
3805	#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
3806	#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
3807	#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
3808	#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
3809	#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
3810	#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
3811
3812	#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
3813	#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
3814	#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
3815	#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
3816	#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
3817	#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
3818
3819
3820	/* ADC_CH.INTCTRL bit masks and bit positions */
3821	#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
3822	#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
3823	#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
3824	#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
3825	#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
3826	#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
3827
3828	#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
3829	#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
3830	#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
3831	#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
3832	#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
3833	#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
3834
3835
3836	/* ADC_CH.INTFLAGS bit masks and bit positions */
3837	#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
3838	#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
3839
3840
3841	/* ADC.CTRLA bit masks and bit positions */
3842	#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
3843	#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
3844
3845	#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
3846	#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
3847
3848
3849	/* ADC.CTRLB bit masks and bit positions */
3850	#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
3851	#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
3852
3853	#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
3854	#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
3855
3856	#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
3857	#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
3858	#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
3859	#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
3860	#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
3861	#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
3862
3863
3864	/* ADC.REFCTRL bit masks and bit positions */
3865	#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
3866	#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
3867	#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
3868	#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
3869	#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
3870	#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
3871
3872	#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
3873	#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
3874
3875	#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
3876	#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
3877
3878
3879	/* ADC.EVCTRL bit masks and bit positions */
3880	#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
3881	#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
3882	#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
3883	#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
3884	#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
3885	#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
3886
3887	#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
3888	#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
3889	#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
3890	#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
3891	#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
3892	#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
3893	#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
3894	#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
3895
3896	#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
3897	#define ADC_EVACT_gp 0 /* Event Action Select group position. */
3898	#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
3899	#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
3900	#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
3901	#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
3902	#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
3903	#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
3904
3905
3906	/* ADC.PRESCALER bit masks and bit positions */
3907	#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
3908	#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
3909	#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
3910	#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
3911	#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
3912	#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
3913	#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
3914	#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
3915
3916
3917	/* ADC.CALCTRL bit masks and bit positions */
3918	#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
3919	#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
3920
3921
3922	/* ADC.INTFLAGS bit masks and bit positions */
3923	#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
3924	#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
3925
3926
3927	/* RTC - Real-Time Clounter */
3928	/* RTC.CTRL bit masks and bit positions */
3929	#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
3930	#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
3931	#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
3932	#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
3933	#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
3934	#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
3935	#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
3936	#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
3937
3938
3939	/* RTC.STATUS bit masks and bit positions */
3940	#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
3941	#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
3942
3943
3944	/* RTC.INTCTRL bit masks and bit positions */
3945	#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
3946	#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
3947	#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
3948	#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
3949	#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
3950	#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
3951
3952	#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
3953	#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
3954	#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
3955	#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
3956	#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
3957	#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
3958
3959
3960	/* RTC.INTFLAGS bit masks and bit positions */
3961	#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
3962	#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
3963
3964	#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
3965	#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
3966
3967
3968	/* EBI - External Bus Interface */
3969	/* EBI_CS.CTRLA bit masks and bit positions */
3970	#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
3971	#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
3972	#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
3973	#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
3974	#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
3975	#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
3976	#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
3977	#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
3978	#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
3979	#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
3980	#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
3981	#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
3982
3983	#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
3984	#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
3985	#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
3986	#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
3987	#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
3988	#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
3989
3990
3991	/* EBI_CS.CTRLB bit masks and bit positions */
3992	#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
3993	#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
3994	#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
3995	#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
3996	#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
3997	#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
3998	#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
3999	#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
4000
4001	#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
4002	#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
4003
4004	#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
4005	#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
4006
4007	#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
4008	#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
4009	#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
4010	#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
4011	#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
4012	#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
4013
4014
4015	/* EBI.CTRL bit masks and bit positions */
4016	#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
4017	#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
4018	#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
4019	#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
4020	#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
4021	#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
4022
4023	#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
4024	#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
4025	#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
4026	#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
4027	#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
4028	#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
4029
4030	#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
4031	#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
4032	#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
4033	#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
4034	#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
4035	#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
4036
4037	#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
4038	#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
4039	#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
4040	#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
4041	#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
4042	#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
4043
4044
4045	/* EBI.SDRAMCTRLA bit masks and bit positions */
4046	#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
4047	#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
4048
4049	#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
4050	#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
4051
4052	#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
4053	#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
4054	#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
4055	#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
4056	#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
4057	#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
4058
4059
4060	/* EBI.SDRAMCTRLB bit masks and bit positions */
4061	#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
4062	#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
4063	#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
4064	#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
4065	#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
4066	#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
4067
4068	#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
4069	#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
4070	#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
4071	#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
4072	#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
4073	#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
4074	#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
4075	#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
4076
4077	#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
4078	#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
4079	#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4080	#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
4081	#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4082	#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
4083	#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4084	#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
4085
4086
4087	/* EBI.SDRAMCTRLC bit masks and bit positions */
4088	#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
4089	#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
4090	#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
4091	#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
4092	#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
4093	#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
4094
4095	#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4096	#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4097	#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4098	#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4099	#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4100	#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4101	#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4102	#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4103
4104	#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
4105	#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
4106	#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
4107	#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
4108	#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
4109	#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
4110	#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
4111	#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
4112
4113
4114	/* TWI - Two-Wire Interface */
4115	/* TWI_MASTER.CTRLA bit masks and bit positions */
4116	#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4117	#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
4118	#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4119	#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4120	#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4121	#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4122
4123	#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
4124	#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
4125
4126	#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
4127	#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
4128
4129	#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
4130	#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
4131
4132
4133	/* TWI_MASTER.CTRLB bit masks and bit positions */
4134	#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
4135	#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
4136	#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
4137	#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
4138	#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
4139	#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
4140
4141	#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
4142	#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
4143
4144	#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4145	#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
4146
4147
4148	/* TWI_MASTER.CTRLC bit masks and bit positions */
4149	#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4150	#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
4151
4152	#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
4153	#define TWI_MASTER_CMD_gp 0 /* Command group position. */
4154	#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
4155	#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
4156	#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
4157	#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
4158
4159
4160	/* TWI_MASTER.STATUS bit masks and bit positions */
4161	#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
4162	#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
4163
4164	#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
4165	#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
4166
4167	#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4168	#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
4169
4170	#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4171	#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
4172
4173	#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
4174	#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
4175
4176	#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
4177	#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
4178
4179	#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
4180	#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
4181	#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
4182	#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
4183	#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
4184	#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
4185
4186
4187	/* TWI_SLAVE.CTRLA bit masks and bit positions */
4188	#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4189	#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
4190	#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4191	#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4192	#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4193	#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4194
4195	#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
4196	#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
4197
4198	#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
4199	#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
4200
4201	#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
4202	#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
4203
4204	#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
4205	#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
4206
4207	#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
4208	#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
4209
4210	#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4211	#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
4212
4213
4214	/* TWI_SLAVE.CTRLB bit masks and bit positions */
4215	#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4216	#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
4217
4218	#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
4219	#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
4220	#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
4221	#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
4222	#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
4223	#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
4224
4225
4226	/* TWI_SLAVE.STATUS bit masks and bit positions */
4227	#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
4228	#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
4229
4230	#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
4231	#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
4232
4233	#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4234	#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
4235
4236	#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4237	#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
4238
4239	#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
4240	#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
4241
4242	#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
4243	#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
4244
4245	#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
4246	#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
4247
4248	#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
4249	#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
4250
4251
4252	/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
4253	#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
4254	#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
4255	#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
4256	#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
4257	#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
4258	#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
4259	#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
4260	#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
4261	#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
4262	#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
4263	#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
4264	#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
4265	#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
4266	#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
4267	#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
4268	#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
4269
4270	#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
4271	#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
4272
4273
4274	/* TWI.CTRL bit masks and bit positions */
4275	#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
4276	#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
4277
4278	#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
4279	#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
4280
4281
4282	/* PORT - Port Configuration */
4283	/* PORTCFG.VPCTRLA bit masks and bit positions */
4284	#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
4285	#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
4286	#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
4287	#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
4288	#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
4289	#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
4290	#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
4291	#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
4292	#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
4293	#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
4294
4295	#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
4296	#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
4297	#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
4298	#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
4299	#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
4300	#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
4301	#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
4302	#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
4303	#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
4304	#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
4305
4306
4307	/* PORTCFG.VPCTRLB bit masks and bit positions */
4308	#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
4309	#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
4310	#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
4311	#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
4312	#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
4313	#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
4314	#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
4315	#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
4316	#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
4317	#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
4318
4319	#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
4320	#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
4321	#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
4322	#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
4323	#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
4324	#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
4325	#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
4326	#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
4327	#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
4328	#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
4329
4330
4331	/* PORTCFG.CLKEVOUT bit masks and bit positions */
4332	#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
4333	#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
4334	#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
4335	#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
4336	#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
4337	#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
4338
4339	#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
4340	#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
4341	#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
4342	#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
4343	#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
4344	#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
4345
4346
4347	/* VPORT.INTFLAGS bit masks and bit positions */
4348	#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4349	#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4350
4351	#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4352	#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4353
4354
4355	/* PORT.INTCTRL bit masks and bit positions */
4356	#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
4357	#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
4358	#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
4359	#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
4360	#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
4361	#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
4362
4363	#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
4364	#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
4365	#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
4366	#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
4367	#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
4368	#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
4369
4370
4371	/* PORT.INTFLAGS bit masks and bit positions */
4372	#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4373	#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4374
4375	#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4376	#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4377
4378
4379	/* PORT.PIN0CTRL bit masks and bit positions */
4380	#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
4381	#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
4382
4383	#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
4384	#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
4385
4386	#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
4387	#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
4388	#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
4389	#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
4390	#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
4391	#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
4392	#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
4393	#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
4394
4395	#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
4396	#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
4397	#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
4398	#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
4399	#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
4400	#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
4401	#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
4402	#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
4403
4404
4405	/* PORT.PIN1CTRL bit masks and bit positions */
4406	/* PORT_SRLEN_bm Predefined. */
4407	/* PORT_SRLEN_bp Predefined. */
4408
4409	/* PORT_INVEN_bm Predefined. */
4410	/* PORT_INVEN_bp Predefined. */
4411
4412	/* PORT_OPC_gm Predefined. */
4413	/* PORT_OPC_gp Predefined. */
4414	/* PORT_OPC0_bm Predefined. */
4415	/* PORT_OPC0_bp Predefined. */
4416	/* PORT_OPC1_bm Predefined. */
4417	/* PORT_OPC1_bp Predefined. */
4418	/* PORT_OPC2_bm Predefined. */
4419	/* PORT_OPC2_bp Predefined. */
4420
4421	/* PORT_ISC_gm Predefined. */
4422	/* PORT_ISC_gp Predefined. */
4423	/* PORT_ISC0_bm Predefined. */
4424	/* PORT_ISC0_bp Predefined. */
4425	/* PORT_ISC1_bm Predefined. */
4426	/* PORT_ISC1_bp Predefined. */
4427	/* PORT_ISC2_bm Predefined. */
4428	/* PORT_ISC2_bp Predefined. */
4429
4430
4431	/* PORT.PIN2CTRL bit masks and bit positions */
4432	/* PORT_SRLEN_bm Predefined. */
4433	/* PORT_SRLEN_bp Predefined. */
4434
4435	/* PORT_INVEN_bm Predefined. */
4436	/* PORT_INVEN_bp Predefined. */
4437
4438	/* PORT_OPC_gm Predefined. */
4439	/* PORT_OPC_gp Predefined. */
4440	/* PORT_OPC0_bm Predefined. */
4441	/* PORT_OPC0_bp Predefined. */
4442	/* PORT_OPC1_bm Predefined. */
4443	/* PORT_OPC1_bp Predefined. */
4444	/* PORT_OPC2_bm Predefined. */
4445	/* PORT_OPC2_bp Predefined. */
4446
4447	/* PORT_ISC_gm Predefined. */
4448	/* PORT_ISC_gp Predefined. */
4449	/* PORT_ISC0_bm Predefined. */
4450	/* PORT_ISC0_bp Predefined. */
4451	/* PORT_ISC1_bm Predefined. */
4452	/* PORT_ISC1_bp Predefined. */
4453	/* PORT_ISC2_bm Predefined. */
4454	/* PORT_ISC2_bp Predefined. */
4455
4456
4457	/* PORT.PIN3CTRL bit masks and bit positions */
4458	/* PORT_SRLEN_bm Predefined. */
4459	/* PORT_SRLEN_bp Predefined. */
4460
4461	/* PORT_INVEN_bm Predefined. */
4462	/* PORT_INVEN_bp Predefined. */
4463
4464	/* PORT_OPC_gm Predefined. */
4465	/* PORT_OPC_gp Predefined. */
4466	/* PORT_OPC0_bm Predefined. */
4467	/* PORT_OPC0_bp Predefined. */
4468	/* PORT_OPC1_bm Predefined. */
4469	/* PORT_OPC1_bp Predefined. */
4470	/* PORT_OPC2_bm Predefined. */
4471	/* PORT_OPC2_bp Predefined. */
4472
4473	/* PORT_ISC_gm Predefined. */
4474	/* PORT_ISC_gp Predefined. */
4475	/* PORT_ISC0_bm Predefined. */
4476	/* PORT_ISC0_bp Predefined. */
4477	/* PORT_ISC1_bm Predefined. */
4478	/* PORT_ISC1_bp Predefined. */
4479	/* PORT_ISC2_bm Predefined. */
4480	/* PORT_ISC2_bp Predefined. */
4481
4482
4483	/* PORT.PIN4CTRL bit masks and bit positions */
4484	/* PORT_SRLEN_bm Predefined. */
4485	/* PORT_SRLEN_bp Predefined. */
4486
4487	/* PORT_INVEN_bm Predefined. */
4488	/* PORT_INVEN_bp Predefined. */
4489
4490	/* PORT_OPC_gm Predefined. */
4491	/* PORT_OPC_gp Predefined. */
4492	/* PORT_OPC0_bm Predefined. */
4493	/* PORT_OPC0_bp Predefined. */
4494	/* PORT_OPC1_bm Predefined. */
4495	/* PORT_OPC1_bp Predefined. */
4496	/* PORT_OPC2_bm Predefined. */
4497	/* PORT_OPC2_bp Predefined. */
4498
4499	/* PORT_ISC_gm Predefined. */
4500	/* PORT_ISC_gp Predefined. */
4501	/* PORT_ISC0_bm Predefined. */
4502	/* PORT_ISC0_bp Predefined. */
4503	/* PORT_ISC1_bm Predefined. */
4504	/* PORT_ISC1_bp Predefined. */
4505	/* PORT_ISC2_bm Predefined. */
4506	/* PORT_ISC2_bp Predefined. */
4507
4508
4509	/* PORT.PIN5CTRL bit masks and bit positions */
4510	/* PORT_SRLEN_bm Predefined. */
4511	/* PORT_SRLEN_bp Predefined. */
4512
4513	/* PORT_INVEN_bm Predefined. */
4514	/* PORT_INVEN_bp Predefined. */
4515
4516	/* PORT_OPC_gm Predefined. */
4517	/* PORT_OPC_gp Predefined. */
4518	/* PORT_OPC0_bm Predefined. */
4519	/* PORT_OPC0_bp Predefined. */
4520	/* PORT_OPC1_bm Predefined. */
4521	/* PORT_OPC1_bp Predefined. */
4522	/* PORT_OPC2_bm Predefined. */
4523	/* PORT_OPC2_bp Predefined. */
4524
4525	/* PORT_ISC_gm Predefined. */
4526	/* PORT_ISC_gp Predefined. */
4527	/* PORT_ISC0_bm Predefined. */
4528	/* PORT_ISC0_bp Predefined. */
4529	/* PORT_ISC1_bm Predefined. */
4530	/* PORT_ISC1_bp Predefined. */
4531	/* PORT_ISC2_bm Predefined. */
4532	/* PORT_ISC2_bp Predefined. */
4533
4534
4535	/* PORT.PIN6CTRL bit masks and bit positions */
4536	/* PORT_SRLEN_bm Predefined. */
4537	/* PORT_SRLEN_bp Predefined. */
4538
4539	/* PORT_INVEN_bm Predefined. */
4540	/* PORT_INVEN_bp Predefined. */
4541
4542	/* PORT_OPC_gm Predefined. */
4543	/* PORT_OPC_gp Predefined. */
4544	/* PORT_OPC0_bm Predefined. */
4545	/* PORT_OPC0_bp Predefined. */
4546	/* PORT_OPC1_bm Predefined. */
4547	/* PORT_OPC1_bp Predefined. */
4548	/* PORT_OPC2_bm Predefined. */
4549	/* PORT_OPC2_bp Predefined. */
4550
4551	/* PORT_ISC_gm Predefined. */
4552	/* PORT_ISC_gp Predefined. */
4553	/* PORT_ISC0_bm Predefined. */
4554	/* PORT_ISC0_bp Predefined. */
4555	/* PORT_ISC1_bm Predefined. */
4556	/* PORT_ISC1_bp Predefined. */
4557	/* PORT_ISC2_bm Predefined. */
4558	/* PORT_ISC2_bp Predefined. */
4559
4560
4561	/* PORT.PIN7CTRL bit masks and bit positions */
4562	/* PORT_SRLEN_bm Predefined. */
4563	/* PORT_SRLEN_bp Predefined. */
4564
4565	/* PORT_INVEN_bm Predefined. */
4566	/* PORT_INVEN_bp Predefined. */
4567
4568	/* PORT_OPC_gm Predefined. */
4569	/* PORT_OPC_gp Predefined. */
4570	/* PORT_OPC0_bm Predefined. */
4571	/* PORT_OPC0_bp Predefined. */
4572	/* PORT_OPC1_bm Predefined. */
4573	/* PORT_OPC1_bp Predefined. */
4574	/* PORT_OPC2_bm Predefined. */
4575	/* PORT_OPC2_bp Predefined. */
4576
4577	/* PORT_ISC_gm Predefined. */
4578	/* PORT_ISC_gp Predefined. */
4579	/* PORT_ISC0_bm Predefined. */
4580	/* PORT_ISC0_bp Predefined. */
4581	/* PORT_ISC1_bm Predefined. */
4582	/* PORT_ISC1_bp Predefined. */
4583	/* PORT_ISC2_bm Predefined. */
4584	/* PORT_ISC2_bp Predefined. */
4585
4586
4587	/* TC - 16-bit Timer/Counter With PWM */
4588	/* TC0.CTRLA bit masks and bit positions */
4589	#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4590	#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
4591	#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4592	#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4593	#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4594	#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4595	#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4596	#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4597	#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4598	#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4599
4600
4601	/* TC0.CTRLB bit masks and bit positions */
4602	#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
4603	#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
4604
4605	#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
4606	#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
4607
4608	#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4609	#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4610
4611	#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4612	#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4613
4614	#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4615	#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
4616	#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4617	#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4618	#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4619	#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4620	#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4621	#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4622
4623
4624	/* TC0.CTRLC bit masks and bit positions */
4625	#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
4626	#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
4627
4628	#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
4629	#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
4630
4631	#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4632	#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
4633
4634	#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4635	#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
4636
4637
4638	/* TC0.CTRLD bit masks and bit positions */
4639	#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
4640	#define TC0_EVACT_gp 5 /* Event Action group position. */
4641	#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4642	#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
4643	#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4644	#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
4645	#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4646	#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
4647
4648	#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
4649	#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
4650
4651	#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
4652	#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
4653	#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4654	#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4655	#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4656	#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4657	#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4658	#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4659	#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4660	#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4661
4662
4663	/* TC0.CTRLE bit masks and bit positions */
4664	#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
4665	#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
4666
4667	#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4668	#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
4669
4670
4671	/* TC0.INTCTRLA bit masks and bit positions */
4672	#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4673	#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4674	#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4675	#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4676	#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4677	#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4678
4679	#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4680	#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4681	#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4682	#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4683	#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4684	#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4685
4686
4687	/* TC0.INTCTRLB bit masks and bit positions */
4688	#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
4689	#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
4690	#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
4691	#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
4692	#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
4693	#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
4694
4695	#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
4696	#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
4697	#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
4698	#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
4699	#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
4700	#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
4701
4702	#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4703	#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4704	#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4705	#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4706	#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4707	#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4708
4709	#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4710	#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4711	#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4712	#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4713	#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4714	#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4715
4716
4717	/* TC0.CTRLFCLR bit masks and bit positions */
4718	#define TC0_CMD_gm 0x0C /* Command group mask. */
4719	#define TC0_CMD_gp 2 /* Command group position. */
4720	#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
4721	#define TC0_CMD0_bp 2 /* Command bit 0 position. */
4722	#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
4723	#define TC0_CMD1_bp 3 /* Command bit 1 position. */
4724
4725	#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
4726	#define TC0_LUPD_bp 1 /* Lock Update bit position. */
4727
4728	#define TC0_DIR_bm 0x01 /* Direction bit mask. */
4729	#define TC0_DIR_bp 0 /* Direction bit position. */
4730
4731
4732	/* TC0.CTRLFSET bit masks and bit positions */
4733	/* TC0_CMD_gm Predefined. */
4734	/* TC0_CMD_gp Predefined. */
4735	/* TC0_CMD0_bm Predefined. */
4736	/* TC0_CMD0_bp Predefined. */
4737	/* TC0_CMD1_bm Predefined. */
4738	/* TC0_CMD1_bp Predefined. */
4739
4740	/* TC0_LUPD_bm Predefined. */
4741	/* TC0_LUPD_bp Predefined. */
4742
4743	/* TC0_DIR_bm Predefined. */
4744	/* TC0_DIR_bp Predefined. */
4745
4746
4747	/* TC0.CTRLGCLR bit masks and bit positions */
4748	#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
4749	#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
4750
4751	#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
4752	#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
4753
4754	#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
4755	#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
4756
4757	#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
4758	#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
4759
4760	#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
4761	#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
4762
4763
4764	/* TC0.CTRLGSET bit masks and bit positions */
4765	/* TC0_CCDBV_bm Predefined. */
4766	/* TC0_CCDBV_bp Predefined. */
4767
4768	/* TC0_CCCBV_bm Predefined. */
4769	/* TC0_CCCBV_bp Predefined. */
4770
4771	/* TC0_CCBBV_bm Predefined. */
4772	/* TC0_CCBBV_bp Predefined. */
4773
4774	/* TC0_CCABV_bm Predefined. */
4775	/* TC0_CCABV_bp Predefined. */
4776
4777	/* TC0_PERBV_bm Predefined. */
4778	/* TC0_PERBV_bp Predefined. */
4779
4780
4781	/* TC0.INTFLAGS bit masks and bit positions */
4782	#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
4783	#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
4784
4785	#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
4786	#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
4787
4788	#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
4789	#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
4790
4791	#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
4792	#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
4793
4794	#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
4795	#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
4796
4797	#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4798	#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4799
4800
4801	/* TC1.CTRLA bit masks and bit positions */
4802	#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4803	#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
4804	#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4805	#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4806	#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4807	#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4808	#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4809	#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4810	#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4811	#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4812
4813
4814	/* TC1.CTRLB bit masks and bit positions */
4815	#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4816	#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4817
4818	#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4819	#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4820
4821	#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4822	#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
4823	#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4824	#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4825	#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4826	#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4827	#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4828	#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4829
4830
4831	/* TC1.CTRLC bit masks and bit positions */
4832	#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4833	#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
4834
4835	#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4836	#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
4837
4838
4839	/* TC1.CTRLD bit masks and bit positions */
4840	#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
4841	#define TC1_EVACT_gp 5 /* Event Action group position. */
4842	#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4843	#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
4844	#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4845	#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
4846	#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4847	#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
4848
4849	#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
4850	#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
4851
4852	#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
4853	#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
4854	#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4855	#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4856	#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4857	#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4858	#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4859	#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4860	#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4861	#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4862
4863
4864	/* TC1.CTRLE bit masks and bit positions */
4865	#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */
4866	#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */
4867
4868	#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4869	#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
4870
4871
4872	/* TC1.INTCTRLA bit masks and bit positions */
4873	#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4874	#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4875	#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4876	#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4877	#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4878	#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4879
4880	#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4881	#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4882	#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4883	#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4884	#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4885	#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4886
4887
4888	/* TC1.INTCTRLB bit masks and bit positions */
4889	#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4890	#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4891	#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4892	#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4893	#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4894	#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4895
4896	#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4897	#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4898	#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4899	#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4900	#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4901	#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4902
4903
4904	/* TC1.CTRLFCLR bit masks and bit positions */
4905	#define TC1_CMD_gm 0x0C /* Command group mask. */
4906	#define TC1_CMD_gp 2 /* Command group position. */
4907	#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
4908	#define TC1_CMD0_bp 2 /* Command bit 0 position. */
4909	#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
4910	#define TC1_CMD1_bp 3 /* Command bit 1 position. */
4911
4912	#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
4913	#define TC1_LUPD_bp 1 /* Lock Update bit position. */
4914
4915	#define TC1_DIR_bm 0x01 /* Direction bit mask. */
4916	#define TC1_DIR_bp 0 /* Direction bit position. */
4917
4918
4919	/* TC1.CTRLFSET bit masks and bit positions */
4920	/* TC1_CMD_gm Predefined. */
4921	/* TC1_CMD_gp Predefined. */
4922	/* TC1_CMD0_bm Predefined. */
4923	/* TC1_CMD0_bp Predefined. */
4924	/* TC1_CMD1_bm Predefined. */
4925	/* TC1_CMD1_bp Predefined. */
4926
4927	/* TC1_LUPD_bm Predefined. */
4928	/* TC1_LUPD_bp Predefined. */
4929
4930	/* TC1_DIR_bm Predefined. */
4931	/* TC1_DIR_bp Predefined. */
4932
4933
4934	/* TC1.CTRLGCLR bit masks and bit positions */
4935	#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
4936	#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
4937
4938	#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
4939	#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
4940
4941	#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
4942	#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
4943
4944
4945	/* TC1.CTRLGSET bit masks and bit positions */
4946	/* TC1_CCBBV_bm Predefined. */
4947	/* TC1_CCBBV_bp Predefined. */
4948
4949	/* TC1_CCABV_bm Predefined. */
4950	/* TC1_CCABV_bp Predefined. */
4951
4952	/* TC1_PERBV_bm Predefined. */
4953	/* TC1_PERBV_bp Predefined. */
4954
4955
4956	/* TC1.INTFLAGS bit masks and bit positions */
4957	#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
4958	#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
4959
4960	#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
4961	#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
4962
4963	#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
4964	#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
4965
4966	#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4967	#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4968
4969
4970	/* AWEX.CTRL bit masks and bit positions */
4971	#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
4972	#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
4973
4974	#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
4975	#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
4976
4977	#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
4978	#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
4979
4980	#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
4981	#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
4982
4983	#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
4984	#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
4985
4986	#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
4987	#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
4988
4989
4990	/* AWEX.FDCTRL bit masks and bit positions */
4991	#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
4992	#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
4993
4994	#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
4995	#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
4996
4997	#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
4998	#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
4999	#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
5000	#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
5001	#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
5002	#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
5003
5004
5005	/* AWEX.STATUS bit masks and bit positions */
5006	#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
5007	#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
5008
5009	#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
5010	#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
5011
5012	#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
5013	#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
5014
5015
5016	/* HIRES.CTRL bit masks and bit positions */
5017	#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
5018	#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
5019	#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
5020	#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
5021	#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
5022	#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
5023
5024
5025	/* USART - Universal Asynchronous Receiver-Transmitter */
5026	/* USART.STATUS bit masks and bit positions */
5027	#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
5028	#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
5029
5030	#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
5031	#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
5032
5033	#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
5034	#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
5035
5036	#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
5037	#define USART_FERR_bp 4 /* Frame Error bit position. */
5038
5039	#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
5040	#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
5041
5042	#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
5043	#define USART_PERR_bp 2 /* Parity Error bit position. */
5044
5045	#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
5046	#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
5047
5048
5049	/* USART.CTRLA bit masks and bit positions */
5050	#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
5051	#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
5052	#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
5053	#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
5054	#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
5055	#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
5056
5057	#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
5058	#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
5059	#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
5060	#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
5061	#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
5062	#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
5063
5064	#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
5065	#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
5066	#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
5067	#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
5068	#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
5069	#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
5070
5071
5072	/* USART.CTRLB bit masks and bit positions */
5073	#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
5074	#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
5075
5076	#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
5077	#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
5078
5079	#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
5080	#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
5081
5082	#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
5083	#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
5084
5085	#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
5086	#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
5087
5088
5089	/* USART.CTRLC bit masks and bit positions */
5090	#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
5091	#define USART_CMODE_gp 6 /* Communication Mode group position. */
5092	#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
5093	#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
5094	#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
5095	#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
5096
5097	#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
5098	#define USART_PMODE_gp 4 /* Parity Mode group position. */
5099	#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
5100	#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
5101	#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
5102	#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
5103
5104	#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
5105	#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
5106
5107	#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
5108	#define USART_CHSIZE_gp 0 /* Character Size group position. */
5109	#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
5110	#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
5111	#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
5112	#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
5113	#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
5114	#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
5115
5116
5117	/* USART.BAUDCTRLA bit masks and bit positions */
5118	#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
5119	#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
5120	#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5121	#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
5122	#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5123	#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
5124	#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5125	#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
5126	#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5127	#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
5128	#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5129	#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
5130	#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5131	#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
5132	#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5133	#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
5134	#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5135	#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
5136
5137
5138	/* USART.BAUDCTRLB bit masks and bit positions */
5139	#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
5140	#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
5141	#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
5142	#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
5143	#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
5144	#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
5145	#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
5146	#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
5147	#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
5148	#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
5149
5150	/* USART_BSEL_gm Predefined. */
5151	/* USART_BSEL_gp Predefined. */
5152	/* USART_BSEL0_bm Predefined. */
5153	/* USART_BSEL0_bp Predefined. */
5154	/* USART_BSEL1_bm Predefined. */
5155	/* USART_BSEL1_bp Predefined. */
5156	/* USART_BSEL2_bm Predefined. */
5157	/* USART_BSEL2_bp Predefined. */
5158	/* USART_BSEL3_bm Predefined. */
5159	/* USART_BSEL3_bp Predefined. */
5160
5161
5162	/* SPI - Serial Peripheral Interface */
5163	/* SPI.CTRL bit masks and bit positions */
5164	#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
5165	#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
5166
5167	#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
5168	#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
5169
5170	#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
5171	#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
5172
5173	#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
5174	#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
5175
5176	#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
5177	#define SPI_MODE_gp 2 /* SPI Mode group position. */
5178	#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
5179	#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
5180	#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
5181	#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
5182
5183	#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
5184	#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
5185	#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
5186	#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
5187	#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
5188	#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
5189
5190
5191	/* SPI.INTCTRL bit masks and bit positions */
5192	#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
5193	#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
5194	#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
5195	#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
5196	#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
5197	#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
5198
5199
5200	/* SPI.STATUS bit masks and bit positions */
5201	#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
5202	#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
5203
5204	#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
5205	#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
5206
5207
5208	/* IRCOM - IR Communication Module */
5209	/* IRCOM.CTRL bit masks and bit positions */
5210	#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
5211	#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
5212	#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
5213	#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
5214	#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
5215	#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
5216	#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
5217	#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
5218	#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
5219	#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
5220
5221
5222
5223	// Generic Port Pins
5224
5225	#define PIN0_bm 0x01
5226	#define PIN0_bp 0
5227	#define PIN1_bm 0x02
5228	#define PIN1_bp 1
5229	#define PIN2_bm 0x04
5230	#define PIN2_bp 2
5231	#define PIN3_bm 0x08
5232	#define PIN3_bp 3
5233	#define PIN4_bm 0x10
5234	#define PIN4_bp 4
5235	#define PIN5_bm 0x20
5236	#define PIN5_bp 5
5237	#define PIN6_bm 0x40
5238	#define PIN6_bp 6
5239	#define PIN7_bm 0x80
5240	#define PIN7_bp 7
5241
5242
5243	/* ========== Interrupt Vector Definitions ========== */
5244	/* Vector 0 is the reset vector */
5245
5246	/* OSC interrupt vectors */
5247	#define OSC_XOSCF_vect_num 1
5248	#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
5249
5250	/* PORTC interrupt vectors */
5251	#define PORTC_INT0_vect_num 2
5252	#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
5253	#define PORTC_INT1_vect_num 3
5254	#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
5255
5256	/* PORTR interrupt vectors */
5257	#define PORTR_INT0_vect_num 4
5258	#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
5259	#define PORTR_INT1_vect_num 5
5260	#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
5261
5262	/* RTC interrupt vectors */
5263	#define RTC_OVF_vect_num 10
5264	#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
5265	#define RTC_COMP_vect_num 11
5266	#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
5267
5268	/* TWIC interrupt vectors */
5269	#define TWIC_TWIS_vect_num 12
5270	#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
5271	#define TWIC_TWIM_vect_num 13
5272	#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
5273
5274	/* TCC0 interrupt vectors */
5275	#define TCC0_OVF_vect_num 14
5276	#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
5277	#define TCC0_ERR_vect_num 15
5278	#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
5279	#define TCC0_CCA_vect_num 16
5280	#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
5281	#define TCC0_CCB_vect_num 17
5282	#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
5283	#define TCC0_CCC_vect_num 18
5284	#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
5285	#define TCC0_CCD_vect_num 19
5286	#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
5287
5288	/* TCC1 interrupt vectors */
5289	#define TCC1_OVF_vect_num 20
5290	#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
5291	#define TCC1_ERR_vect_num 21
5292	#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
5293	#define TCC1_CCA_vect_num 22
5294	#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
5295	#define TCC1_CCB_vect_num 23
5296	#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
5297
5298	/* SPIC interrupt vectors */
5299	#define SPIC_INT_vect_num 24
5300	#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
5301
5302	/* USARTC0 interrupt vectors */
5303	#define USARTC0_RXC_vect_num 25
5304	#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
5305	#define USARTC0_DRE_vect_num 26
5306	#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
5307	#define USARTC0_TXC_vect_num 27
5308	#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
5309
5310	/* NVM interrupt vectors */
5311	#define NVM_EE_vect_num 32
5312	#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
5313	#define NVM_SPM_vect_num 33
5314	#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
5315
5316	/* PORTB interrupt vectors */
5317	#define PORTB_INT0_vect_num 34
5318	#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
5319	#define PORTB_INT1_vect_num 35
5320	#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
5321
5322	/* PORTE interrupt vectors */
5323	#define PORTE_INT0_vect_num 43
5324	#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
5325	#define PORTE_INT1_vect_num 44
5326	#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
5327
5328	/* TCE0 interrupt vectors */
5329	#define TCE0_OVF_vect_num 47
5330	#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
5331	#define TCE0_ERR_vect_num 48
5332	#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
5333	#define TCE0_CCA_vect_num 49
5334	#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
5335	#define TCE0_CCB_vect_num 50
5336	#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
5337	#define TCE0_CCC_vect_num 51
5338	#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
5339	#define TCE0_CCD_vect_num 52
5340	#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
5341
5342	/* PORTD interrupt vectors */
5343	#define PORTD_INT0_vect_num 64
5344	#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
5345	#define PORTD_INT1_vect_num 65
5346	#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
5347
5348	/* PORTA interrupt vectors */
5349	#define PORTA_INT0_vect_num 66
5350	#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
5351	#define PORTA_INT1_vect_num 67
5352	#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
5353
5354	/* ACA interrupt vectors */
5355	#define ACA_AC0_vect_num 68
5356	#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
5357	#define ACA_AC1_vect_num 69
5358	#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
5359	#define ACA_ACW_vect_num 70
5360	#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
5361
5362	/* ADCA interrupt vectors */
5363	#define ADCA_CH0_vect_num 71
5364	#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
5365
5366	/* TCD0 interrupt vectors */
5367	#define TCD0_OVF_vect_num 77
5368	#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
5369	#define TCD0_ERR_vect_num 78
5370	#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
5371	#define TCD0_CCA_vect_num 79
5372	#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
5373	#define TCD0_CCB_vect_num 80
5374	#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
5375	#define TCD0_CCC_vect_num 81
5376	#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
5377	#define TCD0_CCD_vect_num 82
5378	#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
5379
5380	/* SPID interrupt vectors */
5381	#define SPID_INT_vect_num 87
5382	#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
5383
5384	/* USARTD0 interrupt vectors */
5385	#define USARTD0_RXC_vect_num 88
5386	#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
5387	#define USARTD0_DRE_vect_num 89
5388	#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
5389	#define USARTD0_TXC_vect_num 90
5390	#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
5391
5392
5393	#define _VECTOR_SIZE 4 /* Size of individual vector. */
5394	#define _VECTORS_SIZE (91 * _VECTOR_SIZE)
5395
5396
5397	/* ========== Constants ========== */
5398
5399	#define PROGMEM_START (0x0000)
5400	#define PROGMEM_SIZE (36864)
5401	#define PROGMEM_PAGE_SIZE (256)
5402	#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
5403
5404	#define APP_SECTION_START (0x0000)
5405	#define APP_SECTION_SIZE (32768)
5406	#define APP_SECTION_PAGE_SIZE (256)
5407	#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
5408
5409	#define APPTABLE_SECTION_START (0x7000)
5410	#define APPTABLE_SECTION_SIZE (4096)
5411	#define APPTABLE_SECTION_PAGE_SIZE (256)
5412	#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5413
5414	#define BOOT_SECTION_START (0x8000)
5415	#define BOOT_SECTION_SIZE (4096)
5416	#define BOOT_SECTION_PAGE_SIZE (256)
5417	#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5418
5419	#define DATAMEM_START (0x0000)
5420	#define DATAMEM_SIZE (12288)
5421	#define DATAMEM_PAGE_SIZE (0)
5422	#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
5423
5424	#define IO_START (0x0000)
5425	#define IO_SIZE (4096)
5426	#define IO_PAGE_SIZE (0)
5427	#define IO_END (IO_START + IO_SIZE - 1)
5428
5429	#define MAPPED_EEPROM_START (0x1000)
5430	#define MAPPED_EEPROM_SIZE (1024)
5431	#define MAPPED_EEPROM_PAGE_SIZE (0)
5432	#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5433
5434	#define INTERNAL_SRAM_START (0x2000)
5435	#define INTERNAL_SRAM_SIZE (4096)
5436	#define INTERNAL_SRAM_PAGE_SIZE (0)
5437	#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5438
5439	#define EEPROM_START (0x0000)
5440	#define EEPROM_SIZE (1024)
5441	#define EEPROM_PAGE_SIZE (32)
5442	#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
5443
5444	#define FUSE_START (0x0000)
5445	#define FUSE_SIZE (6)
5446	#define FUSE_PAGE_SIZE (0)
5447	#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
5448
5449	#define LOCKBIT_START (0x0000)
5450	#define LOCKBIT_SIZE (1)
5451	#define LOCKBIT_PAGE_SIZE (0)
5452	#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
5453
5454	#define SIGNATURES_START (0x0000)
5455	#define SIGNATURES_SIZE (3)
5456	#define SIGNATURES_PAGE_SIZE (0)
5457	#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
5458
5459	#define USER_SIGNATURES_START (0x0000)
5460	#define USER_SIGNATURES_SIZE (256)
5461	#define USER_SIGNATURES_PAGE_SIZE (0)
5462	#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5463
5464	#define PROD_SIGNATURES_START (0x0000)
5465	#define PROD_SIGNATURES_SIZE (52)
5466	#define PROD_SIGNATURES_PAGE_SIZE (0)
5467	#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5468
5469	#define FLASHEND PROGMEM_END
5470	#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5471	#define RAMSTART INTERNAL_SRAM_START
5472	#define RAMSIZE INTERNAL_SRAM_SIZE
5473	#define RAMEND INTERNAL_SRAM_END
5474	#define XRAMSTART EXTERNAL_SRAM_START
5475	#define XRAMSIZE EXTERNAL_SRAM_SIZE
5476	#define XRAMEND INTERNAL_SRAM_END
5477	#define E2END EEPROM_END
5478	#define E2PAGESIZE EEPROM_PAGE_SIZE
5479
5480
5481	/* ========== Fuses ========== */
5482	#define FUSE_MEMORY_SIZE 6
5483
5484	/* Fuse Byte 0 */
5485	#define FUSE_USERID0 ~_BV(0) /* User ID Bit 0 */
5486	#define FUSE_USERID1 ~_BV(1) /* User ID Bit 1 */
5487	#define FUSE_USERID2 ~_BV(2) /* User ID Bit 2 */
5488	#define FUSE_USERID3 ~_BV(3) /* User ID Bit 3 */
5489	#define FUSE_USERID4 ~_BV(4) /* User ID Bit 4 */
5490	#define FUSE_USERID5 ~_BV(5) /* User ID Bit 5 */
5491	#define FUSE_USERID6 ~_BV(6) /* User ID Bit 6 */
5492	#define FUSE_USERID7 ~_BV(7) /* User ID Bit 7 */
5493	#define FUSE0_DEFAULT (0xFF)
5494
5495	/* Fuse Byte 1 */
5496	#define FUSE_WDP0 ~_BV(0) /* Watchdog Timeout Period Bit 0 */
5497	#define FUSE_WDP1 ~_BV(1) /* Watchdog Timeout Period Bit 1 */
5498	#define FUSE_WDP2 ~_BV(2) /* Watchdog Timeout Period Bit 2 */
5499	#define FUSE_WDP3 ~_BV(3) /* Watchdog Timeout Period Bit 3 */
5500	#define FUSE_WDWP0 ~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
5501	#define FUSE_WDWP1 ~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
5502	#define FUSE_WDWP2 ~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
5503	#define FUSE_WDWP3 ~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
5504	#define FUSE1_DEFAULT (0xFF)
5505
5506	/* Fuse Byte 2 */
5507	#define FUSE_BODPD0 ~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
5508	#define FUSE_BODPD1 ~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
5509	#define FUSE_BOOTRST ~_BV(6) /* Boot Loader Section Reset Vector */
5510	#define FUSE_DVSDON ~_BV(7) /* Spike Detector Enable */
5511	#define FUSE2_DEFAULT (0xFF)
5512
5513	/* Fuse Byte 3 Reserved */
5514
5515	/* Fuse Byte 4 */
5516	#define FUSE_WDLOCK ~_BV(1) /* Watchdog Timer Lock */
5517	#define FUSE_SUT0 ~_BV(2) /* Start-up Time Bit 0 */
5518	#define FUSE_SUT1 ~_BV(3) /* Start-up Time Bit 1 */
5519	#define FUSE4_DEFAULT (0xFF)
5520
5521	/* Fuse Byte 5 */
5522	#define FUSE_BODLVL0 ~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
5523	#define FUSE_BODLVL1 ~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
5524	#define FUSE_BODLVL2 ~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
5525	#define FUSE_EESAVE ~_BV(3) /* Preserve EEPROM Through Chip Erase */
5526	#define FUSE_BODACT0 ~_BV(4) /* BOD Operation in Active Mode Bit 0 */
5527	#define FUSE_BODACT1 ~_BV(5) /* BOD Operation in Active Mode Bit 1 */
5528	#define FUSE5_DEFAULT (0xFF)
5529
5530
5531	/* ========== Lock Bits ========== */
5532	#define __LOCK_BITS_EXIST
5533	#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5534	#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5535	#define __BOOT_LOCK_BOOT_BITS_EXIST
5536
5537
5538	/* ========== Signature ========== */
5539	#define SIGNATURE_0 0x1E
5540	#define SIGNATURE_1 0x95
5541	#define SIGNATURE_2 0x42
5542
5543
5544	#endif /* _AVR_ATxmega32D4_H_ */
5545

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