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iox256d3.h @ 9b4422a2

4.115

Last change on this file since 9b4422a2 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

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1	/* Copyright (c) 2009 Atmel Corporation
2	All rights reserved.
3
4	Redistribution and use in source and binary forms, with or without
5	modification, are permitted provided that the following conditions are met:
6
7	* Redistributions of source code must retain the above copyright
8	notice, this list of conditions and the following disclaimer.
9
10	* Redistributions in binary form must reproduce the above copyright
11	notice, this list of conditions and the following disclaimer in
12	the documentation and/or other materials provided with the
13	distribution.
14
15	* Neither the name of the copyright holders nor the names of
16	contributors may be used to endorse or promote products derived
17	from this software without specific prior written permission.
18
19	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20	AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21	IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22	ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23	LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24	CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25	SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26	INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27	CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29	POSSIBILITY OF SUCH DAMAGE. */
30
31
32	/* avr/iox256d3.h - definitions for ATxmega256D3 */
33
34	/* This file should only be included from <avr/io.h>, never directly. */
35
36	#ifndef _AVR_IO_H_
37	# error "Include <avr/io.h> instead of this file."
38	#endif
39
40	#ifndef _AVR_IOXXX_H_
41	# define _AVR_IOXXX_H_ "iox256d3.h"
42	#else
43	# error "Attempt to include more than one <avr/ioXXX.h> file."
44	#endif
45
46
47	#ifndef _AVR_ATxmega256D3_H_
48	#define _AVR_ATxmega256D3_H_ 1
49
50
51	/* Ungrouped common registers */
52	#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
53	#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
54	#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
55	#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
56	#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
57	#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
58	#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
59	#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
60	#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
61	#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
62	#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
63	#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
64	#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
65	#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
66	#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
67	#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
68
69	#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
70	#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
71	#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
72	#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
73	#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
74	#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
75	#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
76	#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
77	#define SREG _SFR_MEM8(0x003F) /* Status Register */
78
79
80	/* C Language Only */
81	#if !defined (__ASSEMBLER__)
82
83	#include <stdint.h>
84
85	typedef volatile uint8_t register8_t;
86	typedef volatile uint16_t register16_t;
87	typedef volatile uint32_t register32_t;
88
89
90	#ifdef _WORDREGISTER
91	#undef _WORDREGISTER
92	#endif
93	#define _WORDREGISTER(regname) \
94	__extension__ union \
95	{ \
96	register16_t regname; \
97	struct \
98	{ \
99	register8_t regname ## L; \
100	register8_t regname ## H; \
101	}; \
102	}
103
104	#ifdef _DWORDREGISTER
105	#undef _DWORDREGISTER
106	#endif
107	#define _DWORDREGISTER(regname) \
108	__extension__ union \
109	{ \
110	register32_t regname; \
111	struct \
112	{ \
113	register8_t regname ## 0; \
114	register8_t regname ## 1; \
115	register8_t regname ## 2; \
116	register8_t regname ## 3; \
117	}; \
118	}
119
120
121	/*
122	==========================================================================
123	IO Module Structures
124	==========================================================================
125	*/
126
127
128	/*
129	--------------------------------------------------------------------------
130	XOCD - On-Chip Debug System
131	--------------------------------------------------------------------------
132	*/
133
134	/* On-Chip Debug System */
135	typedef struct OCD_struct
136	{
137	register8_t OCDR0; /* OCD Register 0 */
138	register8_t OCDR1; /* OCD Register 1 */
139	} OCD_t;
140
141
142	/* CCP signatures */
143	typedef enum CCP_enum
144	{
145	CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
146	CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
147	} CCP_t;
148
149
150	/*
151	--------------------------------------------------------------------------
152	CLK - Clock System
153	--------------------------------------------------------------------------
154	*/
155
156	/* Clock System */
157	typedef struct CLK_struct
158	{
159	register8_t CTRL; /* Control Register */
160	register8_t PSCTRL; /* Prescaler Control Register */
161	register8_t LOCK; /* Lock register */
162	register8_t RTCCTRL; /* RTC Control Register */
163	} CLK_t;
164
165	/* System Clock Selection */
166	typedef enum CLK_SCLKSEL_enum
167	{
168	CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
169	CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
170	CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
171	CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
172	CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
173	} CLK_SCLKSEL_t;
174
175	/* Prescaler A Division Factor */
176	typedef enum CLK_PSADIV_enum
177	{
178	CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
179	CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
180	CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
181	CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
182	CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
183	CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
184	CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
185	CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
186	CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
187	CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
188	} CLK_PSADIV_t;
189
190	/* Prescaler B and C Division Factor */
191	typedef enum CLK_PSBCDIV_enum
192	{
193	CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
194	CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
195	CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
196	CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
197	} CLK_PSBCDIV_t;
198
199	/* RTC Clock Source */
200	typedef enum CLK_RTCSRC_enum
201	{
202	CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
203	CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
204	CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
205	CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
206	} CLK_RTCSRC_t;
207
208
209	/*
210	--------------------------------------------------------------------------
211	SLEEP - Sleep Controller
212	--------------------------------------------------------------------------
213	*/
214
215	/* Sleep Controller */
216	typedef struct SLEEP_struct
217	{
218	register8_t CTRL; /* Control Register */
219	} SLEEP_t;
220
221	/* Sleep Mode */
222	typedef enum SLEEP_SMODE_enum
223	{
224	SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
225	SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
226	SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
227	SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
228	SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
229	} SLEEP_SMODE_t;
230
231
232	/*
233	--------------------------------------------------------------------------
234	OSC - Oscillator
235	--------------------------------------------------------------------------
236	*/
237
238	/* Oscillator */
239	typedef struct OSC_struct
240	{
241	register8_t CTRL; /* Control Register */
242	register8_t STATUS; /* Status Register */
243	register8_t XOSCCTRL; /* External Oscillator Control Register */
244	register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
245	register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
246	register8_t PLLCTRL; /* PLL Control REgister */
247	register8_t DFLLCTRL; /* DFLL Control Register */
248	} OSC_t;
249
250	/* Oscillator Frequency Range */
251	typedef enum OSC_FRQRANGE_enum
252	{
253	OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
254	OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
255	OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
256	OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
257	} OSC_FRQRANGE_t;
258
259	/* External Oscillator Selection and Startup Time */
260	typedef enum OSC_XOSCSEL_enum
261	{
262	OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
263	OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
264	OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
265	OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
266	OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
267	} OSC_XOSCSEL_t;
268
269	/* PLL Clock Source */
270	typedef enum OSC_PLLSRC_enum
271	{
272	OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
273	OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
274	OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
275	} OSC_PLLSRC_t;
276
277
278	/*
279	--------------------------------------------------------------------------
280	DFLL - DFLL
281	--------------------------------------------------------------------------
282	*/
283
284	/* DFLL */
285	typedef struct DFLL_struct
286	{
287	register8_t CTRL; /* Control Register */
288	register8_t reserved_0x01;
289	register8_t CALA; /* Calibration Register A */
290	register8_t CALB; /* Calibration Register B */
291	register8_t COMP0; /* Oscillator Compare Register 0 */
292	register8_t COMP1; /* Oscillator Compare Register 1 */
293	register8_t COMP2; /* Oscillator Compare Register 2 */
294	register8_t reserved_0x07;
295	} DFLL_t;
296
297
298	/*
299	--------------------------------------------------------------------------
300	RST - Reset
301	--------------------------------------------------------------------------
302	*/
303
304	/* Reset */
305	typedef struct RST_struct
306	{
307	register8_t STATUS; /* Status Register */
308	register8_t CTRL; /* Control Register */
309	} RST_t;
310
311
312	/*
313	--------------------------------------------------------------------------
314	WDT - Watch-Dog Timer
315	--------------------------------------------------------------------------
316	*/
317
318	/* Watch-Dog Timer */
319	typedef struct WDT_struct
320	{
321	register8_t CTRL; /* Control */
322	register8_t WINCTRL; /* Windowed Mode Control */
323	register8_t STATUS; /* Status */
324	} WDT_t;
325
326	/* Period setting */
327	typedef enum WDT_PER_enum
328	{
329	WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
330	WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
331	WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
332	WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
333	WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
334	WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
335	WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
336	WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
337	WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
338	WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
339	WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
340	} WDT_PER_t;
341
342	/* Closed window period */
343	typedef enum WDT_WPER_enum
344	{
345	WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
346	WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
347	WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
348	WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
349	WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
350	WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
351	WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
352	WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
353	WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
354	WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
355	WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
356	} WDT_WPER_t;
357
358
359	/*
360	--------------------------------------------------------------------------
361	MCU - MCU Control
362	--------------------------------------------------------------------------
363	*/
364
365	/* MCU Control */
366	typedef struct MCU_struct
367	{
368	register8_t DEVID0; /* Device ID byte 0 */
369	register8_t DEVID1; /* Device ID byte 1 */
370	register8_t DEVID2; /* Device ID byte 2 */
371	register8_t REVID; /* Revision ID */
372	register8_t JTAGUID; /* JTAG User ID */
373	register8_t reserved_0x05;
374	register8_t MCUCR; /* MCU Control */
375	register8_t reserved_0x07;
376	register8_t EVSYSLOCK; /* Event System Lock */
377	register8_t AWEXLOCK; /* AWEX Lock */
378	register8_t reserved_0x0A;
379	register8_t reserved_0x0B;
380	} MCU_t;
381
382
383	/*
384	--------------------------------------------------------------------------
385	PMIC - Programmable Multi-level Interrupt Controller
386	--------------------------------------------------------------------------
387	*/
388
389	/* Programmable Multi-level Interrupt Controller */
390	typedef struct PMIC_struct
391	{
392	register8_t STATUS; /* Status Register */
393	register8_t INTPRI; /* Interrupt Priority */
394	register8_t CTRL; /* Control Register */
395	} PMIC_t;
396
397
398	/*
399	--------------------------------------------------------------------------
400	EVSYS - Event System
401	--------------------------------------------------------------------------
402	*/
403
404	/* Event System */
405	typedef struct EVSYS_struct
406	{
407	register8_t CH0MUX; /* Event Channel 0 Multiplexer */
408	register8_t CH1MUX; /* Event Channel 1 Multiplexer */
409	register8_t CH2MUX; /* Event Channel 2 Multiplexer */
410	register8_t CH3MUX; /* Event Channel 3 Multiplexer */
411	register8_t CH0CTRL; /* Channel 0 Control Register */
412	register8_t CH1CTRL; /* Channel 1 Control Register */
413	register8_t CH2CTRL; /* Channel 2 Control Register */
414	register8_t CH3CTRL; /* Channel 3 Control Register */
415	register8_t STROBE; /* Event Strobe */
416	register8_t DATA; /* Event Data */
417	} EVSYS_t;
418
419	/* Quadrature Decoder Index Recognition Mode */
420	typedef enum EVSYS_QDIRM_enum
421	{
422	EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
423	EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
424	EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
425	EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
426	} EVSYS_QDIRM_t;
427
428	/* Digital filter coefficient */
429	typedef enum EVSYS_DIGFILT_enum
430	{
431	EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
432	EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
433	EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
434	EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
435	EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
436	EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
437	EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
438	EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
439	} EVSYS_DIGFILT_t;
440
441	/* Event Channel multiplexer input selection */
442	typedef enum EVSYS_CHMUX_enum
443	{
444	EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
445	EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
446	EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
447	EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
448	EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
449	EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
450	EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
451	EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
452	EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
453	EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
454	EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
455	EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
456	EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
457	EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
458	EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
459	EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
460	EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
461	EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
462	EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
463	EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
464	EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
465	EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
466	EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
467	EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
468	EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
469	EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
470	EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
471	EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
472	EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
473	EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
474	EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
475	EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
476	EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
477	EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
478	EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
479	EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
480	EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
481	EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
482	EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
483	EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
484	EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
485	EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
486	EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
487	EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
488	EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
489	EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
490	EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
491	EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
492	EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
493	EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
494	EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
495	EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
496	EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
497	EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
498	EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
499	EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
500	EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
501	EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
502	EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
503	EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
504	EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
505	EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
506	EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
507	EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
508	EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
509	EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
510	EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
511	EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
512	EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
513	EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
514	EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
515	EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
516	EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
517	EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
518	EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
519	EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
520	EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
521	EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
522	EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
523	EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
524	EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
525	EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
526	EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
527	EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
528	EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
529	EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
530	EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
531	EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
532	EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
533	EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
534	EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
535	EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
536	EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
537	EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
538	EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
539	EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
540	EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
541	EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
542	EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
543	EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
544	EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
545	EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
546	EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
547	EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
548	EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
549	EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
550	EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
551	EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
552	EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
553	EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
554	EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
555	} EVSYS_CHMUX_t;
556
557
558	/*
559	--------------------------------------------------------------------------
560	NVM - Non Volatile Memory Controller
561	--------------------------------------------------------------------------
562	*/
563
564	/* Non-volatile Memory Controller */
565	typedef struct NVM_struct
566	{
567	register8_t ADDR0; /* Address Register 0 */
568	register8_t ADDR1; /* Address Register 1 */
569	register8_t ADDR2; /* Address Register 2 */
570	register8_t reserved_0x03;
571	register8_t DATA0; /* Data Register 0 */
572	register8_t DATA1; /* Data Register 1 */
573	register8_t DATA2; /* Data Register 2 */
574	register8_t reserved_0x07;
575	register8_t reserved_0x08;
576	register8_t reserved_0x09;
577	register8_t CMD; /* Command */
578	register8_t CTRLA; /* Control Register A */
579	register8_t CTRLB; /* Control Register B */
580	register8_t INTCTRL; /* Interrupt Control */
581	register8_t reserved_0x0E;
582	register8_t STATUS; /* Status */
583	register8_t LOCKBITS; /* Lock Bits */
584	} NVM_t;
585
586	/*
587	--------------------------------------------------------------------------
588	NVM - Non Volatile Memory Controller
589	--------------------------------------------------------------------------
590	*/
591
592	/* Lock Bits */
593	typedef struct NVM_LOCKBITS_struct
594	{
595	register8_t LOCKBITS; /* Lock Bits */
596	} NVM_LOCKBITS_t;
597
598	/*
599	--------------------------------------------------------------------------
600	NVM - Non Volatile Memory Controller
601	--------------------------------------------------------------------------
602	*/
603
604	/* Fuses */
605	typedef struct NVM_FUSES_struct
606	{
607	register8_t FUSEBYTE0; /* User ID */
608	register8_t FUSEBYTE1; /* Watchdog Configuration */
609	register8_t FUSEBYTE2; /* Reset Configuration */
610	register8_t reserved_0x03;
611	register8_t FUSEBYTE4; /* Start-up Configuration */
612	register8_t FUSEBYTE5; /* EESAVE and BOD Level */
613	} NVM_FUSES_t;
614
615	/*
616	--------------------------------------------------------------------------
617	NVM - Non Volatile Memory Controller
618	--------------------------------------------------------------------------
619	*/
620
621	/* Production Signatures */
622	typedef struct NVM_PROD_SIGNATURES_struct
623	{
624	register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
625	register8_t reserved_0x01;
626	register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
627	register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
628	register8_t reserved_0x04;
629	register8_t reserved_0x05;
630	register8_t reserved_0x06;
631	register8_t reserved_0x07;
632	register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
633	register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
634	register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
635	register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
636	register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
637	register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
638	register8_t reserved_0x0E;
639	register8_t reserved_0x0F;
640	register8_t WAFNUM; /* Wafer Number */
641	register8_t reserved_0x11;
642	register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
643	register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
644	register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
645	register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
646	register8_t reserved_0x16;
647	register8_t reserved_0x17;
648	register8_t reserved_0x18;
649	register8_t reserved_0x19;
650	register8_t reserved_0x1A;
651	register8_t reserved_0x1B;
652	register8_t reserved_0x1C;
653	register8_t reserved_0x1D;
654	register8_t reserved_0x1E;
655	register8_t reserved_0x1F;
656	register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
657	register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
658	register8_t reserved_0x22;
659	register8_t reserved_0x23;
660	register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
661	register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
662	register8_t reserved_0x26;
663	register8_t reserved_0x27;
664	register8_t reserved_0x28;
665	register8_t reserved_0x29;
666	register8_t reserved_0x2A;
667	register8_t reserved_0x2B;
668	register8_t reserved_0x2C;
669	register8_t reserved_0x2D;
670	register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
671	register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
672	register8_t reserved_0x30;
673	register8_t reserved_0x31;
674	register8_t reserved_0x32;
675	register8_t reserved_0x33;
676	register8_t reserved_0x34;
677	register8_t reserved_0x35;
678	register8_t reserved_0x36;
679	register8_t reserved_0x37;
680	register8_t reserved_0x38;
681	register8_t reserved_0x39;
682	register8_t reserved_0x3A;
683	register8_t reserved_0x3B;
684	register8_t reserved_0x3C;
685	register8_t reserved_0x3D;
686	register8_t reserved_0x3E;
687	} NVM_PROD_SIGNATURES_t;
688
689	/* NVM Command */
690	typedef enum NVM_CMD_enum
691	{
692	NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
693	NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
694	NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
695	NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
696	NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
697	NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
698	NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
699	NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
700	NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
701	NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
702	NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
703	NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
704	NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
705	NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
706	NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
707	NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
708	NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
709	NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
710	NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
711	NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
712	NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
713	NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
714	NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
715	NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
716	NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
717	NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
718	} NVM_CMD_t;
719
720	/* SPM ready interrupt level */
721	typedef enum NVM_SPMLVL_enum
722	{
723	NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
724	NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
725	NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
726	NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
727	} NVM_SPMLVL_t;
728
729	/* EEPROM ready interrupt level */
730	typedef enum NVM_EELVL_enum
731	{
732	NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
733	NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
734	NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
735	NVM_EELVL_HI_gc = (0x03<<0), /* High level */
736	} NVM_EELVL_t;
737
738	/* Boot lock bits - boot setcion */
739	typedef enum NVM_BLBB_enum
740	{
741	NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
742	NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
743	NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
744	NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
745	} NVM_BLBB_t;
746
747	/* Boot lock bits - application section */
748	typedef enum NVM_BLBA_enum
749	{
750	NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
751	NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
752	NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
753	NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
754	} NVM_BLBA_t;
755
756	/* Boot lock bits - application table section */
757	typedef enum NVM_BLBAT_enum
758	{
759	NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
760	NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
761	NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
762	NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
763	} NVM_BLBAT_t;
764
765	/* Lock bits */
766	typedef enum NVM_LB_enum
767	{
768	NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
769	NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
770	NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
771	} NVM_LB_t;
772
773	/* Boot Loader Section Reset Vector */
774	typedef enum BOOTRST_enum
775	{
776	BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
777	BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
778	} BOOTRST_t;
779
780	/* BOD operation */
781	typedef enum BOD_enum
782	{
783	BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
784	BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
785	BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
786	} BOD_t;
787
788	/* Watchdog (Window) Timeout Period */
789	typedef enum WD_enum
790	{
791	WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
792	WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
793	WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
794	WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
795	WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
796	WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
797	WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
798	WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
799	WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
800	WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
801	WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
802	} WD_t;
803
804	/* Start-up Time */
805	typedef enum SUT_enum
806	{
807	SUT_0MS_gc = (0x03<<2), /* 0 ms */
808	SUT_4MS_gc = (0x01<<2), /* 4 ms */
809	SUT_64MS_gc = (0x00<<2), /* 64 ms */
810	} SUT_t;
811
812	/* Brown Out Detection Voltage Level */
813	typedef enum BODLVL_enum
814	{
815	BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
816	BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */
817	BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */
818	BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */
819	BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */
820	BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */
821	BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */
822	} BODLVL_t;
823
824
825	/*
826	--------------------------------------------------------------------------
827	AC - Analog Comparator
828	--------------------------------------------------------------------------
829	*/
830
831	/* Analog Comparator */
832	typedef struct AC_struct
833	{
834	register8_t AC0CTRL; /* Comparator 0 Control */
835	register8_t AC1CTRL; /* Comparator 1 Control */
836	register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
837	register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
838	register8_t CTRLA; /* Control Register A */
839	register8_t CTRLB; /* Control Register B */
840	register8_t WINCTRL; /* Window Mode Control */
841	register8_t STATUS; /* Status */
842	} AC_t;
843
844	/* Interrupt mode */
845	typedef enum AC_INTMODE_enum
846	{
847	AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
848	AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
849	AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
850	} AC_INTMODE_t;
851
852	/* Interrupt level */
853	typedef enum AC_INTLVL_enum
854	{
855	AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
856	AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
857	AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
858	AC_INTLVL_HI_gc = (0x03<<4), /* High level */
859	} AC_INTLVL_t;
860
861	/* Hysteresis mode selection */
862	typedef enum AC_HYSMODE_enum
863	{
864	AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
865	AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
866	AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
867	} AC_HYSMODE_t;
868
869	/* Positive input multiplexer selection */
870	typedef enum AC_MUXPOS_enum
871	{
872	AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
873	AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
874	AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
875	AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
876	AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
877	AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
878	AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
879	} AC_MUXPOS_t;
880
881	/* Negative input multiplexer selection */
882	typedef enum AC_MUXNEG_enum
883	{
884	AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
885	AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
886	AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
887	AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
888	AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
889	AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
890	AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
891	} AC_MUXNEG_t;
892
893	/* Windows interrupt mode */
894	typedef enum AC_WINTMODE_enum
895	{
896	AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
897	AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
898	AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
899	AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
900	} AC_WINTMODE_t;
901
902	/* Window interrupt level */
903	typedef enum AC_WINTLVL_enum
904	{
905	AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
906	AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
907	AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
908	AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
909	} AC_WINTLVL_t;
910
911	/* Window mode state */
912	typedef enum AC_WSTATE_enum
913	{
914	AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
915	AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
916	AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
917	} AC_WSTATE_t;
918
919
920	/*
921	--------------------------------------------------------------------------
922	ADC - Analog/Digital Converter
923	--------------------------------------------------------------------------
924	*/
925
926	/* ADC Channel */
927	typedef struct ADC_CH_struct
928	{
929	register8_t CTRL; /* Control Register */
930	register8_t MUXCTRL; /* MUX Control */
931	register8_t INTCTRL; /* Channel Interrupt Control */
932	register8_t INTFLAGS; /* Interrupt Flags */
933	_WORDREGISTER(RES); /* Channel Result */
934	register8_t reserved_0x6;
935	register8_t reserved_0x7;
936	} ADC_CH_t;
937
938	/*
939	--------------------------------------------------------------------------
940	ADC - Analog/Digital Converter
941	--------------------------------------------------------------------------
942	*/
943
944	/* Analog-to-Digital Converter */
945	typedef struct ADC_struct
946	{
947	register8_t CTRLA; /* Control Register A */
948	register8_t CTRLB; /* Control Register B */
949	register8_t REFCTRL; /* Reference Control */
950	register8_t EVCTRL; /* Event Control */
951	register8_t PRESCALER; /* Clock Prescaler */
952	register8_t reserved_0x05;
953	register8_t INTFLAGS; /* Interrupt Flags */
954	register8_t TEMP; /* ACD Temporary Register */
955	register8_t reserved_0x08;
956	register8_t reserved_0x09;
957	register8_t reserved_0x0A;
958	register8_t reserved_0x0B;
959	_WORDREGISTER(CAL); /* Calibration Value */
960	register8_t reserved_0x0E;
961	register8_t reserved_0x0F;
962	_WORDREGISTER(CH0RES); /* Channel 0 Result */
963	register8_t reserved_0x12;
964	register8_t reserved_0x13;
965	register8_t reserved_0x14;
966	register8_t reserved_0x15;
967	register8_t reserved_0x16;
968	register8_t reserved_0x17;
969	_WORDREGISTER(CMP); /* Compare Value */
970	register8_t reserved_0x1A;
971	register8_t reserved_0x1B;
972	register8_t reserved_0x1C;
973	register8_t reserved_0x1D;
974	register8_t reserved_0x1E;
975	register8_t reserved_0x1F;
976	ADC_CH_t CH0; /* ADC Channel 0 */
977	} ADC_t;
978
979	/* Positive input multiplexer selection */
980	typedef enum ADC_CH_MUXPOS_enum
981	{
982	ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
983	ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
984	ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
985	ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
986	ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
987	ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
988	ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
989	ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
990	} ADC_CH_MUXPOS_t;
991
992	/* Negative input multiplexer selection */
993	typedef enum ADC_CH_MUXNEG_enum
994	{
995	ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
996	ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
997	ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
998	ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
999	ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
1000	ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
1001	ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
1002	ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
1003	} ADC_CH_MUXNEG_t;
1004
1005	/* Input mode */
1006	typedef enum ADC_CH_INPUTMODE_enum
1007	{
1008	ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1009	ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1010	ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1011	ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1012	} ADC_CH_INPUTMODE_t;
1013
1014	/* Gain factor */
1015	typedef enum ADC_CH_GAIN_enum
1016	{
1017	ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1018	ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1019	ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1020	ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1021	ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1022	ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1023	ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1024	} ADC_CH_GAIN_t;
1025
1026	/* Conversion result resolution */
1027	typedef enum ADC_RESOLUTION_enum
1028	{
1029	ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1030	ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1031	ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1032	} ADC_RESOLUTION_t;
1033
1034	/* Voltage reference selection */
1035	typedef enum ADC_REFSEL_enum
1036	{
1037	ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1038	ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
1039	ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1040	ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1041	} ADC_REFSEL_t;
1042
1043	/* Event channel input selection */
1044	typedef enum ADC_EVSEL_enum
1045	{
1046	ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1047	ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1048	ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1049	ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1050	ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1051	ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1052	ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1053	ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1054	} ADC_EVSEL_t;
1055
1056	/* Event action selection */
1057	typedef enum ADC_EVACT_enum
1058	{
1059	ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1060	ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1061	} ADC_EVACT_t;
1062
1063	/* Interupt mode */
1064	typedef enum ADC_CH_INTMODE_enum
1065	{
1066	ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1067	ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1068	ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1069	} ADC_CH_INTMODE_t;
1070
1071	/* Interrupt level */
1072	typedef enum ADC_CH_INTLVL_enum
1073	{
1074	ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1075	ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1076	ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1077	ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1078	} ADC_CH_INTLVL_t;
1079
1080	/* Clock prescaler */
1081	typedef enum ADC_PRESCALER_enum
1082	{
1083	ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1084	ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1085	ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1086	ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1087	ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1088	ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1089	ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1090	ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1091	} ADC_PRESCALER_t;
1092
1093
1094	/*
1095	--------------------------------------------------------------------------
1096	RTC - Real-Time Clounter
1097	--------------------------------------------------------------------------
1098	*/
1099
1100	/* Real-Time Counter */
1101	typedef struct RTC_struct
1102	{
1103	register8_t CTRL; /* Control Register */
1104	register8_t STATUS; /* Status Register */
1105	register8_t INTCTRL; /* Interrupt Control Register */
1106	register8_t INTFLAGS; /* Interrupt Flags */
1107	register8_t TEMP; /* Temporary register */
1108	register8_t reserved_0x05;
1109	register8_t reserved_0x06;
1110	register8_t reserved_0x07;
1111	_WORDREGISTER(CNT); /* Count Register */
1112	_WORDREGISTER(PER); /* Period Register */
1113	_WORDREGISTER(COMP); /* Compare Register */
1114	} RTC_t;
1115
1116	/* Prescaler Factor */
1117	typedef enum RTC_PRESCALER_enum
1118	{
1119	RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1120	RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1121	RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1122	RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1123	RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1124	RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1125	RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1126	RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1127	} RTC_PRESCALER_t;
1128
1129	/* Compare Interrupt level */
1130	typedef enum RTC_COMPINTLVL_enum
1131	{
1132	RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1133	RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1134	RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1135	RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1136	} RTC_COMPINTLVL_t;
1137
1138	/* Overflow Interrupt level */
1139	typedef enum RTC_OVFINTLVL_enum
1140	{
1141	RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1142	RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1143	RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1144	RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1145	} RTC_OVFINTLVL_t;
1146
1147
1148	/*
1149	--------------------------------------------------------------------------
1150	EBI - External Bus Interface
1151	--------------------------------------------------------------------------
1152	*/
1153
1154	/* EBI Chip Select Module */
1155	typedef struct EBI_CS_struct
1156	{
1157	register8_t CTRLA; /* Chip Select Control Register A */
1158	register8_t CTRLB; /* Chip Select Control Register B */
1159	_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1160	} EBI_CS_t;
1161
1162	/*
1163	--------------------------------------------------------------------------
1164	EBI - External Bus Interface
1165	--------------------------------------------------------------------------
1166	*/
1167
1168	/* External Bus Interface */
1169	typedef struct EBI_struct
1170	{
1171	register8_t CTRL; /* Control */
1172	register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1173	register8_t reserved_0x02;
1174	register8_t reserved_0x03;
1175	_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1176	_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1177	register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1178	register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1179	register8_t reserved_0x0A;
1180	register8_t reserved_0x0B;
1181	register8_t reserved_0x0C;
1182	register8_t reserved_0x0D;
1183	register8_t reserved_0x0E;
1184	register8_t reserved_0x0F;
1185	EBI_CS_t CS0; /* Chip Select 0 */
1186	EBI_CS_t CS1; /* Chip Select 1 */
1187	EBI_CS_t CS2; /* Chip Select 2 */
1188	EBI_CS_t CS3; /* Chip Select 3 */
1189	} EBI_t;
1190
1191	/* Chip Select adress space */
1192	typedef enum EBI_CS_ASPACE_enum
1193	{
1194	EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
1195	EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
1196	EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
1197	EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
1198	EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
1199	EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
1200	EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
1201	EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
1202	EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
1203	EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
1204	EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
1205	EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
1206	EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
1207	EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
1208	EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
1209	EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
1210	EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
1211	} EBI_CS_ASPACE_t;
1212
1213	/* */
1214	typedef enum EBI_CS_SRWS_enum
1215	{
1216	EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1217	EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1218	EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1219	EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1220	EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1221	EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1222	EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1223	EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1224	} EBI_CS_SRWS_t;
1225
1226	/* Chip Select address mode */
1227	typedef enum EBI_CS_MODE_enum
1228	{
1229	EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1230	EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1231	EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1232	EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1233	} EBI_CS_MODE_t;
1234
1235	/* Chip Select SDRAM mode */
1236	typedef enum EBI_CS_SDMODE_enum
1237	{
1238	EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1239	EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1240	} EBI_CS_SDMODE_t;
1241
1242	/* */
1243	typedef enum EBI_SDDATAW_enum
1244	{
1245	EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1246	EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1247	} EBI_SDDATAW_t;
1248
1249	/* */
1250	typedef enum EBI_LPCMODE_enum
1251	{
1252	EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1253	EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1254	} EBI_LPCMODE_t;
1255
1256	/* */
1257	typedef enum EBI_SRMODE_enum
1258	{
1259	EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1260	EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1261	EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1262	EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1263	} EBI_SRMODE_t;
1264
1265	/* */
1266	typedef enum EBI_IFMODE_enum
1267	{
1268	EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1269	EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1270	EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1271	EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1272	} EBI_IFMODE_t;
1273
1274	/* */
1275	typedef enum EBI_SDCOL_enum
1276	{
1277	EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1278	EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1279	EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1280	EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1281	} EBI_SDCOL_t;
1282
1283	/* */
1284	typedef enum EBI_MRDLY_enum
1285	{
1286	EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1287	EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1288	EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1289	EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1290	} EBI_MRDLY_t;
1291
1292	/* */
1293	typedef enum EBI_ROWCYCDLY_enum
1294	{
1295	EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1296	EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1297	EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1298	EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1299	EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1300	EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1301	EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1302	EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1303	} EBI_ROWCYCDLY_t;
1304
1305	/* */
1306	typedef enum EBI_RPDLY_enum
1307	{
1308	EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1309	EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1310	EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1311	EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1312	EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1313	EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1314	EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1315	EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1316	} EBI_RPDLY_t;
1317
1318	/* */
1319	typedef enum EBI_WRDLY_enum
1320	{
1321	EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1322	EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1323	EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1324	EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1325	} EBI_WRDLY_t;
1326
1327	/* */
1328	typedef enum EBI_ESRDLY_enum
1329	{
1330	EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1331	EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1332	EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1333	EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1334	EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1335	EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1336	EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1337	EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1338	} EBI_ESRDLY_t;
1339
1340	/* */
1341	typedef enum EBI_ROWCOLDLY_enum
1342	{
1343	EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1344	EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1345	EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1346	EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1347	EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1348	EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1349	EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1350	EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1351	} EBI_ROWCOLDLY_t;
1352
1353
1354	/*
1355	--------------------------------------------------------------------------
1356	TWI - Two-Wire Interface
1357	--------------------------------------------------------------------------
1358	*/
1359
1360	/* */
1361	typedef struct TWI_MASTER_struct
1362	{
1363	register8_t CTRLA; /* Control Register A */
1364	register8_t CTRLB; /* Control Register B */
1365	register8_t CTRLC; /* Control Register C */
1366	register8_t STATUS; /* Status Register */
1367	register8_t BAUD; /* Baurd Rate Control Register */
1368	register8_t ADDR; /* Address Register */
1369	register8_t DATA; /* Data Register */
1370	} TWI_MASTER_t;
1371
1372	/*
1373	--------------------------------------------------------------------------
1374	TWI - Two-Wire Interface
1375	--------------------------------------------------------------------------
1376	*/
1377
1378	/* */
1379	typedef struct TWI_SLAVE_struct
1380	{
1381	register8_t CTRLA; /* Control Register A */
1382	register8_t CTRLB; /* Control Register B */
1383	register8_t STATUS; /* Status Register */
1384	register8_t ADDR; /* Address Register */
1385	register8_t DATA; /* Data Register */
1386	register8_t ADDRMASK; /* Address Mask Register */
1387	} TWI_SLAVE_t;
1388
1389	/*
1390	--------------------------------------------------------------------------
1391	TWI - Two-Wire Interface
1392	--------------------------------------------------------------------------
1393	*/
1394
1395	/* Two-Wire Interface */
1396	typedef struct TWI_struct
1397	{
1398	register8_t CTRL; /* TWI Common Control Register */
1399	TWI_MASTER_t MASTER; /* TWI master module */
1400	TWI_SLAVE_t SLAVE; /* TWI slave module */
1401	} TWI_t;
1402
1403	/* Master Interrupt Level */
1404	typedef enum TWI_MASTER_INTLVL_enum
1405	{
1406	TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1407	TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1408	TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1409	TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1410	} TWI_MASTER_INTLVL_t;
1411
1412	/* Inactive Timeout */
1413	typedef enum TWI_MASTER_TIMEOUT_enum
1414	{
1415	TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1416	TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1417	TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1418	TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1419	} TWI_MASTER_TIMEOUT_t;
1420
1421	/* Master Command */
1422	typedef enum TWI_MASTER_CMD_enum
1423	{
1424	TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1425	TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1426	TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1427	TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1428	} TWI_MASTER_CMD_t;
1429
1430	/* Master Bus State */
1431	typedef enum TWI_MASTER_BUSSTATE_enum
1432	{
1433	TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1434	TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1435	TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1436	TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1437	} TWI_MASTER_BUSSTATE_t;
1438
1439	/* Slave Interrupt Level */
1440	typedef enum TWI_SLAVE_INTLVL_enum
1441	{
1442	TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1443	TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1444	TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1445	TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1446	} TWI_SLAVE_INTLVL_t;
1447
1448	/* Slave Command */
1449	typedef enum TWI_SLAVE_CMD_enum
1450	{
1451	TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1452	TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1453	TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1454	} TWI_SLAVE_CMD_t;
1455
1456
1457	/*
1458	--------------------------------------------------------------------------
1459	PORT - Port Configuration
1460	--------------------------------------------------------------------------
1461	*/
1462
1463	/* I/O port Configuration */
1464	typedef struct PORTCFG_struct
1465	{
1466	register8_t MPCMASK; /* Multi-pin Configuration Mask */
1467	register8_t reserved_0x01;
1468	register8_t VPCTRLA; /* Virtual Port Control Register A */
1469	register8_t VPCTRLB; /* Virtual Port Control Register B */
1470	register8_t CLKEVOUT; /* Clock and Event Out Register */
1471	} PORTCFG_t;
1472
1473	/*
1474	--------------------------------------------------------------------------
1475	PORT - Port Configuration
1476	--------------------------------------------------------------------------
1477	*/
1478
1479	/* Virtual Port */
1480	typedef struct VPORT_struct
1481	{
1482	register8_t DIR; /* I/O Port Data Direction */
1483	register8_t OUT; /* I/O Port Output */
1484	register8_t IN; /* I/O Port Input */
1485	register8_t INTFLAGS; /* Interrupt Flag Register */
1486	} VPORT_t;
1487
1488	/*
1489	--------------------------------------------------------------------------
1490	PORT - Port Configuration
1491	--------------------------------------------------------------------------
1492	*/
1493
1494	/* I/O Ports */
1495	typedef struct PORT_struct
1496	{
1497	register8_t DIR; /* I/O Port Data Direction */
1498	register8_t DIRSET; /* I/O Port Data Direction Set */
1499	register8_t DIRCLR; /* I/O Port Data Direction Clear */
1500	register8_t DIRTGL; /* I/O Port Data Direction Toggle */
1501	register8_t OUT; /* I/O Port Output */
1502	register8_t OUTSET; /* I/O Port Output Set */
1503	register8_t OUTCLR; /* I/O Port Output Clear */
1504	register8_t OUTTGL; /* I/O Port Output Toggle */
1505	register8_t IN; /* I/O port Input */
1506	register8_t INTCTRL; /* Interrupt Control Register */
1507	register8_t INT0MASK; /* Port Interrupt 0 Mask */
1508	register8_t INT1MASK; /* Port Interrupt 1 Mask */
1509	register8_t INTFLAGS; /* Interrupt Flag Register */
1510	register8_t reserved_0x0D;
1511	register8_t reserved_0x0E;
1512	register8_t reserved_0x0F;
1513	register8_t PIN0CTRL; /* Pin 0 Control Register */
1514	register8_t PIN1CTRL; /* Pin 1 Control Register */
1515	register8_t PIN2CTRL; /* Pin 2 Control Register */
1516	register8_t PIN3CTRL; /* Pin 3 Control Register */
1517	register8_t PIN4CTRL; /* Pin 4 Control Register */
1518	register8_t PIN5CTRL; /* Pin 5 Control Register */
1519	register8_t PIN6CTRL; /* Pin 6 Control Register */
1520	register8_t PIN7CTRL; /* Pin 7 Control Register */
1521	} PORT_t;
1522
1523	/* Virtual Port 0 Mapping */
1524	typedef enum PORTCFG_VP0MAP_enum
1525	{
1526	PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1527	PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1528	PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1529	PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1530	PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1531	PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1532	PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1533	PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1534	PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1535	PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1536	PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1537	PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1538	PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1539	PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1540	PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1541	PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1542	} PORTCFG_VP0MAP_t;
1543
1544	/* Virtual Port 1 Mapping */
1545	typedef enum PORTCFG_VP1MAP_enum
1546	{
1547	PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1548	PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1549	PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1550	PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1551	PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1552	PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1553	PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1554	PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1555	PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1556	PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1557	PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1558	PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1559	PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1560	PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1561	PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1562	PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1563	} PORTCFG_VP1MAP_t;
1564
1565	/* Virtual Port 2 Mapping */
1566	typedef enum PORTCFG_VP2MAP_enum
1567	{
1568	PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1569	PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1570	PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1571	PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1572	PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1573	PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1574	PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1575	PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1576	PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1577	PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1578	PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1579	PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1580	PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1581	PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1582	PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1583	PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1584	} PORTCFG_VP2MAP_t;
1585
1586	/* Virtual Port 3 Mapping */
1587	typedef enum PORTCFG_VP3MAP_enum
1588	{
1589	PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1590	PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1591	PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1592	PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1593	PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1594	PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1595	PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1596	PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1597	PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1598	PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1599	PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1600	PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1601	PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1602	PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1603	PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1604	PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1605	} PORTCFG_VP3MAP_t;
1606
1607	/* Clock Output Port */
1608	typedef enum PORTCFG_CLKOUT_enum
1609	{
1610	PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
1611	PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
1612	PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
1613	PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
1614	} PORTCFG_CLKOUT_t;
1615
1616	/* Event Output Port */
1617	typedef enum PORTCFG_EVOUT_enum
1618	{
1619	PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
1620	PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
1621	PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
1622	PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
1623	} PORTCFG_EVOUT_t;
1624
1625	/* Port Interrupt 0 Level */
1626	typedef enum PORT_INT0LVL_enum
1627	{
1628	PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1629	PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
1630	PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
1631	PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
1632	} PORT_INT0LVL_t;
1633
1634	/* Port Interrupt 1 Level */
1635	typedef enum PORT_INT1LVL_enum
1636	{
1637	PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1638	PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
1639	PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
1640	PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
1641	} PORT_INT1LVL_t;
1642
1643	/* Output/Pull Configuration */
1644	typedef enum PORT_OPC_enum
1645	{
1646	PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
1647	PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
1648	PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
1649	PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
1650	PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
1651	PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
1652	PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
1653	PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
1654	} PORT_OPC_t;
1655
1656	/* Input/Sense Configuration */
1657	typedef enum PORT_ISC_enum
1658	{
1659	PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
1660	PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
1661	PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
1662	PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
1663	PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
1664	} PORT_ISC_t;
1665
1666
1667	/*
1668	--------------------------------------------------------------------------
1669	TC - 16-bit Timer/Counter With PWM
1670	--------------------------------------------------------------------------
1671	*/
1672
1673	/* 16-bit Timer/Counter 0 */
1674	typedef struct TC0_struct
1675	{
1676	register8_t CTRLA; /* Control Register A */
1677	register8_t CTRLB; /* Control Register B */
1678	register8_t CTRLC; /* Control register C */
1679	register8_t CTRLD; /* Control Register D */
1680	register8_t CTRLE; /* Control Register E */
1681	register8_t reserved_0x05;
1682	register8_t INTCTRLA; /* Interrupt Control Register A */
1683	register8_t INTCTRLB; /* Interrupt Control Register B */
1684	register8_t CTRLFCLR; /* Control Register F Clear */
1685	register8_t CTRLFSET; /* Control Register F Set */
1686	register8_t CTRLGCLR; /* Control Register G Clear */
1687	register8_t CTRLGSET; /* Control Register G Set */
1688	register8_t INTFLAGS; /* Interrupt Flag Register */
1689	register8_t reserved_0x0D;
1690	register8_t reserved_0x0E;
1691	register8_t TEMP; /* Temporary Register For 16-bit Access */
1692	register8_t reserved_0x10;
1693	register8_t reserved_0x11;
1694	register8_t reserved_0x12;
1695	register8_t reserved_0x13;
1696	register8_t reserved_0x14;
1697	register8_t reserved_0x15;
1698	register8_t reserved_0x16;
1699	register8_t reserved_0x17;
1700	register8_t reserved_0x18;
1701	register8_t reserved_0x19;
1702	register8_t reserved_0x1A;
1703	register8_t reserved_0x1B;
1704	register8_t reserved_0x1C;
1705	register8_t reserved_0x1D;
1706	register8_t reserved_0x1E;
1707	register8_t reserved_0x1F;
1708	_WORDREGISTER(CNT); /* Count */
1709	register8_t reserved_0x22;
1710	register8_t reserved_0x23;
1711	register8_t reserved_0x24;
1712	register8_t reserved_0x25;
1713	_WORDREGISTER(PER); /* Period */
1714	_WORDREGISTER(CCA); /* Compare or Capture A */
1715	_WORDREGISTER(CCB); /* Compare or Capture B */
1716	_WORDREGISTER(CCC); /* Compare or Capture C */
1717	_WORDREGISTER(CCD); /* Compare or Capture D */
1718	register8_t reserved_0x30;
1719	register8_t reserved_0x31;
1720	register8_t reserved_0x32;
1721	register8_t reserved_0x33;
1722	register8_t reserved_0x34;
1723	register8_t reserved_0x35;
1724	_WORDREGISTER(PERBUF); /* Period Buffer */
1725	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1726	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1727	_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
1728	_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
1729	} TC0_t;
1730
1731	/*
1732	--------------------------------------------------------------------------
1733	TC - 16-bit Timer/Counter With PWM
1734	--------------------------------------------------------------------------
1735	*/
1736
1737	/* 16-bit Timer/Counter 1 */
1738	typedef struct TC1_struct
1739	{
1740	register8_t CTRLA; /* Control Register A */
1741	register8_t CTRLB; /* Control Register B */
1742	register8_t CTRLC; /* Control register C */
1743	register8_t CTRLD; /* Control Register D */
1744	register8_t CTRLE; /* Control Register E */
1745	register8_t reserved_0x05;
1746	register8_t INTCTRLA; /* Interrupt Control Register A */
1747	register8_t INTCTRLB; /* Interrupt Control Register B */
1748	register8_t CTRLFCLR; /* Control Register F Clear */
1749	register8_t CTRLFSET; /* Control Register F Set */
1750	register8_t CTRLGCLR; /* Control Register G Clear */
1751	register8_t CTRLGSET; /* Control Register G Set */
1752	register8_t INTFLAGS; /* Interrupt Flag Register */
1753	register8_t reserved_0x0D;
1754	register8_t reserved_0x0E;
1755	register8_t TEMP; /* Temporary Register For 16-bit Access */
1756	register8_t reserved_0x10;
1757	register8_t reserved_0x11;
1758	register8_t reserved_0x12;
1759	register8_t reserved_0x13;
1760	register8_t reserved_0x14;
1761	register8_t reserved_0x15;
1762	register8_t reserved_0x16;
1763	register8_t reserved_0x17;
1764	register8_t reserved_0x18;
1765	register8_t reserved_0x19;
1766	register8_t reserved_0x1A;
1767	register8_t reserved_0x1B;
1768	register8_t reserved_0x1C;
1769	register8_t reserved_0x1D;
1770	register8_t reserved_0x1E;
1771	register8_t reserved_0x1F;
1772	_WORDREGISTER(CNT); /* Count */
1773	register8_t reserved_0x22;
1774	register8_t reserved_0x23;
1775	register8_t reserved_0x24;
1776	register8_t reserved_0x25;
1777	_WORDREGISTER(PER); /* Period */
1778	_WORDREGISTER(CCA); /* Compare or Capture A */
1779	_WORDREGISTER(CCB); /* Compare or Capture B */
1780	register8_t reserved_0x2C;
1781	register8_t reserved_0x2D;
1782	register8_t reserved_0x2E;
1783	register8_t reserved_0x2F;
1784	register8_t reserved_0x30;
1785	register8_t reserved_0x31;
1786	register8_t reserved_0x32;
1787	register8_t reserved_0x33;
1788	register8_t reserved_0x34;
1789	register8_t reserved_0x35;
1790	_WORDREGISTER(PERBUF); /* Period Buffer */
1791	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1792	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1793	} TC1_t;
1794
1795	/*
1796	--------------------------------------------------------------------------
1797	TC - 16-bit Timer/Counter With PWM
1798	--------------------------------------------------------------------------
1799	*/
1800
1801	/* Advanced Waveform Extension */
1802	typedef struct AWEX_struct
1803	{
1804	register8_t CTRL; /* Control Register */
1805	register8_t reserved_0x01;
1806	register8_t FDEMASK; /* Fault Detection Event Mask */
1807	register8_t FDCTRL; /* Fault Detection Control Register */
1808	register8_t STATUS; /* Status Register */
1809	register8_t reserved_0x05;
1810	register8_t DTBOTH; /* Dead Time Both Sides */
1811	register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
1812	register8_t DTLS; /* Dead Time Low Side */
1813	register8_t DTHS; /* Dead Time High Side */
1814	register8_t DTLSBUF; /* Dead Time Low Side Buffer */
1815	register8_t DTHSBUF; /* Dead Time High Side Buffer */
1816	register8_t OUTOVEN; /* Output Override Enable */
1817	} AWEX_t;
1818
1819	/*
1820	--------------------------------------------------------------------------
1821	TC - 16-bit Timer/Counter With PWM
1822	--------------------------------------------------------------------------
1823	*/
1824
1825	/* High-Resolution Extension */
1826	typedef struct HIRES_struct
1827	{
1828	register8_t CTRLA; /* Control Register */
1829	} HIRES_t;
1830
1831	/* Clock Selection */
1832	typedef enum TC_CLKSEL_enum
1833	{
1834	TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
1835	TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
1836	TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
1837	TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
1838	TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
1839	TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
1840	TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
1841	TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
1842	TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
1843	TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
1844	TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
1845	TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
1846	TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
1847	TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
1848	TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
1849	TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
1850	} TC_CLKSEL_t;
1851
1852	/* Waveform Generation Mode */
1853	typedef enum TC_WGMODE_enum
1854	{
1855	TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
1856	TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
1857	TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
1858	TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
1859	TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
1860	TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
1861	} TC_WGMODE_t;
1862
1863	/* Event Action */
1864	typedef enum TC_EVACT_enum
1865	{
1866	TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
1867	TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
1868	TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
1869	TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
1870	TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
1871	TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
1872	TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
1873	} TC_EVACT_t;
1874
1875	/* Event Selection */
1876	typedef enum TC_EVSEL_enum
1877	{
1878	TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
1879	TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
1880	TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
1881	TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
1882	TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
1883	TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
1884	TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
1885	TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
1886	TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
1887	} TC_EVSEL_t;
1888
1889	/* Error Interrupt Level */
1890	typedef enum TC_ERRINTLVL_enum
1891	{
1892	TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1893	TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
1894	TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1895	TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
1896	} TC_ERRINTLVL_t;
1897
1898	/* Overflow Interrupt Level */
1899	typedef enum TC_OVFINTLVL_enum
1900	{
1901	TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1902	TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1903	TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1904	TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1905	} TC_OVFINTLVL_t;
1906
1907	/* Compare or Capture D Interrupt Level */
1908	typedef enum TC_CCDINTLVL_enum
1909	{
1910	TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1911	TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
1912	TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
1913	TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
1914	} TC_CCDINTLVL_t;
1915
1916	/* Compare or Capture C Interrupt Level */
1917	typedef enum TC_CCCINTLVL_enum
1918	{
1919	TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
1920	TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
1921	TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
1922	TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
1923	} TC_CCCINTLVL_t;
1924
1925	/* Compare or Capture B Interrupt Level */
1926	typedef enum TC_CCBINTLVL_enum
1927	{
1928	TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1929	TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
1930	TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1931	TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
1932	} TC_CCBINTLVL_t;
1933
1934	/* Compare or Capture A Interrupt Level */
1935	typedef enum TC_CCAINTLVL_enum
1936	{
1937	TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1938	TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
1939	TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1940	TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
1941	} TC_CCAINTLVL_t;
1942
1943	/* Timer/Counter Command */
1944	typedef enum TC_CMD_enum
1945	{
1946	TC_CMD_NONE_gc = (0x00<<2), /* No Command */
1947	TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
1948	TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
1949	TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
1950	} TC_CMD_t;
1951
1952	/* Fault Detect Action */
1953	typedef enum AWEX_FDACT_enum
1954	{
1955	AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
1956	AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
1957	AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
1958	} AWEX_FDACT_t;
1959
1960	/* High Resolution Enable */
1961	typedef enum HIRES_HREN_enum
1962	{
1963	HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
1964	HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
1965	HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
1966	HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
1967	} HIRES_HREN_t;
1968
1969
1970	/*
1971	--------------------------------------------------------------------------
1972	USART - Universal Asynchronous Receiver-Transmitter
1973	--------------------------------------------------------------------------
1974	*/
1975
1976	/* Universal Synchronous/Asynchronous Receiver/Transmitter */
1977	typedef struct USART_struct
1978	{
1979	register8_t DATA; /* Data Register */
1980	register8_t STATUS; /* Status Register */
1981	register8_t reserved_0x02;
1982	register8_t CTRLA; /* Control Register A */
1983	register8_t CTRLB; /* Control Register B */
1984	register8_t CTRLC; /* Control Register C */
1985	register8_t BAUDCTRLA; /* Baud Rate Control Register A */
1986	register8_t BAUDCTRLB; /* Baud Rate Control Register B */
1987	} USART_t;
1988
1989	/* Receive Complete Interrupt level */
1990	typedef enum USART_RXCINTLVL_enum
1991	{
1992	USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
1993	USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
1994	USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
1995	USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
1996	} USART_RXCINTLVL_t;
1997
1998	/* Transmit Complete Interrupt level */
1999	typedef enum USART_TXCINTLVL_enum
2000	{
2001	USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2002	USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2003	USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2004	USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2005	} USART_TXCINTLVL_t;
2006
2007	/* Data Register Empty Interrupt level */
2008	typedef enum USART_DREINTLVL_enum
2009	{
2010	USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2011	USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2012	USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2013	USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2014	} USART_DREINTLVL_t;
2015
2016	/* Character Size */
2017	typedef enum USART_CHSIZE_enum
2018	{
2019	USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2020	USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2021	USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2022	USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2023	USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2024	} USART_CHSIZE_t;
2025
2026	/* Communication Mode */
2027	typedef enum USART_CMODE_enum
2028	{
2029	USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2030	USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2031	USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2032	USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2033	} USART_CMODE_t;
2034
2035	/* Parity Mode */
2036	typedef enum USART_PMODE_enum
2037	{
2038	USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2039	USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2040	USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2041	} USART_PMODE_t;
2042
2043
2044	/*
2045	--------------------------------------------------------------------------
2046	SPI - Serial Peripheral Interface
2047	--------------------------------------------------------------------------
2048	*/
2049
2050	/* Serial Peripheral Interface */
2051	typedef struct SPI_struct
2052	{
2053	register8_t CTRL; /* Control Register */
2054	register8_t INTCTRL; /* Interrupt Control Register */
2055	register8_t STATUS; /* Status Register */
2056	register8_t DATA; /* Data Register */
2057	} SPI_t;
2058
2059	/* SPI Mode */
2060	typedef enum SPI_MODE_enum
2061	{
2062	SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2063	SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2064	SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2065	SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2066	} SPI_MODE_t;
2067
2068	/* Prescaler setting */
2069	typedef enum SPI_PRESCALER_enum
2070	{
2071	SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2072	SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2073	SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2074	SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2075	} SPI_PRESCALER_t;
2076
2077	/* Interrupt level */
2078	typedef enum SPI_INTLVL_enum
2079	{
2080	SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2081	SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2082	SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2083	SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2084	} SPI_INTLVL_t;
2085
2086
2087	/*
2088	--------------------------------------------------------------------------
2089	IRCOM - IR Communication Module
2090	--------------------------------------------------------------------------
2091	*/
2092
2093	/* IR Communication Module */
2094	typedef struct IRCOM_struct
2095	{
2096	register8_t CTRL; /* Control Register */
2097	register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2098	register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2099	} IRCOM_t;
2100
2101	/* Event channel selection */
2102	typedef enum IRDA_EVSEL_enum
2103	{
2104	IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2105	IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2106	IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2107	IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2108	IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2109	IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2110	IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2111	IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2112	IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2113	} IRDA_EVSEL_t;
2114
2115
2116
2117	/*
2118	==========================================================================
2119	IO Module Instances. Mapped to memory.
2120	==========================================================================
2121	*/
2122
2123	#define GPIO ((GPIO_t ) 0x0000) /* General Purpose IO Registers */
2124	#define VPORT0 ((VPORT_t ) 0x0010) /* Virtual Port 0 */
2125	#define VPORT1 ((VPORT_t ) 0x0014) /* Virtual Port 1 */
2126	#define VPORT2 ((VPORT_t ) 0x0018) /* Virtual Port 2 */
2127	#define VPORT3 ((VPORT_t ) 0x001C) /* Virtual Port 3 */
2128	#define OCD ((OCD_t ) 0x002E) /* On-Chip Debug System */
2129	#define CPU ((CPU_t ) 0x0030) /* CPU Registers */
2130	#define CLK ((CLK_t ) 0x0040) /* Clock System */
2131	#define SLEEP ((SLEEP_t ) 0x0048) /* Sleep Controller */
2132	#define OSC ((OSC_t ) 0x0050) /* Oscillator Control */
2133	#define DFLLRC32M ((DFLL_t ) 0x0060) /* DFLL for 32MHz RC Oscillator */
2134	#define DFLLRC2M ((DFLL_t ) 0x0068) /* DFLL for 2MHz RC Oscillator */
2135	#define RST ((RST_t ) 0x0078) /* Reset Controller */
2136	#define WDT ((WDT_t ) 0x0080) /* Watch-Dog Timer */
2137	#define MCU ((MCU_t ) 0x0090) /* MCU Control */
2138	#define PMIC ((PMIC_t ) 0x00A0) /* Programmable Interrupt Controller */
2139	#define PORTCFG ((PORTCFG_t ) 0x00B0) /* Port Configuration */
2140	#define EVSYS ((EVSYS_t ) 0x0180) /* Event System */
2141	#define NVM ((NVM_t ) 0x01C0) /* Non Volatile Memory Controller */
2142	#define ADCA ((ADC_t ) 0x0200) /* Analog to Digital Converter A */
2143	#define ACA ((AC_t ) 0x0380) /* Analog Comparator A */
2144	#define RTC ((RTC_t ) 0x0400) /* Real-Time Counter */
2145	#define TWIC ((TWI_t ) 0x0480) /* Two-Wire Interface C */
2146	#define PORTA ((PORT_t ) 0x0600) /* Port A */
2147	#define PORTB ((PORT_t ) 0x0620) /* Port B */
2148	#define PORTC ((PORT_t ) 0x0640) /* Port C */
2149	#define PORTD ((PORT_t ) 0x0660) /* Port D */
2150	#define PORTE ((PORT_t ) 0x0680) /* Port E */
2151	#define PORTF ((PORT_t ) 0x06A0) /* Port F */
2152	#define PORTR ((PORT_t ) 0x07E0) /* Port R */
2153	#define TCC0 ((TC0_t ) 0x0800) /* Timer/Counter C0 */
2154	#define TCC1 ((TC1_t ) 0x0840) /* Timer/Counter C1 */
2155	#define AWEXC ((AWEX_t ) 0x0880) /* Advanced Waveform Extension C */
2156	#define HIRESC ((HIRES_t ) 0x0890) /* High-Resolution Extension C */
2157	#define USARTC0 ((USART_t ) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2158	#define SPIC ((SPI_t ) 0x08C0) /* Serial Peripheral Interface C */
2159	#define IRCOM ((IRCOM_t ) 0x08F8) /* IR Communication Module */
2160	#define TCD0 ((TC0_t ) 0x0900) /* Timer/Counter D0 */
2161	#define USARTD0 ((USART_t ) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2162	#define SPID ((SPI_t ) 0x09C0) /* Serial Peripheral Interface D */
2163	#define TCE0 ((TC0_t ) 0x0A00) /* Timer/Counter E0 */
2164	#define AWEXE ((AWEX_t ) 0x0A80) /* Advanced Waveform Extension E */
2165	#define USARTE0 ((USART_t ) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
2166	#define SPIE ((SPI_t ) 0x0AC0) /* Serial Peripheral Interface E */
2167	#define TCF0 ((TC0_t ) 0x0B00) /* Timer/Counter F0 */
2168
2169
2170	#endif /* !defined (__ASSEMBLER__) */
2171
2172
2173	/* ========== Flattened fully qualified IO register names ========== */
2174
2175	/* GPIO - General Purpose IO Registers */
2176	#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
2177	#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
2178	#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
2179	#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
2180	#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
2181	#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
2182	#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
2183	#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
2184	#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
2185	#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
2186	#define GPIO_GPIORA _SFR_MEM8(0x000A)
2187	#define GPIO_GPIORB _SFR_MEM8(0x000B)
2188	#define GPIO_GPIORC _SFR_MEM8(0x000C)
2189	#define GPIO_GPIORD _SFR_MEM8(0x000D)
2190	#define GPIO_GPIORE _SFR_MEM8(0x000E)
2191	#define GPIO_GPIORF _SFR_MEM8(0x000F)
2192
2193	/* VPORT0 - Virtual Port 0 */
2194	#define VPORT0_DIR _SFR_MEM8(0x0010)
2195	#define VPORT0_OUT _SFR_MEM8(0x0011)
2196	#define VPORT0_IN _SFR_MEM8(0x0012)
2197	#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2198
2199	/* VPORT1 - Virtual Port 1 */
2200	#define VPORT1_DIR _SFR_MEM8(0x0014)
2201	#define VPORT1_OUT _SFR_MEM8(0x0015)
2202	#define VPORT1_IN _SFR_MEM8(0x0016)
2203	#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2204
2205	/* VPORT2 - Virtual Port 2 */
2206	#define VPORT2_DIR _SFR_MEM8(0x0018)
2207	#define VPORT2_OUT _SFR_MEM8(0x0019)
2208	#define VPORT2_IN _SFR_MEM8(0x001A)
2209	#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2210
2211	/* VPORT3 - Virtual Port 3 */
2212	#define VPORT3_DIR _SFR_MEM8(0x001C)
2213	#define VPORT3_OUT _SFR_MEM8(0x001D)
2214	#define VPORT3_IN _SFR_MEM8(0x001E)
2215	#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2216
2217	/* OCD - On-Chip Debug System */
2218	#define OCD_OCDR0 _SFR_MEM8(0x002E)
2219	#define OCD_OCDR1 _SFR_MEM8(0x002F)
2220
2221	/* CPU - CPU Registers */
2222	#define CPU_CCP _SFR_MEM8(0x0034)
2223	#define CPU_RAMPD _SFR_MEM8(0x0038)
2224	#define CPU_RAMPX _SFR_MEM8(0x0039)
2225	#define CPU_RAMPY _SFR_MEM8(0x003A)
2226	#define CPU_RAMPZ _SFR_MEM8(0x003B)
2227	#define CPU_EIND _SFR_MEM8(0x003C)
2228	#define CPU_SPL _SFR_MEM8(0x003D)
2229	#define CPU_SPH _SFR_MEM8(0x003E)
2230	#define CPU_SREG _SFR_MEM8(0x003F)
2231
2232	/* CLK - Clock System */
2233	#define CLK_CTRL _SFR_MEM8(0x0040)
2234	#define CLK_PSCTRL _SFR_MEM8(0x0041)
2235	#define CLK_LOCK _SFR_MEM8(0x0042)
2236	#define CLK_RTCCTRL _SFR_MEM8(0x0043)
2237
2238	/* SLEEP - Sleep Controller */
2239	#define SLEEP_CTRL _SFR_MEM8(0x0048)
2240
2241	/* OSC - Oscillator Control */
2242	#define OSC_CTRL _SFR_MEM8(0x0050)
2243	#define OSC_STATUS _SFR_MEM8(0x0051)
2244	#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2245	#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
2246	#define OSC_RC32KCAL _SFR_MEM8(0x0054)
2247	#define OSC_PLLCTRL _SFR_MEM8(0x0055)
2248	#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2249
2250	/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2251	#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2252	#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2253	#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2254	#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2255	#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2256	#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2257
2258	/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2259	#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2260	#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2261	#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2262	#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2263	#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2264	#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2265
2266	/* RST - Reset Controller */
2267	#define RST_STATUS _SFR_MEM8(0x0078)
2268	#define RST_CTRL _SFR_MEM8(0x0079)
2269
2270	/* WDT - Watch-Dog Timer */
2271	#define WDT_CTRL _SFR_MEM8(0x0080)
2272	#define WDT_WINCTRL _SFR_MEM8(0x0081)
2273	#define WDT_STATUS _SFR_MEM8(0x0082)
2274
2275	/* MCU - MCU Control */
2276	#define MCU_DEVID0 _SFR_MEM8(0x0090)
2277	#define MCU_DEVID1 _SFR_MEM8(0x0091)
2278	#define MCU_DEVID2 _SFR_MEM8(0x0092)
2279	#define MCU_REVID _SFR_MEM8(0x0093)
2280	#define MCU_JTAGUID _SFR_MEM8(0x0094)
2281	#define MCU_MCUCR _SFR_MEM8(0x0096)
2282	#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2283	#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2284
2285	/* PMIC - Programmable Interrupt Controller */
2286	#define PMIC_STATUS _SFR_MEM8(0x00A0)
2287	#define PMIC_INTPRI _SFR_MEM8(0x00A1)
2288	#define PMIC_CTRL _SFR_MEM8(0x00A2)
2289
2290	/* PORTCFG - Port Configuration */
2291	#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2292	#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2293	#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2294	#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2295
2296	/* EVSYS - Event System */
2297	#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2298	#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2299	#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2300	#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2301	#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2302	#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2303	#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2304	#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2305	#define EVSYS_STROBE _SFR_MEM8(0x0190)
2306	#define EVSYS_DATA _SFR_MEM8(0x0191)
2307
2308	/* NVM - Non Volatile Memory Controller */
2309	#define NVM_ADDR0 _SFR_MEM8(0x01C0)
2310	#define NVM_ADDR1 _SFR_MEM8(0x01C1)
2311	#define NVM_ADDR2 _SFR_MEM8(0x01C2)
2312	#define NVM_DATA0 _SFR_MEM8(0x01C4)
2313	#define NVM_DATA1 _SFR_MEM8(0x01C5)
2314	#define NVM_DATA2 _SFR_MEM8(0x01C6)
2315	#define NVM_CMD _SFR_MEM8(0x01CA)
2316	#define NVM_CTRLA _SFR_MEM8(0x01CB)
2317	#define NVM_CTRLB _SFR_MEM8(0x01CC)
2318	#define NVM_INTCTRL _SFR_MEM8(0x01CD)
2319	#define NVM_STATUS _SFR_MEM8(0x01CF)
2320	#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2321
2322	/* ADCA - Analog to Digital Converter A */
2323	#define ADCA_CTRLA _SFR_MEM8(0x0200)
2324	#define ADCA_CTRLB _SFR_MEM8(0x0201)
2325	#define ADCA_REFCTRL _SFR_MEM8(0x0202)
2326	#define ADCA_EVCTRL _SFR_MEM8(0x0203)
2327	#define ADCA_PRESCALER _SFR_MEM8(0x0204)
2328	#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2329	#define ADCA_TEMP _SFR_MEM8(0x0207)
2330	#define ADCA_CAL _SFR_MEM16(0x020C)
2331	#define ADCA_CH0RES _SFR_MEM16(0x0210)
2332	#define ADCA_CMP _SFR_MEM16(0x0218)
2333	#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2334	#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2335	#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2336	#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2337	#define ADCA_CH0_RES _SFR_MEM16(0x0224)
2338
2339	/* ACA - Analog Comparator A */
2340	#define ACA_AC0CTRL _SFR_MEM8(0x0380)
2341	#define ACA_AC1CTRL _SFR_MEM8(0x0381)
2342	#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
2343	#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
2344	#define ACA_CTRLA _SFR_MEM8(0x0384)
2345	#define ACA_CTRLB _SFR_MEM8(0x0385)
2346	#define ACA_WINCTRL _SFR_MEM8(0x0386)
2347	#define ACA_STATUS _SFR_MEM8(0x0387)
2348
2349	/* RTC - Real-Time Counter */
2350	#define RTC_CTRL _SFR_MEM8(0x0400)
2351	#define RTC_STATUS _SFR_MEM8(0x0401)
2352	#define RTC_INTCTRL _SFR_MEM8(0x0402)
2353	#define RTC_INTFLAGS _SFR_MEM8(0x0403)
2354	#define RTC_TEMP _SFR_MEM8(0x0404)
2355	#define RTC_CNT _SFR_MEM16(0x0408)
2356	#define RTC_PER _SFR_MEM16(0x040A)
2357	#define RTC_COMP _SFR_MEM16(0x040C)
2358
2359	/* TWIC - Two-Wire Interface C */
2360	#define TWIC_CTRL _SFR_MEM8(0x0480)
2361	#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
2362	#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
2363	#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
2364	#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
2365	#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
2366	#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
2367	#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
2368	#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
2369	#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
2370	#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
2371	#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
2372	#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
2373	#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
2374
2375	/* PORTA - Port A */
2376	#define PORTA_DIR _SFR_MEM8(0x0600)
2377	#define PORTA_DIRSET _SFR_MEM8(0x0601)
2378	#define PORTA_DIRCLR _SFR_MEM8(0x0602)
2379	#define PORTA_DIRTGL _SFR_MEM8(0x0603)
2380	#define PORTA_OUT _SFR_MEM8(0x0604)
2381	#define PORTA_OUTSET _SFR_MEM8(0x0605)
2382	#define PORTA_OUTCLR _SFR_MEM8(0x0606)
2383	#define PORTA_OUTTGL _SFR_MEM8(0x0607)
2384	#define PORTA_IN _SFR_MEM8(0x0608)
2385	#define PORTA_INTCTRL _SFR_MEM8(0x0609)
2386	#define PORTA_INT0MASK _SFR_MEM8(0x060A)
2387	#define PORTA_INT1MASK _SFR_MEM8(0x060B)
2388	#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
2389	#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
2390	#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
2391	#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
2392	#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
2393	#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
2394	#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
2395	#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
2396	#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
2397
2398	/* PORTB - Port B */
2399	#define PORTB_DIR _SFR_MEM8(0x0620)
2400	#define PORTB_DIRSET _SFR_MEM8(0x0621)
2401	#define PORTB_DIRCLR _SFR_MEM8(0x0622)
2402	#define PORTB_DIRTGL _SFR_MEM8(0x0623)
2403	#define PORTB_OUT _SFR_MEM8(0x0624)
2404	#define PORTB_OUTSET _SFR_MEM8(0x0625)
2405	#define PORTB_OUTCLR _SFR_MEM8(0x0626)
2406	#define PORTB_OUTTGL _SFR_MEM8(0x0627)
2407	#define PORTB_IN _SFR_MEM8(0x0628)
2408	#define PORTB_INTCTRL _SFR_MEM8(0x0629)
2409	#define PORTB_INT0MASK _SFR_MEM8(0x062A)
2410	#define PORTB_INT1MASK _SFR_MEM8(0x062B)
2411	#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
2412	#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
2413	#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
2414	#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
2415	#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
2416	#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
2417	#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
2418	#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
2419	#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
2420
2421	/* PORTC - Port C */
2422	#define PORTC_DIR _SFR_MEM8(0x0640)
2423	#define PORTC_DIRSET _SFR_MEM8(0x0641)
2424	#define PORTC_DIRCLR _SFR_MEM8(0x0642)
2425	#define PORTC_DIRTGL _SFR_MEM8(0x0643)
2426	#define PORTC_OUT _SFR_MEM8(0x0644)
2427	#define PORTC_OUTSET _SFR_MEM8(0x0645)
2428	#define PORTC_OUTCLR _SFR_MEM8(0x0646)
2429	#define PORTC_OUTTGL _SFR_MEM8(0x0647)
2430	#define PORTC_IN _SFR_MEM8(0x0648)
2431	#define PORTC_INTCTRL _SFR_MEM8(0x0649)
2432	#define PORTC_INT0MASK _SFR_MEM8(0x064A)
2433	#define PORTC_INT1MASK _SFR_MEM8(0x064B)
2434	#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
2435	#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
2436	#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
2437	#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
2438	#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
2439	#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
2440	#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
2441	#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
2442	#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
2443
2444	/* PORTD - Port D */
2445	#define PORTD_DIR _SFR_MEM8(0x0660)
2446	#define PORTD_DIRSET _SFR_MEM8(0x0661)
2447	#define PORTD_DIRCLR _SFR_MEM8(0x0662)
2448	#define PORTD_DIRTGL _SFR_MEM8(0x0663)
2449	#define PORTD_OUT _SFR_MEM8(0x0664)
2450	#define PORTD_OUTSET _SFR_MEM8(0x0665)
2451	#define PORTD_OUTCLR _SFR_MEM8(0x0666)
2452	#define PORTD_OUTTGL _SFR_MEM8(0x0667)
2453	#define PORTD_IN _SFR_MEM8(0x0668)
2454	#define PORTD_INTCTRL _SFR_MEM8(0x0669)
2455	#define PORTD_INT0MASK _SFR_MEM8(0x066A)
2456	#define PORTD_INT1MASK _SFR_MEM8(0x066B)
2457	#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
2458	#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
2459	#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
2460	#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
2461	#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
2462	#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
2463	#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
2464	#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
2465	#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
2466
2467	/* PORTE - Port E */
2468	#define PORTE_DIR _SFR_MEM8(0x0680)
2469	#define PORTE_DIRSET _SFR_MEM8(0x0681)
2470	#define PORTE_DIRCLR _SFR_MEM8(0x0682)
2471	#define PORTE_DIRTGL _SFR_MEM8(0x0683)
2472	#define PORTE_OUT _SFR_MEM8(0x0684)
2473	#define PORTE_OUTSET _SFR_MEM8(0x0685)
2474	#define PORTE_OUTCLR _SFR_MEM8(0x0686)
2475	#define PORTE_OUTTGL _SFR_MEM8(0x0687)
2476	#define PORTE_IN _SFR_MEM8(0x0688)
2477	#define PORTE_INTCTRL _SFR_MEM8(0x0689)
2478	#define PORTE_INT0MASK _SFR_MEM8(0x068A)
2479	#define PORTE_INT1MASK _SFR_MEM8(0x068B)
2480	#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
2481	#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
2482	#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
2483	#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
2484	#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
2485	#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
2486	#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
2487	#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
2488	#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
2489
2490	/* PORTF - Port F */
2491	#define PORTF_DIR _SFR_MEM8(0x06A0)
2492	#define PORTF_DIRSET _SFR_MEM8(0x06A1)
2493	#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
2494	#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
2495	#define PORTF_OUT _SFR_MEM8(0x06A4)
2496	#define PORTF_OUTSET _SFR_MEM8(0x06A5)
2497	#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
2498	#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
2499	#define PORTF_IN _SFR_MEM8(0x06A8)
2500	#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
2501	#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
2502	#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
2503	#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
2504	#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
2505	#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
2506	#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
2507	#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
2508	#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
2509	#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
2510	#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
2511	#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
2512
2513	/* PORTR - Port R */
2514	#define PORTR_DIR _SFR_MEM8(0x07E0)
2515	#define PORTR_DIRSET _SFR_MEM8(0x07E1)
2516	#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
2517	#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
2518	#define PORTR_OUT _SFR_MEM8(0x07E4)
2519	#define PORTR_OUTSET _SFR_MEM8(0x07E5)
2520	#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
2521	#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
2522	#define PORTR_IN _SFR_MEM8(0x07E8)
2523	#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
2524	#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
2525	#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
2526	#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
2527	#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
2528	#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
2529	#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
2530	#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
2531	#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
2532	#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
2533	#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
2534	#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
2535
2536	/* TCC0 - Timer/Counter C0 */
2537	#define TCC0_CTRLA _SFR_MEM8(0x0800)
2538	#define TCC0_CTRLB _SFR_MEM8(0x0801)
2539	#define TCC0_CTRLC _SFR_MEM8(0x0802)
2540	#define TCC0_CTRLD _SFR_MEM8(0x0803)
2541	#define TCC0_CTRLE _SFR_MEM8(0x0804)
2542	#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
2543	#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
2544	#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
2545	#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
2546	#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
2547	#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
2548	#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
2549	#define TCC0_TEMP _SFR_MEM8(0x080F)
2550	#define TCC0_CNT _SFR_MEM16(0x0820)
2551	#define TCC0_PER _SFR_MEM16(0x0826)
2552	#define TCC0_CCA _SFR_MEM16(0x0828)
2553	#define TCC0_CCB _SFR_MEM16(0x082A)
2554	#define TCC0_CCC _SFR_MEM16(0x082C)
2555	#define TCC0_CCD _SFR_MEM16(0x082E)
2556	#define TCC0_PERBUF _SFR_MEM16(0x0836)
2557	#define TCC0_CCABUF _SFR_MEM16(0x0838)
2558	#define TCC0_CCBBUF _SFR_MEM16(0x083A)
2559	#define TCC0_CCCBUF _SFR_MEM16(0x083C)
2560	#define TCC0_CCDBUF _SFR_MEM16(0x083E)
2561
2562	/* TCC1 - Timer/Counter C1 */
2563	#define TCC1_CTRLA _SFR_MEM8(0x0840)
2564	#define TCC1_CTRLB _SFR_MEM8(0x0841)
2565	#define TCC1_CTRLC _SFR_MEM8(0x0842)
2566	#define TCC1_CTRLD _SFR_MEM8(0x0843)
2567	#define TCC1_CTRLE _SFR_MEM8(0x0844)
2568	#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
2569	#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
2570	#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
2571	#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
2572	#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
2573	#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
2574	#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
2575	#define TCC1_TEMP _SFR_MEM8(0x084F)
2576	#define TCC1_CNT _SFR_MEM16(0x0860)
2577	#define TCC1_PER _SFR_MEM16(0x0866)
2578	#define TCC1_CCA _SFR_MEM16(0x0868)
2579	#define TCC1_CCB _SFR_MEM16(0x086A)
2580	#define TCC1_PERBUF _SFR_MEM16(0x0876)
2581	#define TCC1_CCABUF _SFR_MEM16(0x0878)
2582	#define TCC1_CCBBUF _SFR_MEM16(0x087A)
2583
2584	/* AWEXC - Advanced Waveform Extension C */
2585	#define AWEXC_CTRL _SFR_MEM8(0x0880)
2586	#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
2587	#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
2588	#define AWEXC_STATUS _SFR_MEM8(0x0884)
2589	#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
2590	#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
2591	#define AWEXC_DTLS _SFR_MEM8(0x0888)
2592	#define AWEXC_DTHS _SFR_MEM8(0x0889)
2593	#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
2594	#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
2595	#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
2596
2597	/* HIRESC - High-Resolution Extension C */
2598	#define HIRESC_CTRLA _SFR_MEM8(0x0890)
2599
2600	/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2601	#define USARTC0_DATA _SFR_MEM8(0x08A0)
2602	#define USARTC0_STATUS _SFR_MEM8(0x08A1)
2603	#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
2604	#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
2605	#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
2606	#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
2607	#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
2608
2609	/* SPIC - Serial Peripheral Interface C */
2610	#define SPIC_CTRL _SFR_MEM8(0x08C0)
2611	#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
2612	#define SPIC_STATUS _SFR_MEM8(0x08C2)
2613	#define SPIC_DATA _SFR_MEM8(0x08C3)
2614
2615	/* IRCOM - IR Communication Module */
2616	#define IRCOM_CTRL _SFR_MEM8(0x08F8)
2617	#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
2618	#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
2619
2620	/* TCD0 - Timer/Counter D0 */
2621	#define TCD0_CTRLA _SFR_MEM8(0x0900)
2622	#define TCD0_CTRLB _SFR_MEM8(0x0901)
2623	#define TCD0_CTRLC _SFR_MEM8(0x0902)
2624	#define TCD0_CTRLD _SFR_MEM8(0x0903)
2625	#define TCD0_CTRLE _SFR_MEM8(0x0904)
2626	#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
2627	#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
2628	#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
2629	#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
2630	#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
2631	#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
2632	#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
2633	#define TCD0_TEMP _SFR_MEM8(0x090F)
2634	#define TCD0_CNT _SFR_MEM16(0x0920)
2635	#define TCD0_PER _SFR_MEM16(0x0926)
2636	#define TCD0_CCA _SFR_MEM16(0x0928)
2637	#define TCD0_CCB _SFR_MEM16(0x092A)
2638	#define TCD0_CCC _SFR_MEM16(0x092C)
2639	#define TCD0_CCD _SFR_MEM16(0x092E)
2640	#define TCD0_PERBUF _SFR_MEM16(0x0936)
2641	#define TCD0_CCABUF _SFR_MEM16(0x0938)
2642	#define TCD0_CCBBUF _SFR_MEM16(0x093A)
2643	#define TCD0_CCCBUF _SFR_MEM16(0x093C)
2644	#define TCD0_CCDBUF _SFR_MEM16(0x093E)
2645
2646	/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2647	#define USARTD0_DATA _SFR_MEM8(0x09A0)
2648	#define USARTD0_STATUS _SFR_MEM8(0x09A1)
2649	#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
2650	#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
2651	#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
2652	#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
2653	#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
2654
2655	/* SPID - Serial Peripheral Interface D */
2656	#define SPID_CTRL _SFR_MEM8(0x09C0)
2657	#define SPID_INTCTRL _SFR_MEM8(0x09C1)
2658	#define SPID_STATUS _SFR_MEM8(0x09C2)
2659	#define SPID_DATA _SFR_MEM8(0x09C3)
2660
2661	/* TCE0 - Timer/Counter E0 */
2662	#define TCE0_CTRLA _SFR_MEM8(0x0A00)
2663	#define TCE0_CTRLB _SFR_MEM8(0x0A01)
2664	#define TCE0_CTRLC _SFR_MEM8(0x0A02)
2665	#define TCE0_CTRLD _SFR_MEM8(0x0A03)
2666	#define TCE0_CTRLE _SFR_MEM8(0x0A04)
2667	#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
2668	#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
2669	#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
2670	#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
2671	#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
2672	#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
2673	#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
2674	#define TCE0_TEMP _SFR_MEM8(0x0A0F)
2675	#define TCE0_CNT _SFR_MEM16(0x0A20)
2676	#define TCE0_PER _SFR_MEM16(0x0A26)
2677	#define TCE0_CCA _SFR_MEM16(0x0A28)
2678	#define TCE0_CCB _SFR_MEM16(0x0A2A)
2679	#define TCE0_CCC _SFR_MEM16(0x0A2C)
2680	#define TCE0_CCD _SFR_MEM16(0x0A2E)
2681	#define TCE0_PERBUF _SFR_MEM16(0x0A36)
2682	#define TCE0_CCABUF _SFR_MEM16(0x0A38)
2683	#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
2684	#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
2685	#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
2686
2687	/* AWEXE - Advanced Waveform Extension E */
2688	#define AWEXE_CTRL _SFR_MEM8(0x0A80)
2689	#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
2690	#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
2691	#define AWEXE_STATUS _SFR_MEM8(0x0A84)
2692	#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
2693	#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
2694	#define AWEXE_DTLS _SFR_MEM8(0x0A88)
2695	#define AWEXE_DTHS _SFR_MEM8(0x0A89)
2696	#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
2697	#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
2698	#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
2699
2700	/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
2701	#define USARTE0_DATA _SFR_MEM8(0x0AA0)
2702	#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
2703	#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
2704	#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
2705	#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
2706	#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
2707	#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
2708
2709	/* SPIE - Serial Peripheral Interface E */
2710	#define SPIE_CTRL _SFR_MEM8(0x0AC0)
2711	#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
2712	#define SPIE_STATUS _SFR_MEM8(0x0AC2)
2713	#define SPIE_DATA _SFR_MEM8(0x0AC3)
2714
2715	/* TCF0 - Timer/Counter F0 */
2716	#define TCF0_CTRLA _SFR_MEM8(0x0B00)
2717	#define TCF0_CTRLB _SFR_MEM8(0x0B01)
2718	#define TCF0_CTRLC _SFR_MEM8(0x0B02)
2719	#define TCF0_CTRLD _SFR_MEM8(0x0B03)
2720	#define TCF0_CTRLE _SFR_MEM8(0x0B04)
2721	#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
2722	#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
2723	#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
2724	#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
2725	#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
2726	#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
2727	#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
2728	#define TCF0_TEMP _SFR_MEM8(0x0B0F)
2729	#define TCF0_CNT _SFR_MEM16(0x0B20)
2730	#define TCF0_PER _SFR_MEM16(0x0B26)
2731	#define TCF0_CCA _SFR_MEM16(0x0B28)
2732	#define TCF0_CCB _SFR_MEM16(0x0B2A)
2733	#define TCF0_CCC _SFR_MEM16(0x0B2C)
2734	#define TCF0_CCD _SFR_MEM16(0x0B2E)
2735	#define TCF0_PERBUF _SFR_MEM16(0x0B36)
2736	#define TCF0_CCABUF _SFR_MEM16(0x0B38)
2737	#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
2738	#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
2739	#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
2740
2741
2742
2743	/================== Bitfield Definitions ================== /
2744
2745	/* XOCD - On-Chip Debug System */
2746	/* OCD.OCDR1 bit masks and bit positions */
2747	#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
2748	#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
2749
2750
2751	/* CPU - CPU */
2752	/* CPU.CCP bit masks and bit positions */
2753	#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
2754	#define CPU_CCP_gp 0 /* CCP signature group position. */
2755	#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
2756	#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
2757	#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
2758	#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
2759	#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
2760	#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
2761	#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
2762	#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
2763	#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
2764	#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
2765	#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
2766	#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
2767	#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
2768	#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
2769	#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
2770	#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
2771
2772
2773	/* CPU.SREG bit masks and bit positions */
2774	#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
2775	#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
2776
2777	#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
2778	#define CPU_T_bp 6 /* Transfer Bit bit position. */
2779
2780	#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
2781	#define CPU_H_bp 5 /* Half Carry Flag bit position. */
2782
2783	#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
2784	#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
2785
2786	#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
2787	#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
2788
2789	#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
2790	#define CPU_N_bp 2 /* Negative Flag bit position. */
2791
2792	#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
2793	#define CPU_Z_bp 1 /* Zero Flag bit position. */
2794
2795	#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
2796	#define CPU_C_bp 0 /* Carry Flag bit position. */
2797
2798
2799	/* CLK - Clock System */
2800	/* CLK.CTRL bit masks and bit positions */
2801	#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
2802	#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
2803	#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
2804	#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
2805	#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
2806	#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
2807	#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
2808	#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
2809
2810
2811	/* CLK.PSCTRL bit masks and bit positions */
2812	#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
2813	#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
2814	#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
2815	#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
2816	#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
2817	#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
2818	#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
2819	#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
2820	#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
2821	#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
2822	#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
2823	#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
2824
2825	#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
2826	#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
2827	#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
2828	#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
2829	#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
2830	#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
2831
2832
2833	/* CLK.LOCK bit masks and bit positions */
2834	#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
2835	#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
2836
2837
2838	/* CLK.RTCCTRL bit masks and bit positions */
2839	#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
2840	#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
2841	#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
2842	#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
2843	#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
2844	#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
2845	#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
2846	#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
2847
2848	#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
2849	#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
2850
2851
2852	/* SLEEP - Sleep Controller */
2853	/* SLEEP.CTRL bit masks and bit positions */
2854	#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
2855	#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
2856	#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
2857	#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
2858	#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
2859	#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
2860	#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
2861	#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
2862
2863	#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
2864	#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
2865
2866
2867	/* OSC - Oscillator */
2868	/* OSC.CTRL bit masks and bit positions */
2869	#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
2870	#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
2871
2872	#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
2873	#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
2874
2875	#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
2876	#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
2877
2878	#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
2879	#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
2880
2881	#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
2882	#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
2883
2884
2885	/* OSC.STATUS bit masks and bit positions */
2886	#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
2887	#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
2888
2889	#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
2890	#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
2891
2892	#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
2893	#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
2894
2895	#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
2896	#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
2897
2898	#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
2899	#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
2900
2901
2902	/* OSC.XOSCCTRL bit masks and bit positions */
2903	#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
2904	#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
2905	#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
2906	#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
2907	#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
2908	#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
2909
2910	#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
2911	#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
2912
2913	#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
2914	#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
2915	#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
2916	#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
2917	#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
2918	#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
2919	#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
2920	#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
2921	#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
2922	#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
2923
2924
2925	/* OSC.XOSCFAIL bit masks and bit positions */
2926	#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
2927	#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
2928
2929	#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
2930	#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
2931
2932
2933	/* OSC.PLLCTRL bit masks and bit positions */
2934	#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
2935	#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
2936	#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
2937	#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
2938	#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
2939	#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
2940
2941	#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
2942	#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
2943	#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
2944	#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
2945	#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
2946	#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
2947	#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
2948	#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
2949	#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
2950	#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
2951	#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
2952	#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
2953
2954
2955	/* OSC.DFLLCTRL bit masks and bit positions */
2956	#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
2957	#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
2958
2959	#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
2960	#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
2961
2962
2963	/* DFLL - DFLL */
2964	/* DFLL.CTRL bit masks and bit positions */
2965	#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
2966	#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
2967
2968
2969	/* DFLL.CALA bit masks and bit positions */
2970	#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
2971	#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
2972	#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
2973	#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
2974	#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
2975	#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
2976	#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
2977	#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
2978	#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
2979	#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
2980	#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
2981	#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
2982	#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
2983	#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
2984	#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
2985	#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
2986
2987
2988	/* DFLL.CALB bit masks and bit positions */
2989	#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
2990	#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
2991	#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
2992	#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
2993	#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
2994	#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
2995	#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
2996	#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
2997	#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
2998	#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
2999	#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
3000	#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
3001	#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
3002	#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
3003
3004
3005	/* RST - Reset */
3006	/* RST.STATUS bit masks and bit positions */
3007	#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
3008	#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
3009
3010	#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
3011	#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
3012
3013	#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
3014	#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
3015
3016	#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
3017	#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
3018
3019	#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
3020	#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
3021
3022	#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
3023	#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
3024
3025	#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
3026	#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
3027
3028
3029	/* RST.CTRL bit masks and bit positions */
3030	#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
3031	#define RST_SWRST_bp 0 /* Software Reset bit position. */
3032
3033
3034	/* WDT - Watch-Dog Timer */
3035	/* WDT.CTRL bit masks and bit positions */
3036	#define WDT_PER_gm 0x3C /* Period group mask. */
3037	#define WDT_PER_gp 2 /* Period group position. */
3038	#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
3039	#define WDT_PER0_bp 2 /* Period bit 0 position. */
3040	#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
3041	#define WDT_PER1_bp 3 /* Period bit 1 position. */
3042	#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
3043	#define WDT_PER2_bp 4 /* Period bit 2 position. */
3044	#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
3045	#define WDT_PER3_bp 5 /* Period bit 3 position. */
3046
3047	#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
3048	#define WDT_ENABLE_bp 1 /* Enable bit position. */
3049
3050	#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
3051	#define WDT_CEN_bp 0 /* Change Enable bit position. */
3052
3053
3054	/* WDT.WINCTRL bit masks and bit positions */
3055	#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
3056	#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
3057	#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
3058	#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
3059	#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
3060	#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
3061	#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
3062	#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
3063	#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
3064	#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
3065
3066	#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
3067	#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
3068
3069	#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
3070	#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
3071
3072
3073	/* WDT.STATUS bit masks and bit positions */
3074	#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
3075	#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
3076
3077
3078	/* MCU - MCU Control */
3079	/* MCU.MCUCR bit masks and bit positions */
3080	#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
3081	#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
3082
3083
3084	/* MCU.EVSYSLOCK bit masks and bit positions */
3085	#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
3086	#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
3087
3088	#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
3089	#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
3090
3091
3092	/* MCU.AWEXLOCK bit masks and bit positions */
3093	#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
3094	#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
3095
3096	#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
3097	#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
3098
3099
3100	/* PMIC - Programmable Multi-level Interrupt Controller */
3101	/* PMIC.STATUS bit masks and bit positions */
3102	#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
3103	#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
3104
3105	#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
3106	#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
3107
3108	#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
3109	#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
3110
3111	#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
3112	#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
3113
3114
3115	/* PMIC.CTRL bit masks and bit positions */
3116	#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
3117	#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
3118
3119	#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
3120	#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
3121
3122	#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
3123	#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
3124
3125	#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
3126	#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
3127
3128	#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
3129	#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
3130
3131
3132	/* EVSYS - Event System */
3133	/* EVSYS.CH0MUX bit masks and bit positions */
3134	#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
3135	#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
3136	#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
3137	#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
3138	#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
3139	#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
3140	#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
3141	#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
3142	#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
3143	#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
3144	#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
3145	#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
3146	#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
3147	#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
3148	#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
3149	#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
3150	#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
3151	#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
3152
3153
3154	/* EVSYS.CH1MUX bit masks and bit positions */
3155	/* EVSYS_CHMUX_gm Predefined. */
3156	/* EVSYS_CHMUX_gp Predefined. */
3157	/* EVSYS_CHMUX0_bm Predefined. */
3158	/* EVSYS_CHMUX0_bp Predefined. */
3159	/* EVSYS_CHMUX1_bm Predefined. */
3160	/* EVSYS_CHMUX1_bp Predefined. */
3161	/* EVSYS_CHMUX2_bm Predefined. */
3162	/* EVSYS_CHMUX2_bp Predefined. */
3163	/* EVSYS_CHMUX3_bm Predefined. */
3164	/* EVSYS_CHMUX3_bp Predefined. */
3165	/* EVSYS_CHMUX4_bm Predefined. */
3166	/* EVSYS_CHMUX4_bp Predefined. */
3167	/* EVSYS_CHMUX5_bm Predefined. */
3168	/* EVSYS_CHMUX5_bp Predefined. */
3169	/* EVSYS_CHMUX6_bm Predefined. */
3170	/* EVSYS_CHMUX6_bp Predefined. */
3171	/* EVSYS_CHMUX7_bm Predefined. */
3172	/* EVSYS_CHMUX7_bp Predefined. */
3173
3174
3175	/* EVSYS.CH2MUX bit masks and bit positions */
3176	/* EVSYS_CHMUX_gm Predefined. */
3177	/* EVSYS_CHMUX_gp Predefined. */
3178	/* EVSYS_CHMUX0_bm Predefined. */
3179	/* EVSYS_CHMUX0_bp Predefined. */
3180	/* EVSYS_CHMUX1_bm Predefined. */
3181	/* EVSYS_CHMUX1_bp Predefined. */
3182	/* EVSYS_CHMUX2_bm Predefined. */
3183	/* EVSYS_CHMUX2_bp Predefined. */
3184	/* EVSYS_CHMUX3_bm Predefined. */
3185	/* EVSYS_CHMUX3_bp Predefined. */
3186	/* EVSYS_CHMUX4_bm Predefined. */
3187	/* EVSYS_CHMUX4_bp Predefined. */
3188	/* EVSYS_CHMUX5_bm Predefined. */
3189	/* EVSYS_CHMUX5_bp Predefined. */
3190	/* EVSYS_CHMUX6_bm Predefined. */
3191	/* EVSYS_CHMUX6_bp Predefined. */
3192	/* EVSYS_CHMUX7_bm Predefined. */
3193	/* EVSYS_CHMUX7_bp Predefined. */
3194
3195
3196	/* EVSYS.CH3MUX bit masks and bit positions */
3197	/* EVSYS_CHMUX_gm Predefined. */
3198	/* EVSYS_CHMUX_gp Predefined. */
3199	/* EVSYS_CHMUX0_bm Predefined. */
3200	/* EVSYS_CHMUX0_bp Predefined. */
3201	/* EVSYS_CHMUX1_bm Predefined. */
3202	/* EVSYS_CHMUX1_bp Predefined. */
3203	/* EVSYS_CHMUX2_bm Predefined. */
3204	/* EVSYS_CHMUX2_bp Predefined. */
3205	/* EVSYS_CHMUX3_bm Predefined. */
3206	/* EVSYS_CHMUX3_bp Predefined. */
3207	/* EVSYS_CHMUX4_bm Predefined. */
3208	/* EVSYS_CHMUX4_bp Predefined. */
3209	/* EVSYS_CHMUX5_bm Predefined. */
3210	/* EVSYS_CHMUX5_bp Predefined. */
3211	/* EVSYS_CHMUX6_bm Predefined. */
3212	/* EVSYS_CHMUX6_bp Predefined. */
3213	/* EVSYS_CHMUX7_bm Predefined. */
3214	/* EVSYS_CHMUX7_bp Predefined. */
3215
3216
3217	/* EVSYS.CH0CTRL bit masks and bit positions */
3218	#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
3219	#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
3220	#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3221	#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3222	#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3223	#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3224
3225	#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
3226	#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
3227
3228	#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
3229	#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
3230
3231	#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
3232	#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
3233	#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
3234	#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
3235	#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
3236	#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
3237	#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
3238	#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
3239
3240
3241	/* EVSYS.CH1CTRL bit masks and bit positions */
3242	/* EVSYS_DIGFILT_gm Predefined. */
3243	/* EVSYS_DIGFILT_gp Predefined. */
3244	/* EVSYS_DIGFILT0_bm Predefined. */
3245	/* EVSYS_DIGFILT0_bp Predefined. */
3246	/* EVSYS_DIGFILT1_bm Predefined. */
3247	/* EVSYS_DIGFILT1_bp Predefined. */
3248	/* EVSYS_DIGFILT2_bm Predefined. */
3249	/* EVSYS_DIGFILT2_bp Predefined. */
3250
3251
3252	/* EVSYS.CH2CTRL bit masks and bit positions */
3253	/* EVSYS_QDIRM_gm Predefined. */
3254	/* EVSYS_QDIRM_gp Predefined. */
3255	/* EVSYS_QDIRM0_bm Predefined. */
3256	/* EVSYS_QDIRM0_bp Predefined. */
3257	/* EVSYS_QDIRM1_bm Predefined. */
3258	/* EVSYS_QDIRM1_bp Predefined. */
3259
3260	/* EVSYS_QDIEN_bm Predefined. */
3261	/* EVSYS_QDIEN_bp Predefined. */
3262
3263	/* EVSYS_QDEN_bm Predefined. */
3264	/* EVSYS_QDEN_bp Predefined. */
3265
3266	/* EVSYS_DIGFILT_gm Predefined. */
3267	/* EVSYS_DIGFILT_gp Predefined. */
3268	/* EVSYS_DIGFILT0_bm Predefined. */
3269	/* EVSYS_DIGFILT0_bp Predefined. */
3270	/* EVSYS_DIGFILT1_bm Predefined. */
3271	/* EVSYS_DIGFILT1_bp Predefined. */
3272	/* EVSYS_DIGFILT2_bm Predefined. */
3273	/* EVSYS_DIGFILT2_bp Predefined. */
3274
3275
3276	/* EVSYS.CH3CTRL bit masks and bit positions */
3277	/* EVSYS_DIGFILT_gm Predefined. */
3278	/* EVSYS_DIGFILT_gp Predefined. */
3279	/* EVSYS_DIGFILT0_bm Predefined. */
3280	/* EVSYS_DIGFILT0_bp Predefined. */
3281	/* EVSYS_DIGFILT1_bm Predefined. */
3282	/* EVSYS_DIGFILT1_bp Predefined. */
3283	/* EVSYS_DIGFILT2_bm Predefined. */
3284	/* EVSYS_DIGFILT2_bp Predefined. */
3285
3286
3287	/* NVM - Non Volatile Memory Controller */
3288	/* NVM.CMD bit masks and bit positions */
3289	#define NVM_CMD_gm 0xFF /* Command group mask. */
3290	#define NVM_CMD_gp 0 /* Command group position. */
3291	#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
3292	#define NVM_CMD0_bp 0 /* Command bit 0 position. */
3293	#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
3294	#define NVM_CMD1_bp 1 /* Command bit 1 position. */
3295	#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
3296	#define NVM_CMD2_bp 2 /* Command bit 2 position. */
3297	#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
3298	#define NVM_CMD3_bp 3 /* Command bit 3 position. */
3299	#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
3300	#define NVM_CMD4_bp 4 /* Command bit 4 position. */
3301	#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
3302	#define NVM_CMD5_bp 5 /* Command bit 5 position. */
3303	#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
3304	#define NVM_CMD6_bp 6 /* Command bit 6 position. */
3305	#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
3306	#define NVM_CMD7_bp 7 /* Command bit 7 position. */
3307
3308
3309	/* NVM.CTRLA bit masks and bit positions */
3310	#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
3311	#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
3312
3313
3314	/* NVM.CTRLB bit masks and bit positions */
3315	#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
3316	#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
3317
3318	#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
3319	#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
3320
3321	#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
3322	#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
3323
3324	#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
3325	#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
3326
3327
3328	/* NVM.INTCTRL bit masks and bit positions */
3329	#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
3330	#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
3331	#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
3332	#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
3333	#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
3334	#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
3335
3336	#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
3337	#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
3338	#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
3339	#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
3340	#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
3341	#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
3342
3343
3344	/* NVM.STATUS bit masks and bit positions */
3345	#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
3346	#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
3347
3348	#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
3349	#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
3350
3351	#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
3352	#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
3353
3354	#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
3355	#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
3356
3357
3358	/* NVM.LOCKBITS bit masks and bit positions */
3359	#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3360	#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3361	#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3362	#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3363	#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3364	#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3365
3366	#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3367	#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3368	#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3369	#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3370	#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3371	#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3372
3373	#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3374	#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3375	#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3376	#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3377	#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3378	#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3379
3380	#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
3381	#define NVM_LB_gp 0 /* Lock Bits group position. */
3382	#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3383	#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
3384	#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3385	#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
3386
3387
3388	/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
3389	#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3390	#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3391	#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3392	#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3393	#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3394	#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3395
3396	#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3397	#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3398	#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3399	#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3400	#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3401	#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3402
3403	#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3404	#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3405	#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3406	#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3407	#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3408	#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3409
3410	#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
3411	#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
3412	#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3413	#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
3414	#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3415	#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
3416
3417
3418	/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
3419	#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
3420	#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
3421	#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
3422	#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
3423	#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
3424	#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
3425	#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
3426	#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
3427	#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
3428	#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
3429	#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
3430	#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
3431	#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
3432	#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
3433	#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
3434	#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
3435	#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
3436	#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
3437
3438
3439	/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
3440	#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
3441	#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
3442	#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
3443	#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
3444	#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
3445	#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
3446	#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
3447	#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
3448	#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
3449	#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
3450
3451	#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
3452	#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
3453	#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
3454	#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
3455	#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
3456	#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
3457	#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
3458	#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
3459	#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
3460	#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
3461
3462
3463	/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
3464	#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
3465	#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
3466
3467	#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
3468	#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
3469
3470	#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
3471	#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
3472	#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
3473	#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
3474	#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
3475	#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
3476
3477
3478	/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
3479	#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */
3480	#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */
3481
3482	#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
3483	#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
3484	#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
3485	#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
3486	#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
3487	#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
3488
3489	#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
3490	#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
3491
3492
3493	/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
3494	#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
3495	#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
3496	#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
3497	#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
3498	#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
3499	#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
3500
3501	#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
3502	#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
3503
3504	#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
3505	#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
3506	#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
3507	#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
3508	#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
3509	#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
3510	#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
3511	#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
3512
3513
3514	/* AC - Analog Comparator */
3515	/* AC.AC0CTRL bit masks and bit positions */
3516	#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
3517	#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
3518	#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
3519	#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
3520	#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
3521	#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
3522
3523	#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
3524	#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
3525	#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
3526	#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
3527	#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
3528	#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
3529
3530	#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
3531	#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
3532
3533	#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
3534	#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
3535	#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
3536	#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
3537	#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
3538	#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
3539
3540	#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
3541	#define AC_ENABLE_bp 0 /* Enable bit position. */
3542
3543
3544	/* AC.AC1CTRL bit masks and bit positions */
3545	/* AC_INTMODE_gm Predefined. */
3546	/* AC_INTMODE_gp Predefined. */
3547	/* AC_INTMODE0_bm Predefined. */
3548	/* AC_INTMODE0_bp Predefined. */
3549	/* AC_INTMODE1_bm Predefined. */
3550	/* AC_INTMODE1_bp Predefined. */
3551
3552	/* AC_INTLVL_gm Predefined. */
3553	/* AC_INTLVL_gp Predefined. */
3554	/* AC_INTLVL0_bm Predefined. */
3555	/* AC_INTLVL0_bp Predefined. */
3556	/* AC_INTLVL1_bm Predefined. */
3557	/* AC_INTLVL1_bp Predefined. */
3558
3559	/* AC_HSMODE_bm Predefined. */
3560	/* AC_HSMODE_bp Predefined. */
3561
3562	/* AC_HYSMODE_gm Predefined. */
3563	/* AC_HYSMODE_gp Predefined. */
3564	/* AC_HYSMODE0_bm Predefined. */
3565	/* AC_HYSMODE0_bp Predefined. */
3566	/* AC_HYSMODE1_bm Predefined. */
3567	/* AC_HYSMODE1_bp Predefined. */
3568
3569	/* AC_ENABLE_bm Predefined. */
3570	/* AC_ENABLE_bp Predefined. */
3571
3572
3573	/* AC.AC0MUXCTRL bit masks and bit positions */
3574	#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
3575	#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
3576	#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
3577	#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
3578	#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
3579	#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
3580	#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
3581	#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
3582
3583	#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
3584	#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
3585	#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
3586	#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
3587	#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
3588	#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
3589	#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
3590	#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
3591
3592
3593	/* AC.AC1MUXCTRL bit masks and bit positions */
3594	/* AC_MUXPOS_gm Predefined. */
3595	/* AC_MUXPOS_gp Predefined. */
3596	/* AC_MUXPOS0_bm Predefined. */
3597	/* AC_MUXPOS0_bp Predefined. */
3598	/* AC_MUXPOS1_bm Predefined. */
3599	/* AC_MUXPOS1_bp Predefined. */
3600	/* AC_MUXPOS2_bm Predefined. */
3601	/* AC_MUXPOS2_bp Predefined. */
3602
3603	/* AC_MUXNEG_gm Predefined. */
3604	/* AC_MUXNEG_gp Predefined. */
3605	/* AC_MUXNEG0_bm Predefined. */
3606	/* AC_MUXNEG0_bp Predefined. */
3607	/* AC_MUXNEG1_bm Predefined. */
3608	/* AC_MUXNEG1_bp Predefined. */
3609	/* AC_MUXNEG2_bm Predefined. */
3610	/* AC_MUXNEG2_bp Predefined. */
3611
3612
3613	/* AC.CTRLA bit masks and bit positions */
3614	#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
3615	#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
3616
3617
3618	/* AC.CTRLB bit masks and bit positions */
3619	#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
3620	#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
3621	#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
3622	#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
3623	#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
3624	#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
3625	#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
3626	#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
3627	#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
3628	#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
3629	#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
3630	#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
3631	#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
3632	#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
3633
3634
3635	/* AC.WINCTRL bit masks and bit positions */
3636	#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
3637	#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
3638
3639	#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
3640	#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
3641	#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
3642	#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
3643	#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
3644	#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
3645
3646	#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
3647	#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
3648	#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
3649	#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
3650	#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
3651	#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
3652
3653
3654	/* AC.STATUS bit masks and bit positions */
3655	#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
3656	#define AC_WSTATE_gp 6 /* Window Mode State group position. */
3657	#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
3658	#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
3659	#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
3660	#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
3661
3662	#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
3663	#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
3664
3665	#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
3666	#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
3667
3668	#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
3669	#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
3670
3671	#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
3672	#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
3673
3674	#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
3675	#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
3676
3677
3678	/* ADC - Analog/Digital Converter */
3679	/* ADC_CH.CTRL bit masks and bit positions */
3680	#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
3681	#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
3682
3683	#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
3684	#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
3685	#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
3686	#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
3687	#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
3688	#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
3689	#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
3690	#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
3691
3692	#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
3693	#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
3694	#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
3695	#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
3696	#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
3697	#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
3698
3699
3700	/* ADC_CH.MUXCTRL bit masks and bit positions */
3701	#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
3702	#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
3703	#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
3704	#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
3705	#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
3706	#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
3707	#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
3708	#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
3709	#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
3710	#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
3711
3712	#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
3713	#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
3714	#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
3715	#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
3716	#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
3717	#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
3718
3719
3720	/* ADC_CH.INTCTRL bit masks and bit positions */
3721	#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
3722	#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
3723	#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
3724	#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
3725	#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
3726	#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
3727
3728	#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
3729	#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
3730	#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
3731	#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
3732	#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
3733	#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
3734
3735
3736	/* ADC_CH.INTFLAGS bit masks and bit positions */
3737	#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
3738	#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
3739
3740
3741	/* ADC.CTRLA bit masks and bit positions */
3742	#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
3743	#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
3744
3745	#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */
3746	#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */
3747
3748	#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
3749	#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
3750
3751
3752	/* ADC.CTRLB bit masks and bit positions */
3753	#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
3754	#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
3755
3756	#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
3757	#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
3758
3759	#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
3760	#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
3761	#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
3762	#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
3763	#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
3764	#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
3765
3766
3767	/* ADC.REFCTRL bit masks and bit positions */
3768	#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */
3769	#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
3770	#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
3771	#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
3772	#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
3773	#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
3774	#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */
3775	#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */
3776
3777	#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
3778	#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
3779
3780	#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
3781	#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
3782
3783
3784	/* ADC.EVCTRL bit masks and bit positions */
3785	#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
3786	#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
3787	#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
3788	#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
3789	#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
3790	#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
3791	#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
3792	#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
3793
3794	#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */
3795	#define ADC_EVACT_bp 0 /* Event Action Select bit position. */
3796
3797
3798	/* ADC.PRESCALER bit masks and bit positions */
3799	#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
3800	#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
3801	#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
3802	#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
3803	#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
3804	#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
3805	#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
3806	#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
3807
3808
3809	/* ADC.INTFLAGS bit masks and bit positions */
3810	#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
3811	#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
3812
3813
3814	/* RTC - Real-Time Clounter */
3815	/* RTC.CTRL bit masks and bit positions */
3816	#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
3817	#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
3818	#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
3819	#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
3820	#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
3821	#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
3822	#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
3823	#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
3824
3825
3826	/* RTC.STATUS bit masks and bit positions */
3827	#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
3828	#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
3829
3830
3831	/* RTC.INTCTRL bit masks and bit positions */
3832	#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
3833	#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
3834	#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
3835	#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
3836	#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
3837	#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
3838
3839	#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
3840	#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
3841	#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
3842	#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
3843	#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
3844	#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
3845
3846
3847	/* RTC.INTFLAGS bit masks and bit positions */
3848	#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
3849	#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
3850
3851	#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
3852	#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
3853
3854
3855	/* EBI - External Bus Interface */
3856	/* EBI_CS.CTRLA bit masks and bit positions */
3857	#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
3858	#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
3859	#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
3860	#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
3861	#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
3862	#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
3863	#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
3864	#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
3865	#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
3866	#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
3867	#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
3868	#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
3869
3870	#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
3871	#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
3872	#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
3873	#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
3874	#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
3875	#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
3876
3877
3878	/* EBI_CS.CTRLB bit masks and bit positions */
3879	#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
3880	#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
3881	#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
3882	#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
3883	#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
3884	#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
3885	#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
3886	#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
3887
3888	#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
3889	#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
3890
3891	#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
3892	#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
3893
3894	#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
3895	#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
3896	#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
3897	#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
3898	#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
3899	#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
3900
3901
3902	/* EBI.CTRL bit masks and bit positions */
3903	#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
3904	#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
3905	#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
3906	#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
3907	#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
3908	#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
3909
3910	#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
3911	#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
3912	#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
3913	#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
3914	#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
3915	#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
3916
3917	#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
3918	#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
3919	#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
3920	#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
3921	#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
3922	#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
3923
3924	#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
3925	#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
3926	#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
3927	#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
3928	#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
3929	#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
3930
3931
3932	/* EBI.SDRAMCTRLA bit masks and bit positions */
3933	#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
3934	#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
3935
3936	#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
3937	#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
3938
3939	#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
3940	#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
3941	#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
3942	#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
3943	#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
3944	#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
3945
3946
3947	/* EBI.SDRAMCTRLB bit masks and bit positions */
3948	#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
3949	#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
3950	#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
3951	#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
3952	#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
3953	#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
3954
3955	#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
3956	#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
3957	#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
3958	#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
3959	#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
3960	#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
3961	#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
3962	#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
3963
3964	#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
3965	#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
3966	#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
3967	#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
3968	#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
3969	#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
3970	#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
3971	#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
3972
3973
3974	/* EBI.SDRAMCTRLC bit masks and bit positions */
3975	#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
3976	#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
3977	#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
3978	#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
3979	#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
3980	#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
3981
3982	#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
3983	#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
3984	#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
3985	#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
3986	#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
3987	#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
3988	#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
3989	#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
3990
3991	#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
3992	#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
3993	#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
3994	#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
3995	#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
3996	#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
3997	#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
3998	#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
3999
4000
4001	/* TWI - Two-Wire Interface */
4002	/* TWI_MASTER.CTRLA bit masks and bit positions */
4003	#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4004	#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
4005	#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4006	#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4007	#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4008	#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4009
4010	#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
4011	#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
4012
4013	#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
4014	#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
4015
4016	#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
4017	#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
4018
4019
4020	/* TWI_MASTER.CTRLB bit masks and bit positions */
4021	#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
4022	#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
4023	#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
4024	#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
4025	#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
4026	#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
4027
4028	#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
4029	#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
4030
4031	#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4032	#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
4033
4034
4035	/* TWI_MASTER.CTRLC bit masks and bit positions */
4036	#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4037	#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
4038
4039	#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
4040	#define TWI_MASTER_CMD_gp 0 /* Command group position. */
4041	#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
4042	#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
4043	#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
4044	#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
4045
4046
4047	/* TWI_MASTER.STATUS bit masks and bit positions */
4048	#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
4049	#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
4050
4051	#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
4052	#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
4053
4054	#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4055	#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
4056
4057	#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4058	#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
4059
4060	#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
4061	#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
4062
4063	#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
4064	#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
4065
4066	#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
4067	#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
4068	#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
4069	#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
4070	#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
4071	#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
4072
4073
4074	/* TWI_SLAVE.CTRLA bit masks and bit positions */
4075	#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4076	#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
4077	#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4078	#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4079	#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4080	#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4081
4082	#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
4083	#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
4084
4085	#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
4086	#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
4087
4088	#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
4089	#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
4090
4091	#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
4092	#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
4093
4094	#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
4095	#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
4096
4097	#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4098	#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
4099
4100
4101	/* TWI_SLAVE.CTRLB bit masks and bit positions */
4102	#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4103	#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
4104
4105	#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
4106	#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
4107	#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
4108	#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
4109	#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
4110	#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
4111
4112
4113	/* TWI_SLAVE.STATUS bit masks and bit positions */
4114	#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
4115	#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
4116
4117	#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
4118	#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
4119
4120	#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4121	#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
4122
4123	#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4124	#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
4125
4126	#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
4127	#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
4128
4129	#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
4130	#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
4131
4132	#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
4133	#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
4134
4135	#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
4136	#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
4137
4138
4139	/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
4140	#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
4141	#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
4142	#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
4143	#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
4144	#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
4145	#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
4146	#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
4147	#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
4148	#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
4149	#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
4150	#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
4151	#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
4152	#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
4153	#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
4154	#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
4155	#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
4156
4157	#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
4158	#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
4159
4160
4161	/* TWI.CTRL bit masks and bit positions */
4162	#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
4163	#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
4164
4165	#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
4166	#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
4167
4168
4169	/* PORT - Port Configuration */
4170	/* PORTCFG.VPCTRLA bit masks and bit positions */
4171	#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
4172	#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
4173	#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
4174	#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
4175	#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
4176	#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
4177	#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
4178	#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
4179	#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
4180	#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
4181
4182	#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
4183	#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
4184	#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
4185	#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
4186	#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
4187	#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
4188	#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
4189	#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
4190	#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
4191	#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
4192
4193
4194	/* PORTCFG.VPCTRLB bit masks and bit positions */
4195	#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
4196	#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
4197	#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
4198	#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
4199	#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
4200	#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
4201	#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
4202	#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
4203	#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
4204	#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
4205
4206	#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
4207	#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
4208	#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
4209	#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
4210	#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
4211	#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
4212	#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
4213	#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
4214	#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
4215	#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
4216
4217
4218	/* PORTCFG.CLKEVOUT bit masks and bit positions */
4219	#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
4220	#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
4221	#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
4222	#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
4223	#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
4224	#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
4225
4226	#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
4227	#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
4228	#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
4229	#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
4230	#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
4231	#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
4232
4233
4234	/* VPORT.INTFLAGS bit masks and bit positions */
4235	#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4236	#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4237
4238	#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4239	#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4240
4241
4242	/* PORT.INTCTRL bit masks and bit positions */
4243	#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
4244	#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
4245	#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
4246	#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
4247	#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
4248	#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
4249
4250	#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
4251	#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
4252	#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
4253	#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
4254	#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
4255	#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
4256
4257
4258	/* PORT.INTFLAGS bit masks and bit positions */
4259	#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4260	#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4261
4262	#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4263	#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4264
4265
4266	/* PORT.PIN0CTRL bit masks and bit positions */
4267	#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
4268	#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
4269
4270	#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
4271	#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
4272
4273	#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
4274	#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
4275	#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
4276	#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
4277	#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
4278	#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
4279	#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
4280	#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
4281
4282	#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
4283	#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
4284	#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
4285	#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
4286	#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
4287	#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
4288	#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
4289	#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
4290
4291
4292	/* PORT.PIN1CTRL bit masks and bit positions */
4293	/* PORT_SRLEN_bm Predefined. */
4294	/* PORT_SRLEN_bp Predefined. */
4295
4296	/* PORT_INVEN_bm Predefined. */
4297	/* PORT_INVEN_bp Predefined. */
4298
4299	/* PORT_OPC_gm Predefined. */
4300	/* PORT_OPC_gp Predefined. */
4301	/* PORT_OPC0_bm Predefined. */
4302	/* PORT_OPC0_bp Predefined. */
4303	/* PORT_OPC1_bm Predefined. */
4304	/* PORT_OPC1_bp Predefined. */
4305	/* PORT_OPC2_bm Predefined. */
4306	/* PORT_OPC2_bp Predefined. */
4307
4308	/* PORT_ISC_gm Predefined. */
4309	/* PORT_ISC_gp Predefined. */
4310	/* PORT_ISC0_bm Predefined. */
4311	/* PORT_ISC0_bp Predefined. */
4312	/* PORT_ISC1_bm Predefined. */
4313	/* PORT_ISC1_bp Predefined. */
4314	/* PORT_ISC2_bm Predefined. */
4315	/* PORT_ISC2_bp Predefined. */
4316
4317
4318	/* PORT.PIN2CTRL bit masks and bit positions */
4319	/* PORT_SRLEN_bm Predefined. */
4320	/* PORT_SRLEN_bp Predefined. */
4321
4322	/* PORT_INVEN_bm Predefined. */
4323	/* PORT_INVEN_bp Predefined. */
4324
4325	/* PORT_OPC_gm Predefined. */
4326	/* PORT_OPC_gp Predefined. */
4327	/* PORT_OPC0_bm Predefined. */
4328	/* PORT_OPC0_bp Predefined. */
4329	/* PORT_OPC1_bm Predefined. */
4330	/* PORT_OPC1_bp Predefined. */
4331	/* PORT_OPC2_bm Predefined. */
4332	/* PORT_OPC2_bp Predefined. */
4333
4334	/* PORT_ISC_gm Predefined. */
4335	/* PORT_ISC_gp Predefined. */
4336	/* PORT_ISC0_bm Predefined. */
4337	/* PORT_ISC0_bp Predefined. */
4338	/* PORT_ISC1_bm Predefined. */
4339	/* PORT_ISC1_bp Predefined. */
4340	/* PORT_ISC2_bm Predefined. */
4341	/* PORT_ISC2_bp Predefined. */
4342
4343
4344	/* PORT.PIN3CTRL bit masks and bit positions */
4345	/* PORT_SRLEN_bm Predefined. */
4346	/* PORT_SRLEN_bp Predefined. */
4347
4348	/* PORT_INVEN_bm Predefined. */
4349	/* PORT_INVEN_bp Predefined. */
4350
4351	/* PORT_OPC_gm Predefined. */
4352	/* PORT_OPC_gp Predefined. */
4353	/* PORT_OPC0_bm Predefined. */
4354	/* PORT_OPC0_bp Predefined. */
4355	/* PORT_OPC1_bm Predefined. */
4356	/* PORT_OPC1_bp Predefined. */
4357	/* PORT_OPC2_bm Predefined. */
4358	/* PORT_OPC2_bp Predefined. */
4359
4360	/* PORT_ISC_gm Predefined. */
4361	/* PORT_ISC_gp Predefined. */
4362	/* PORT_ISC0_bm Predefined. */
4363	/* PORT_ISC0_bp Predefined. */
4364	/* PORT_ISC1_bm Predefined. */
4365	/* PORT_ISC1_bp Predefined. */
4366	/* PORT_ISC2_bm Predefined. */
4367	/* PORT_ISC2_bp Predefined. */
4368
4369
4370	/* PORT.PIN4CTRL bit masks and bit positions */
4371	/* PORT_SRLEN_bm Predefined. */
4372	/* PORT_SRLEN_bp Predefined. */
4373
4374	/* PORT_INVEN_bm Predefined. */
4375	/* PORT_INVEN_bp Predefined. */
4376
4377	/* PORT_OPC_gm Predefined. */
4378	/* PORT_OPC_gp Predefined. */
4379	/* PORT_OPC0_bm Predefined. */
4380	/* PORT_OPC0_bp Predefined. */
4381	/* PORT_OPC1_bm Predefined. */
4382	/* PORT_OPC1_bp Predefined. */
4383	/* PORT_OPC2_bm Predefined. */
4384	/* PORT_OPC2_bp Predefined. */
4385
4386	/* PORT_ISC_gm Predefined. */
4387	/* PORT_ISC_gp Predefined. */
4388	/* PORT_ISC0_bm Predefined. */
4389	/* PORT_ISC0_bp Predefined. */
4390	/* PORT_ISC1_bm Predefined. */
4391	/* PORT_ISC1_bp Predefined. */
4392	/* PORT_ISC2_bm Predefined. */
4393	/* PORT_ISC2_bp Predefined. */
4394
4395
4396	/* PORT.PIN5CTRL bit masks and bit positions */
4397	/* PORT_SRLEN_bm Predefined. */
4398	/* PORT_SRLEN_bp Predefined. */
4399
4400	/* PORT_INVEN_bm Predefined. */
4401	/* PORT_INVEN_bp Predefined. */
4402
4403	/* PORT_OPC_gm Predefined. */
4404	/* PORT_OPC_gp Predefined. */
4405	/* PORT_OPC0_bm Predefined. */
4406	/* PORT_OPC0_bp Predefined. */
4407	/* PORT_OPC1_bm Predefined. */
4408	/* PORT_OPC1_bp Predefined. */
4409	/* PORT_OPC2_bm Predefined. */
4410	/* PORT_OPC2_bp Predefined. */
4411
4412	/* PORT_ISC_gm Predefined. */
4413	/* PORT_ISC_gp Predefined. */
4414	/* PORT_ISC0_bm Predefined. */
4415	/* PORT_ISC0_bp Predefined. */
4416	/* PORT_ISC1_bm Predefined. */
4417	/* PORT_ISC1_bp Predefined. */
4418	/* PORT_ISC2_bm Predefined. */
4419	/* PORT_ISC2_bp Predefined. */
4420
4421
4422	/* PORT.PIN6CTRL bit masks and bit positions */
4423	/* PORT_SRLEN_bm Predefined. */
4424	/* PORT_SRLEN_bp Predefined. */
4425
4426	/* PORT_INVEN_bm Predefined. */
4427	/* PORT_INVEN_bp Predefined. */
4428
4429	/* PORT_OPC_gm Predefined. */
4430	/* PORT_OPC_gp Predefined. */
4431	/* PORT_OPC0_bm Predefined. */
4432	/* PORT_OPC0_bp Predefined. */
4433	/* PORT_OPC1_bm Predefined. */
4434	/* PORT_OPC1_bp Predefined. */
4435	/* PORT_OPC2_bm Predefined. */
4436	/* PORT_OPC2_bp Predefined. */
4437
4438	/* PORT_ISC_gm Predefined. */
4439	/* PORT_ISC_gp Predefined. */
4440	/* PORT_ISC0_bm Predefined. */
4441	/* PORT_ISC0_bp Predefined. */
4442	/* PORT_ISC1_bm Predefined. */
4443	/* PORT_ISC1_bp Predefined. */
4444	/* PORT_ISC2_bm Predefined. */
4445	/* PORT_ISC2_bp Predefined. */
4446
4447
4448	/* PORT.PIN7CTRL bit masks and bit positions */
4449	/* PORT_SRLEN_bm Predefined. */
4450	/* PORT_SRLEN_bp Predefined. */
4451
4452	/* PORT_INVEN_bm Predefined. */
4453	/* PORT_INVEN_bp Predefined. */
4454
4455	/* PORT_OPC_gm Predefined. */
4456	/* PORT_OPC_gp Predefined. */
4457	/* PORT_OPC0_bm Predefined. */
4458	/* PORT_OPC0_bp Predefined. */
4459	/* PORT_OPC1_bm Predefined. */
4460	/* PORT_OPC1_bp Predefined. */
4461	/* PORT_OPC2_bm Predefined. */
4462	/* PORT_OPC2_bp Predefined. */
4463
4464	/* PORT_ISC_gm Predefined. */
4465	/* PORT_ISC_gp Predefined. */
4466	/* PORT_ISC0_bm Predefined. */
4467	/* PORT_ISC0_bp Predefined. */
4468	/* PORT_ISC1_bm Predefined. */
4469	/* PORT_ISC1_bp Predefined. */
4470	/* PORT_ISC2_bm Predefined. */
4471	/* PORT_ISC2_bp Predefined. */
4472
4473
4474	/* TC - 16-bit Timer/Counter With PWM */
4475	/* TC0.CTRLA bit masks and bit positions */
4476	#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4477	#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
4478	#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4479	#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4480	#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4481	#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4482	#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4483	#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4484	#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4485	#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4486
4487
4488	/* TC0.CTRLB bit masks and bit positions */
4489	#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
4490	#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
4491
4492	#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
4493	#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
4494
4495	#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4496	#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4497
4498	#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4499	#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4500
4501	#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4502	#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
4503	#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4504	#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4505	#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4506	#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4507	#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4508	#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4509
4510
4511	/* TC0.CTRLC bit masks and bit positions */
4512	#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
4513	#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
4514
4515	#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
4516	#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
4517
4518	#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4519	#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
4520
4521	#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4522	#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
4523
4524
4525	/* TC0.CTRLD bit masks and bit positions */
4526	#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
4527	#define TC0_EVACT_gp 5 /* Event Action group position. */
4528	#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4529	#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
4530	#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4531	#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
4532	#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4533	#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
4534
4535	#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
4536	#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
4537
4538	#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
4539	#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
4540	#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4541	#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4542	#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4543	#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4544	#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4545	#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4546	#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4547	#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4548
4549
4550	/* TC0.CTRLE bit masks and bit positions */
4551	#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4552	#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
4553
4554
4555	/* TC0.INTCTRLA bit masks and bit positions */
4556	#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4557	#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4558	#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4559	#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4560	#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4561	#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4562
4563	#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4564	#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4565	#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4566	#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4567	#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4568	#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4569
4570
4571	/* TC0.INTCTRLB bit masks and bit positions */
4572	#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
4573	#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
4574	#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
4575	#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
4576	#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
4577	#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
4578
4579	#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
4580	#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
4581	#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
4582	#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
4583	#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
4584	#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
4585
4586	#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4587	#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4588	#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4589	#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4590	#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4591	#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4592
4593	#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4594	#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4595	#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4596	#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4597	#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4598	#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4599
4600
4601	/* TC0.CTRLFCLR bit masks and bit positions */
4602	#define TC0_CMD_gm 0x0C /* Command group mask. */
4603	#define TC0_CMD_gp 2 /* Command group position. */
4604	#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
4605	#define TC0_CMD0_bp 2 /* Command bit 0 position. */
4606	#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
4607	#define TC0_CMD1_bp 3 /* Command bit 1 position. */
4608
4609	#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
4610	#define TC0_LUPD_bp 1 /* Lock Update bit position. */
4611
4612	#define TC0_DIR_bm 0x01 /* Direction bit mask. */
4613	#define TC0_DIR_bp 0 /* Direction bit position. */
4614
4615
4616	/* TC0.CTRLFSET bit masks and bit positions */
4617	/* TC0_CMD_gm Predefined. */
4618	/* TC0_CMD_gp Predefined. */
4619	/* TC0_CMD0_bm Predefined. */
4620	/* TC0_CMD0_bp Predefined. */
4621	/* TC0_CMD1_bm Predefined. */
4622	/* TC0_CMD1_bp Predefined. */
4623
4624	/* TC0_LUPD_bm Predefined. */
4625	/* TC0_LUPD_bp Predefined. */
4626
4627	/* TC0_DIR_bm Predefined. */
4628	/* TC0_DIR_bp Predefined. */
4629
4630
4631	/* TC0.CTRLGCLR bit masks and bit positions */
4632	#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
4633	#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
4634
4635	#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
4636	#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
4637
4638	#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
4639	#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
4640
4641	#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
4642	#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
4643
4644	#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
4645	#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
4646
4647
4648	/* TC0.CTRLGSET bit masks and bit positions */
4649	/* TC0_CCDBV_bm Predefined. */
4650	/* TC0_CCDBV_bp Predefined. */
4651
4652	/* TC0_CCCBV_bm Predefined. */
4653	/* TC0_CCCBV_bp Predefined. */
4654
4655	/* TC0_CCBBV_bm Predefined. */
4656	/* TC0_CCBBV_bp Predefined. */
4657
4658	/* TC0_CCABV_bm Predefined. */
4659	/* TC0_CCABV_bp Predefined. */
4660
4661	/* TC0_PERBV_bm Predefined. */
4662	/* TC0_PERBV_bp Predefined. */
4663
4664
4665	/* TC0.INTFLAGS bit masks and bit positions */
4666	#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
4667	#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
4668
4669	#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
4670	#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
4671
4672	#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
4673	#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
4674
4675	#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
4676	#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
4677
4678	#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
4679	#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
4680
4681	#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4682	#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4683
4684
4685	/* TC1.CTRLA bit masks and bit positions */
4686	#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4687	#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
4688	#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4689	#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4690	#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4691	#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4692	#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4693	#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4694	#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4695	#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4696
4697
4698	/* TC1.CTRLB bit masks and bit positions */
4699	#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4700	#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4701
4702	#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4703	#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4704
4705	#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4706	#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
4707	#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4708	#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4709	#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4710	#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4711	#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4712	#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4713
4714
4715	/* TC1.CTRLC bit masks and bit positions */
4716	#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4717	#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
4718
4719	#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4720	#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
4721
4722
4723	/* TC1.CTRLD bit masks and bit positions */
4724	#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
4725	#define TC1_EVACT_gp 5 /* Event Action group position. */
4726	#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4727	#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
4728	#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4729	#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
4730	#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4731	#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
4732
4733	#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
4734	#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
4735
4736	#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
4737	#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
4738	#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4739	#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4740	#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4741	#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4742	#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4743	#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4744	#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4745	#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4746
4747
4748	/* TC1.CTRLE bit masks and bit positions */
4749	#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4750	#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
4751
4752
4753	/* TC1.INTCTRLA bit masks and bit positions */
4754	#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4755	#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4756	#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4757	#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4758	#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4759	#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4760
4761	#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4762	#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4763	#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4764	#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4765	#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4766	#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4767
4768
4769	/* TC1.INTCTRLB bit masks and bit positions */
4770	#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4771	#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4772	#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4773	#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4774	#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4775	#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4776
4777	#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4778	#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4779	#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4780	#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4781	#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4782	#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4783
4784
4785	/* TC1.CTRLFCLR bit masks and bit positions */
4786	#define TC1_CMD_gm 0x0C /* Command group mask. */
4787	#define TC1_CMD_gp 2 /* Command group position. */
4788	#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
4789	#define TC1_CMD0_bp 2 /* Command bit 0 position. */
4790	#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
4791	#define TC1_CMD1_bp 3 /* Command bit 1 position. */
4792
4793	#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
4794	#define TC1_LUPD_bp 1 /* Lock Update bit position. */
4795
4796	#define TC1_DIR_bm 0x01 /* Direction bit mask. */
4797	#define TC1_DIR_bp 0 /* Direction bit position. */
4798
4799
4800	/* TC1.CTRLFSET bit masks and bit positions */
4801	/* TC1_CMD_gm Predefined. */
4802	/* TC1_CMD_gp Predefined. */
4803	/* TC1_CMD0_bm Predefined. */
4804	/* TC1_CMD0_bp Predefined. */
4805	/* TC1_CMD1_bm Predefined. */
4806	/* TC1_CMD1_bp Predefined. */
4807
4808	/* TC1_LUPD_bm Predefined. */
4809	/* TC1_LUPD_bp Predefined. */
4810
4811	/* TC1_DIR_bm Predefined. */
4812	/* TC1_DIR_bp Predefined. */
4813
4814
4815	/* TC1.CTRLGCLR bit masks and bit positions */
4816	#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
4817	#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
4818
4819	#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
4820	#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
4821
4822	#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
4823	#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
4824
4825
4826	/* TC1.CTRLGSET bit masks and bit positions */
4827	/* TC1_CCBBV_bm Predefined. */
4828	/* TC1_CCBBV_bp Predefined. */
4829
4830	/* TC1_CCABV_bm Predefined. */
4831	/* TC1_CCABV_bp Predefined. */
4832
4833	/* TC1_PERBV_bm Predefined. */
4834	/* TC1_PERBV_bp Predefined. */
4835
4836
4837	/* TC1.INTFLAGS bit masks and bit positions */
4838	#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
4839	#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
4840
4841	#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
4842	#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
4843
4844	#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
4845	#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
4846
4847	#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4848	#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4849
4850
4851	/* AWEX.CTRL bit masks and bit positions */
4852	#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
4853	#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
4854
4855	#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
4856	#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
4857
4858	#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
4859	#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
4860
4861	#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
4862	#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
4863
4864	#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
4865	#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
4866
4867	#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
4868	#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
4869
4870
4871	/* AWEX.FDCTRL bit masks and bit positions */
4872	#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
4873	#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
4874
4875	#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
4876	#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
4877
4878	#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
4879	#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
4880	#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
4881	#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
4882	#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
4883	#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
4884
4885
4886	/* AWEX.STATUS bit masks and bit positions */
4887	#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
4888	#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
4889
4890	#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
4891	#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
4892
4893	#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
4894	#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
4895
4896
4897	/* HIRES.CTRLA bit masks and bit positions */
4898	#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
4899	#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
4900	#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
4901	#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
4902	#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
4903	#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
4904
4905
4906	/* USART - Universal Asynchronous Receiver-Transmitter */
4907	/* USART.STATUS bit masks and bit positions */
4908	#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
4909	#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
4910
4911	#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
4912	#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
4913
4914	#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
4915	#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
4916
4917	#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
4918	#define USART_FERR_bp 4 /* Frame Error bit position. */
4919
4920	#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
4921	#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
4922
4923	#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
4924	#define USART_PERR_bp 2 /* Parity Error bit position. */
4925
4926	#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
4927	#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
4928
4929
4930	/* USART.CTRLA bit masks and bit positions */
4931	#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
4932	#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
4933	#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
4934	#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
4935	#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
4936	#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
4937
4938	#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
4939	#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
4940	#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
4941	#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
4942	#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
4943	#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
4944
4945	#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
4946	#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
4947	#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
4948	#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
4949	#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
4950	#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
4951
4952
4953	/* USART.CTRLB bit masks and bit positions */
4954	#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
4955	#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
4956
4957	#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
4958	#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
4959
4960	#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
4961	#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
4962
4963	#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
4964	#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
4965
4966	#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
4967	#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
4968
4969
4970	/* USART.CTRLC bit masks and bit positions */
4971	#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
4972	#define USART_CMODE_gp 6 /* Communication Mode group position. */
4973	#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
4974	#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
4975	#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
4976	#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
4977
4978	#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
4979	#define USART_PMODE_gp 4 /* Parity Mode group position. */
4980	#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
4981	#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
4982	#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
4983	#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
4984
4985	#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
4986	#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
4987
4988	#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
4989	#define USART_CHSIZE_gp 0 /* Character Size group position. */
4990	#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
4991	#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
4992	#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
4993	#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
4994	#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
4995	#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
4996
4997
4998	/* USART.BAUDCTRLA bit masks and bit positions */
4999	#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
5000	#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
5001	#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5002	#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
5003	#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5004	#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
5005	#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5006	#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
5007	#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5008	#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
5009	#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5010	#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
5011	#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5012	#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
5013	#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5014	#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
5015	#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5016	#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
5017
5018
5019	/* USART.BAUDCTRLB bit masks and bit positions */
5020	#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
5021	#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
5022	#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
5023	#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
5024	#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
5025	#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
5026	#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
5027	#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
5028	#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
5029	#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
5030
5031	/* USART_BSEL_gm Predefined. */
5032	/* USART_BSEL_gp Predefined. */
5033	/* USART_BSEL0_bm Predefined. */
5034	/* USART_BSEL0_bp Predefined. */
5035	/* USART_BSEL1_bm Predefined. */
5036	/* USART_BSEL1_bp Predefined. */
5037	/* USART_BSEL2_bm Predefined. */
5038	/* USART_BSEL2_bp Predefined. */
5039	/* USART_BSEL3_bm Predefined. */
5040	/* USART_BSEL3_bp Predefined. */
5041
5042
5043	/* SPI - Serial Peripheral Interface */
5044	/* SPI.CTRL bit masks and bit positions */
5045	#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
5046	#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
5047
5048	#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
5049	#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
5050
5051	#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
5052	#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
5053
5054	#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
5055	#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
5056
5057	#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
5058	#define SPI_MODE_gp 2 /* SPI Mode group position. */
5059	#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
5060	#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
5061	#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
5062	#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
5063
5064	#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
5065	#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
5066	#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
5067	#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
5068	#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
5069	#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
5070
5071
5072	/* SPI.INTCTRL bit masks and bit positions */
5073	#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
5074	#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
5075	#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
5076	#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
5077	#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
5078	#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
5079
5080
5081	/* SPI.STATUS bit masks and bit positions */
5082	#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
5083	#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
5084
5085	#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
5086	#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
5087
5088
5089	/* IRCOM - IR Communication Module */
5090	/* IRCOM.CTRL bit masks and bit positions */
5091	#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
5092	#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
5093	#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
5094	#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
5095	#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
5096	#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
5097	#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
5098	#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
5099	#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
5100	#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
5101
5102
5103
5104	// Generic Port Pins
5105
5106	#define PIN0_bm 0x01
5107	#define PIN0_bp 0
5108	#define PIN1_bm 0x02
5109	#define PIN1_bp 1
5110	#define PIN2_bm 0x04
5111	#define PIN2_bp 2
5112	#define PIN3_bm 0x08
5113	#define PIN3_bp 3
5114	#define PIN4_bm 0x10
5115	#define PIN4_bp 4
5116	#define PIN5_bm 0x20
5117	#define PIN5_bp 5
5118	#define PIN6_bm 0x40
5119	#define PIN6_bp 6
5120	#define PIN7_bm 0x80
5121	#define PIN7_bp 7
5122
5123
5124	/* ========== Interrupt Vector Definitions ========== */
5125	/* Vector 0 is the reset vector */
5126
5127	/* OSC interrupt vectors */
5128	#define OSC_XOSCF_vect_num 1
5129	#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
5130
5131	/* PORTC interrupt vectors */
5132	#define PORTC_INT0_vect_num 2
5133	#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
5134	#define PORTC_INT1_vect_num 3
5135	#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
5136
5137	/* PORTR interrupt vectors */
5138	#define PORTR_INT0_vect_num 4
5139	#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
5140	#define PORTR_INT1_vect_num 5
5141	#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
5142
5143	/* RTC interrupt vectors */
5144	#define RTC_OVF_vect_num 10
5145	#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
5146	#define RTC_COMP_vect_num 11
5147	#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
5148
5149	/* TWIC interrupt vectors */
5150	#define TWIC_TWIS_vect_num 12
5151	#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
5152	#define TWIC_TWIM_vect_num 13
5153	#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
5154
5155	/* TCC0 interrupt vectors */
5156	#define TCC0_OVF_vect_num 14
5157	#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
5158	#define TCC0_ERR_vect_num 15
5159	#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
5160	#define TCC0_CCA_vect_num 16
5161	#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
5162	#define TCC0_CCB_vect_num 17
5163	#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
5164	#define TCC0_CCC_vect_num 18
5165	#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
5166	#define TCC0_CCD_vect_num 19
5167	#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
5168
5169	/* TCC1 interrupt vectors */
5170	#define TCC1_OVF_vect_num 20
5171	#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
5172	#define TCC1_ERR_vect_num 21
5173	#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
5174	#define TCC1_CCA_vect_num 22
5175	#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
5176	#define TCC1_CCB_vect_num 23
5177	#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
5178
5179	/* SPIC interrupt vectors */
5180	#define SPIC_INT_vect_num 24
5181	#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
5182
5183	/* USARTC0 interrupt vectors */
5184	#define USARTC0_RXC_vect_num 25
5185	#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
5186	#define USARTC0_DRE_vect_num 26
5187	#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
5188	#define USARTC0_TXC_vect_num 27
5189	#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
5190
5191	/* NVM interrupt vectors */
5192	#define NVM_EE_vect_num 32
5193	#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
5194	#define NVM_SPM_vect_num 33
5195	#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
5196
5197	/* PORTB interrupt vectors */
5198	#define PORTB_INT0_vect_num 34
5199	#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
5200	#define PORTB_INT1_vect_num 35
5201	#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
5202
5203	/* PORTE interrupt vectors */
5204	#define PORTE_INT0_vect_num 43
5205	#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
5206	#define PORTE_INT1_vect_num 44
5207	#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
5208
5209	/* TCE0 interrupt vectors */
5210	#define TCE0_OVF_vect_num 47
5211	#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
5212	#define TCE0_ERR_vect_num 48
5213	#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
5214	#define TCE0_CCA_vect_num 49
5215	#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
5216	#define TCE0_CCB_vect_num 50
5217	#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
5218	#define TCE0_CCC_vect_num 51
5219	#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
5220	#define TCE0_CCD_vect_num 52
5221	#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
5222
5223	/* USARTE0 interrupt vectors */
5224	#define USARTE0_RXC_vect_num 58
5225	#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
5226	#define USARTE0_DRE_vect_num 59
5227	#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
5228	#define USARTE0_TXC_vect_num 60
5229	#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
5230
5231	/* PORTD interrupt vectors */
5232	#define PORTD_INT0_vect_num 64
5233	#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
5234	#define PORTD_INT1_vect_num 65
5235	#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
5236
5237	/* PORTA interrupt vectors */
5238	#define PORTA_INT0_vect_num 66
5239	#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
5240	#define PORTA_INT1_vect_num 67
5241	#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
5242
5243	/* ACA interrupt vectors */
5244	#define ACA_AC0_vect_num 68
5245	#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
5246	#define ACA_AC1_vect_num 69
5247	#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
5248	#define ACA_ACW_vect_num 70
5249	#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
5250
5251	/* ADCA interrupt vectors */
5252	#define ADCA_CH0_vect_num 71
5253	#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
5254
5255	/* TCD0 interrupt vectors */
5256	#define TCD0_OVF_vect_num 77
5257	#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
5258	#define TCD0_ERR_vect_num 78
5259	#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
5260	#define TCD0_CCA_vect_num 79
5261	#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
5262	#define TCD0_CCB_vect_num 80
5263	#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
5264	#define TCD0_CCC_vect_num 81
5265	#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
5266	#define TCD0_CCD_vect_num 82
5267	#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
5268
5269	/* SPID interrupt vectors */
5270	#define SPID_INT_vect_num 87
5271	#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
5272
5273	/* USARTD0 interrupt vectors */
5274	#define USARTD0_RXC_vect_num 88
5275	#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
5276	#define USARTD0_DRE_vect_num 89
5277	#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
5278	#define USARTD0_TXC_vect_num 90
5279	#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
5280
5281	/* PORTF interrupt vectors */
5282	#define PORTF_INT0_vect_num 104
5283	#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
5284	#define PORTF_INT1_vect_num 105
5285	#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
5286
5287	/* TCF0 interrupt vectors */
5288	#define TCF0_OVF_vect_num 108
5289	#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
5290	#define TCF0_ERR_vect_num 109
5291	#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
5292	#define TCF0_CCA_vect_num 110
5293	#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
5294	#define TCF0_CCB_vect_num 111
5295	#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
5296	#define TCF0_CCC_vect_num 112
5297	#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
5298	#define TCF0_CCD_vect_num 113
5299	#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
5300
5301
5302	#define _VECTOR_SIZE 4 /* Size of individual vector. */
5303	#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
5304
5305
5306	/* ========== Constants ========== */
5307
5308	#define PROGMEM_START (0x0000)
5309	#define PROGMEM_SIZE (270336)
5310	#define PROGMEM_PAGE_SIZE (512)
5311	#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
5312
5313	#define APP_SECTION_START (0x0000)
5314	#define APP_SECTION_SIZE (262144)
5315	#define APP_SECTION_PAGE_SIZE (512)
5316	#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
5317
5318	#define APPTABLE_SECTION_START (0x3E000)
5319	#define APPTABLE_SECTION_SIZE (8192)
5320	#define APPTABLE_SECTION_PAGE_SIZE (512)
5321	#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5322
5323	#define BOOT_SECTION_START (0x40000)
5324	#define BOOT_SECTION_SIZE (8192)
5325	#define BOOT_SECTION_PAGE_SIZE (512)
5326	#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5327
5328	#define DATAMEM_START (0x0000)
5329	#define DATAMEM_SIZE (24576)
5330	#define DATAMEM_PAGE_SIZE (0)
5331	#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
5332
5333	#define IO_START (0x0000)
5334	#define IO_SIZE (4096)
5335	#define IO_PAGE_SIZE (0)
5336	#define IO_END (IO_START + IO_SIZE - 1)
5337
5338	#define MAPPED_EEPROM_START (0x1000)
5339	#define MAPPED_EEPROM_SIZE (4096)
5340	#define MAPPED_EEPROM_PAGE_SIZE (0)
5341	#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5342
5343	#define INTERNAL_SRAM_START (0x2000)
5344	#define INTERNAL_SRAM_SIZE (16384)
5345	#define INTERNAL_SRAM_PAGE_SIZE (0)
5346	#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5347
5348	#define EEPROM_START (0x0000)
5349	#define EEPROM_SIZE (4096)
5350	#define EEPROM_PAGE_SIZE (32)
5351	#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
5352
5353	#define FUSE_START (0x0000)
5354	#define FUSE_SIZE (6)
5355	#define FUSE_PAGE_SIZE (0)
5356	#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
5357
5358	#define LOCKBIT_START (0x0000)
5359	#define LOCKBIT_SIZE (1)
5360	#define LOCKBIT_PAGE_SIZE (0)
5361	#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
5362
5363	#define SIGNATURES_START (0x0000)
5364	#define SIGNATURES_SIZE (3)
5365	#define SIGNATURES_PAGE_SIZE (0)
5366	#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
5367
5368	#define USER_SIGNATURES_START (0x0000)
5369	#define USER_SIGNATURES_SIZE (512)
5370	#define USER_SIGNATURES_PAGE_SIZE (0)
5371	#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5372
5373	#define PROD_SIGNATURES_START (0x0000)
5374	#define PROD_SIGNATURES_SIZE (52)
5375	#define PROD_SIGNATURES_PAGE_SIZE (0)
5376	#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5377
5378	#define FLASHEND PROGMEM_END
5379	#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5380	#define RAMSTART INTERNAL_SRAM_START
5381	#define RAMSIZE INTERNAL_SRAM_SIZE
5382	#define RAMEND INTERNAL_SRAM_END
5383	#define XRAMSTART EXTERNAL_SRAM_START
5384	#define XRAMSIZE EXTERNAL_SRAM_SIZE
5385	#define XRAMEND INTERNAL_SRAM_END
5386	#define E2END EEPROM_END
5387	#define E2PAGESIZE EEPROM_PAGE_SIZE
5388
5389
5390	/* ========== Fuses ========== */
5391	#define FUSE_MEMORY_SIZE 6
5392
5393	/* Fuse Byte 0 */
5394	#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
5395	#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
5396	#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
5397	#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
5398	#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
5399	#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
5400	#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
5401	#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
5402	#define FUSE0_DEFAULT (0xFF)
5403
5404	/* Fuse Byte 1 */
5405	#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
5406	#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
5407	#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
5408	#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
5409	#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
5410	#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
5411	#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
5412	#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
5413	#define FUSE1_DEFAULT (0xFF)
5414
5415	/* Fuse Byte 2 */
5416	#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
5417	#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
5418	#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
5419	#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
5420	#define FUSE2_DEFAULT (0xFF)
5421
5422	/* Fuse Byte 3 Reserved */
5423
5424	/* Fuse Byte 4 */
5425	#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
5426	#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
5427	#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
5428	#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */
5429	#define FUSE4_DEFAULT (0xFF)
5430
5431	/* Fuse Byte 5 */
5432	#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
5433	#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
5434	#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
5435	#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
5436	#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
5437	#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
5438	#define FUSE5_DEFAULT (0xFF)
5439
5440
5441	/* ========== Lock Bits ========== */
5442	#define __LOCK_BITS_EXIST
5443	#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5444	#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5445	#define __BOOT_LOCK_BOOT_BITS_EXIST
5446
5447
5448	/* ========== Signature ========== */
5449	#define SIGNATURE_0 0x1E
5450	#define SIGNATURE_1 0x98
5451	#define SIGNATURE_2 0x44
5452
5453
5454	#endif /* _AVR_ATxmega256D3_H_ */
5455

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source: rtems/cpukit/score/cpu/avr/avr/iox256d3.h @ 9b4422a2

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