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source: rtems/cpukit/score/cpu/avr/avr/iox192d3.h @ b10825c

4.115

Last change on this file since b10825c was b10825c, checked in by Joel Sherrill <joel.sherrill@…>, on 01/10/13 at 19:29:41
cpukit: Add EOL on files missing EOL at EOF
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1	/**
2	* @file avr/iox192d3.h
3	*
4	* @brief Definitions for ATxmega192D3
5	*
6	* This file should only be included from <avr/io.h>, never directly.
7	*/
8
9	/*
10	* Copyright (c) 2009 Atmel Corporation
11	* All rights reserved.
12	*
13	* Redistribution and use in source and binary forms, with or without
14	* modification, are permitted provided that the following conditions are met:
15	*
16	* * Redistributions of source code must retain the above copyright
17	* notice, this list of conditions and the following disclaimer.
18	*
19	* * Redistributions in binary form must reproduce the above copyright
20	* notice, this list of conditions and the following disclaimer in
21	* the documentation and/or other materials provided with the
22	* distribution.
23	*
24	* * Neither the name of the copyright holders nor the names of
25	* contributors may be used to endorse or promote products derived
26	* from this software without specific prior written permission.
27	*
28	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
29	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
32	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
33	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
34	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
35	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
37	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38	* POSSIBILITY OF SUCH DAMAGE.
39	*/
40
41	#ifndef _AVR_IO_H_
42	# error "Include <avr/io.h> instead of this file."
43	#endif
44
45	#ifndef _AVR_IOXXX_H_
46	# define _AVR_IOXXX_H_ "iox192d3.h"
47	#else
48	# error "Attempt to include more than one <avr/ioXXX.h> file."
49	#endif
50
51
52	#ifndef _AVR_ATxmega192D3_H_
53	#define _AVR_ATxmega192D3_H_ 1
54
55	/**
56	* @defgroup Avr_iox192d3 ATxmega192D3 Definitions
57	*
58	* @ingroup avr
59	*/
60	/*@{/
61
62	/* Ungrouped common registers */
63	#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
64	#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
65	#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
66	#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
67	#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
68	#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
69	#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
70	#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
71	#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
72	#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
73	#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
74	#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
75	#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
76	#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
77	#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
78	#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
79
80	#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
81	#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
82	#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
83	#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
84	#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
85	#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
86	#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
87	#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
88	#define SREG _SFR_MEM8(0x003F) /* Status Register */
89
90
91	/* C Language Only */
92	#if !defined (__ASSEMBLER__)
93
94	#include <stdint.h>
95
96	typedef volatile uint8_t register8_t;
97	typedef volatile uint16_t register16_t;
98	typedef volatile uint32_t register32_t;
99
100
101	#ifdef _WORDREGISTER
102	#undef _WORDREGISTER
103	#endif
104	#define _WORDREGISTER(regname) \
105	__extension__ union \
106	{ \
107	register16_t regname; \
108	struct \
109	{ \
110	register8_t regname ## L; \
111	register8_t regname ## H; \
112	}; \
113	}
114
115	#ifdef _DWORDREGISTER
116	#undef _DWORDREGISTER
117	#endif
118	#define _DWORDREGISTER(regname) \
119	__extension__ union \
120	{ \
121	register32_t regname; \
122	struct \
123	{ \
124	register8_t regname ## 0; \
125	register8_t regname ## 1; \
126	register8_t regname ## 2; \
127	register8_t regname ## 3; \
128	}; \
129	}
130
131
132	/*
133	==========================================================================
134	IO Module Structures
135	==========================================================================
136	*/
137
138
139	/*
140	--------------------------------------------------------------------------
141	XOCD - On-Chip Debug System
142	--------------------------------------------------------------------------
143	*/
144
145	/* On-Chip Debug System */
146	typedef struct OCD_struct
147	{
148	register8_t OCDR0; /* OCD Register 0 */
149	register8_t OCDR1; /* OCD Register 1 */
150	} OCD_t;
151
152
153	/* CCP signatures */
154	typedef enum CCP_enum
155	{
156	CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
157	CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
158	} CCP_t;
159
160
161	/*
162	--------------------------------------------------------------------------
163	CLK - Clock System
164	--------------------------------------------------------------------------
165	*/
166
167	/* Clock System */
168	typedef struct CLK_struct
169	{
170	register8_t CTRL; /* Control Register */
171	register8_t PSCTRL; /* Prescaler Control Register */
172	register8_t LOCK; /* Lock register */
173	register8_t RTCCTRL; /* RTC Control Register */
174	} CLK_t;
175
176	/*
177	--------------------------------------------------------------------------
178	CLK - Clock System
179	--------------------------------------------------------------------------
180	*/
181
182	/* Power Reduction */
183	typedef struct PR_struct
184	{
185	register8_t PRGEN; /* General Power Reduction */
186	register8_t PRPA; /* Power Reduction Port A */
187	register8_t PRPB; /* Power Reduction Port B */
188	register8_t PRPC; /* Power Reduction Port C */
189	register8_t PRPD; /* Power Reduction Port D */
190	register8_t PRPE; /* Power Reduction Port E */
191	register8_t PRPF; /* Power Reduction Port F */
192	} PR_t;
193
194	/* System Clock Selection */
195	typedef enum CLK_SCLKSEL_enum
196	{
197	CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */
198	CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */
199	CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */
200	CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */
201	CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
202	} CLK_SCLKSEL_t;
203
204	/* Prescaler A Division Factor */
205	typedef enum CLK_PSADIV_enum
206	{
207	CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
208	CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
209	CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
210	CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
211	CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
212	CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
213	CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
214	CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
215	CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
216	CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
217	} CLK_PSADIV_t;
218
219	/* Prescaler B and C Division Factor */
220	typedef enum CLK_PSBCDIV_enum
221	{
222	CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
223	CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
224	CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
225	CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
226	} CLK_PSBCDIV_t;
227
228	/* RTC Clock Source */
229	typedef enum CLK_RTCSRC_enum
230	{
231	CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */
232	CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */
233	CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */
234	CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */
235	} CLK_RTCSRC_t;
236
237
238	/*
239	--------------------------------------------------------------------------
240	SLEEP - Sleep Controller
241	--------------------------------------------------------------------------
242	*/
243
244	/* Sleep Controller */
245	typedef struct SLEEP_struct
246	{
247	register8_t CTRL; /* Control Register */
248	} SLEEP_t;
249
250	/* Sleep Mode */
251	typedef enum SLEEP_SMODE_enum
252	{
253	SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
254	SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
255	SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
256	SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
257	SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
258	} SLEEP_SMODE_t;
259
260
261	/*
262	--------------------------------------------------------------------------
263	OSC - Oscillator
264	--------------------------------------------------------------------------
265	*/
266
267	/* Oscillator */
268	typedef struct OSC_struct
269	{
270	register8_t CTRL; /* Control Register */
271	register8_t STATUS; /* Status Register */
272	register8_t XOSCCTRL; /* External Oscillator Control Register */
273	register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */
274	register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */
275	register8_t PLLCTRL; /* PLL Control REgister */
276	register8_t DFLLCTRL; /* DFLL Control Register */
277	} OSC_t;
278
279	/* Oscillator Frequency Range */
280	typedef enum OSC_FRQRANGE_enum
281	{
282	OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
283	OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
284	OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
285	OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
286	} OSC_FRQRANGE_t;
287
288	/* External Oscillator Selection and Startup Time */
289	typedef enum OSC_XOSCSEL_enum
290	{
291	OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
292	OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */
293	OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */
294	OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */
295	OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */
296	} OSC_XOSCSEL_t;
297
298	/* PLL Clock Source */
299	typedef enum OSC_PLLSRC_enum
300	{
301	OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */
302	OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */
303	OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
304	} OSC_PLLSRC_t;
305
306
307	/*
308	--------------------------------------------------------------------------
309	DFLL - DFLL
310	--------------------------------------------------------------------------
311	*/
312
313	/* DFLL */
314	typedef struct DFLL_struct
315	{
316	register8_t CTRL; /* Control Register */
317	register8_t reserved_0x01;
318	register8_t CALA; /* Calibration Register A */
319	register8_t CALB; /* Calibration Register B */
320	register8_t COMP0; /* Oscillator Compare Register 0 */
321	register8_t COMP1; /* Oscillator Compare Register 1 */
322	register8_t COMP2; /* Oscillator Compare Register 2 */
323	register8_t reserved_0x07;
324	} DFLL_t;
325
326
327	/*
328	--------------------------------------------------------------------------
329	RST - Reset
330	--------------------------------------------------------------------------
331	*/
332
333	/* Reset */
334	typedef struct RST_struct
335	{
336	register8_t STATUS; /* Status Register */
337	register8_t CTRL; /* Control Register */
338	} RST_t;
339
340
341	/*
342	--------------------------------------------------------------------------
343	WDT - Watch-Dog Timer
344	--------------------------------------------------------------------------
345	*/
346
347	/* Watch-Dog Timer */
348	typedef struct WDT_struct
349	{
350	register8_t CTRL; /* Control */
351	register8_t WINCTRL; /* Windowed Mode Control */
352	register8_t STATUS; /* Status */
353	} WDT_t;
354
355	/* Period setting */
356	typedef enum WDT_PER_enum
357	{
358	WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
359	WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
360	WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
361	WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
362	WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
363	WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
364	WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
365	WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
366	WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
367	WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
368	WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
369	} WDT_PER_t;
370
371	/* Closed window period */
372	typedef enum WDT_WPER_enum
373	{
374	WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
375	WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
376	WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
377	WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
378	WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
379	WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
380	WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
381	WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
382	WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
383	WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
384	WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
385	} WDT_WPER_t;
386
387
388	/*
389	--------------------------------------------------------------------------
390	MCU - MCU Control
391	--------------------------------------------------------------------------
392	*/
393
394	/* MCU Control */
395	typedef struct MCU_struct
396	{
397	register8_t DEVID0; /* Device ID byte 0 */
398	register8_t DEVID1; /* Device ID byte 1 */
399	register8_t DEVID2; /* Device ID byte 2 */
400	register8_t REVID; /* Revision ID */
401	register8_t JTAGUID; /* JTAG User ID */
402	register8_t reserved_0x05;
403	register8_t MCUCR; /* MCU Control */
404	register8_t reserved_0x07;
405	register8_t EVSYSLOCK; /* Event System Lock */
406	register8_t AWEXLOCK; /* AWEX Lock */
407	register8_t reserved_0x0A;
408	register8_t reserved_0x0B;
409	} MCU_t;
410
411
412	/*
413	--------------------------------------------------------------------------
414	PMIC - Programmable Multi-level Interrupt Controller
415	--------------------------------------------------------------------------
416	*/
417
418	/* Programmable Multi-level Interrupt Controller */
419	typedef struct PMIC_struct
420	{
421	register8_t STATUS; /* Status Register */
422	register8_t INTPRI; /* Interrupt Priority */
423	register8_t CTRL; /* Control Register */
424	} PMIC_t;
425
426
427	/*
428	--------------------------------------------------------------------------
429	EVSYS - Event System
430	--------------------------------------------------------------------------
431	*/
432
433	/* Event System */
434	typedef struct EVSYS_struct
435	{
436	register8_t CH0MUX; /* Event Channel 0 Multiplexer */
437	register8_t CH1MUX; /* Event Channel 1 Multiplexer */
438	register8_t CH2MUX; /* Event Channel 2 Multiplexer */
439	register8_t CH3MUX; /* Event Channel 3 Multiplexer */
440	register8_t CH0CTRL; /* Channel 0 Control Register */
441	register8_t CH1CTRL; /* Channel 1 Control Register */
442	register8_t CH2CTRL; /* Channel 2 Control Register */
443	register8_t CH3CTRL; /* Channel 3 Control Register */
444	register8_t STROBE; /* Event Strobe */
445	register8_t DATA; /* Event Data */
446	} EVSYS_t;
447
448	/* Quadrature Decoder Index Recognition Mode */
449	typedef enum EVSYS_QDIRM_enum
450	{
451	EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
452	EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
453	EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
454	EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
455	} EVSYS_QDIRM_t;
456
457	/* Digital filter coefficient */
458	typedef enum EVSYS_DIGFILT_enum
459	{
460	EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
461	EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
462	EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
463	EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
464	EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
465	EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
466	EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
467	EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
468	} EVSYS_DIGFILT_t;
469
470	/* Event Channel multiplexer input selection */
471	typedef enum EVSYS_CHMUX_enum
472	{
473	EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
474	EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
475	EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
476	EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
477	EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
478	EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
479	EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
480	EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
481	EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
482	EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
483	EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
484	EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
485	EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
486	EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
487	EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
488	EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
489	EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
490	EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
491	EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
492	EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
493	EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
494	EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
495	EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
496	EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
497	EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
498	EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
499	EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
500	EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
501	EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
502	EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
503	EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
504	EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
505	EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
506	EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
507	EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
508	EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
509	EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
510	EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
511	EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
512	EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
513	EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
514	EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
515	EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
516	EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
517	EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
518	EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
519	EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
520	EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
521	EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
522	EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
523	EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
524	EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
525	EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
526	EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
527	EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
528	EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
529	EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
530	EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
531	EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
532	EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
533	EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
534	EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
535	EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
536	EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
537	EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
538	EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
539	EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
540	EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
541	EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
542	EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */
543	EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */
544	EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
545	EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
546	EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */
547	EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */
548	EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */
549	EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */
550	EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
551	EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
552	EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */
553	EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */
554	EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
555	EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
556	EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */
557	EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */
558	EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */
559	EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */
560	EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
561	EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
562	EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */
563	EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */
564	EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
565	EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
566	EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */
567	EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */
568	EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */
569	EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */
570	EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
571	EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
572	EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */
573	EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */
574	EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
575	EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
576	EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */
577	EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */
578	EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */
579	EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */
580	EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
581	EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
582	EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */
583	EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */
584	} EVSYS_CHMUX_t;
585
586
587	/*
588	--------------------------------------------------------------------------
589	NVM - Non Volatile Memory Controller
590	--------------------------------------------------------------------------
591	*/
592
593	/* Non-volatile Memory Controller */
594	typedef struct NVM_struct
595	{
596	register8_t ADDR0; /* Address Register 0 */
597	register8_t ADDR1; /* Address Register 1 */
598	register8_t ADDR2; /* Address Register 2 */
599	register8_t reserved_0x03;
600	register8_t DATA0; /* Data Register 0 */
601	register8_t DATA1; /* Data Register 1 */
602	register8_t DATA2; /* Data Register 2 */
603	register8_t reserved_0x07;
604	register8_t reserved_0x08;
605	register8_t reserved_0x09;
606	register8_t CMD; /* Command */
607	register8_t CTRLA; /* Control Register A */
608	register8_t CTRLB; /* Control Register B */
609	register8_t INTCTRL; /* Interrupt Control */
610	register8_t reserved_0x0E;
611	register8_t STATUS; /* Status */
612	register8_t LOCKBITS; /* Lock Bits */
613	} NVM_t;
614
615	/*
616	--------------------------------------------------------------------------
617	NVM - Non Volatile Memory Controller
618	--------------------------------------------------------------------------
619	*/
620
621	/* Lock Bits */
622	typedef struct NVM_LOCKBITS_struct
623	{
624	register8_t LOCKBITS; /* Lock Bits */
625	} NVM_LOCKBITS_t;
626
627	/*
628	--------------------------------------------------------------------------
629	NVM - Non Volatile Memory Controller
630	--------------------------------------------------------------------------
631	*/
632
633	/* Fuses */
634	typedef struct NVM_FUSES_struct
635	{
636	register8_t FUSEBYTE0; /* User ID */
637	register8_t FUSEBYTE1; /* Watchdog Configuration */
638	register8_t FUSEBYTE2; /* Reset Configuration */
639	register8_t reserved_0x03;
640	register8_t FUSEBYTE4; /* Start-up Configuration */
641	register8_t FUSEBYTE5; /* EESAVE and BOD Level */
642	} NVM_FUSES_t;
643
644	/*
645	--------------------------------------------------------------------------
646	NVM - Non Volatile Memory Controller
647	--------------------------------------------------------------------------
648	*/
649
650	/* Production Signatures */
651	typedef struct NVM_PROD_SIGNATURES_struct
652	{
653	register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */
654	register8_t reserved_0x01;
655	register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */
656	register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */
657	register8_t reserved_0x04;
658	register8_t reserved_0x05;
659	register8_t reserved_0x06;
660	register8_t reserved_0x07;
661	register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */
662	register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */
663	register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */
664	register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */
665	register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */
666	register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */
667	register8_t reserved_0x0E;
668	register8_t reserved_0x0F;
669	register8_t WAFNUM; /* Wafer Number */
670	register8_t reserved_0x11;
671	register8_t COORDX0; /* Wafer Coordinate X Byte 0 */
672	register8_t COORDX1; /* Wafer Coordinate X Byte 1 */
673	register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */
674	register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */
675	register8_t reserved_0x16;
676	register8_t reserved_0x17;
677	register8_t reserved_0x18;
678	register8_t reserved_0x19;
679	register8_t reserved_0x1A;
680	register8_t reserved_0x1B;
681	register8_t reserved_0x1C;
682	register8_t reserved_0x1D;
683	register8_t reserved_0x1E;
684	register8_t reserved_0x1F;
685	register8_t ADCACAL0; /* ADCA Calibration Byte 0 */
686	register8_t ADCACAL1; /* ADCA Calibration Byte 1 */
687	register8_t reserved_0x22;
688	register8_t reserved_0x23;
689	register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */
690	register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */
691	register8_t reserved_0x26;
692	register8_t reserved_0x27;
693	register8_t reserved_0x28;
694	register8_t reserved_0x29;
695	register8_t reserved_0x2A;
696	register8_t reserved_0x2B;
697	register8_t reserved_0x2C;
698	register8_t reserved_0x2D;
699	register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */
700	register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */
701	register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */
702	register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */
703	register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */
704	register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */
705	register8_t reserved_0x34;
706	register8_t reserved_0x35;
707	register8_t reserved_0x36;
708	register8_t reserved_0x37;
709	register8_t reserved_0x38;
710	register8_t reserved_0x39;
711	register8_t reserved_0x3A;
712	register8_t reserved_0x3B;
713	register8_t reserved_0x3C;
714	register8_t reserved_0x3D;
715	register8_t reserved_0x3E;
716	} NVM_PROD_SIGNATURES_t;
717
718	/* NVM Command */
719	typedef enum NVM_CMD_enum
720	{
721	NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
722	NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
723	NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */
724	NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
725	NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
726	NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
727	NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
728	NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
729	NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
730	NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */
731	NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
732	NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */
733	NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */
734	NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */
735	NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
736	NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
737	NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */
738	NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
739	NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
740	NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
741	NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
742	NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */
743	NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */
744	NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
745	NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
746	NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */
747	} NVM_CMD_t;
748
749	/* SPM ready interrupt level */
750	typedef enum NVM_SPMLVL_enum
751	{
752	NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
753	NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
754	NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
755	NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
756	} NVM_SPMLVL_t;
757
758	/* EEPROM ready interrupt level */
759	typedef enum NVM_EELVL_enum
760	{
761	NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
762	NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
763	NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
764	NVM_EELVL_HI_gc = (0x03<<0), /* High level */
765	} NVM_EELVL_t;
766
767	/* Boot lock bits - boot setcion */
768	typedef enum NVM_BLBB_enum
769	{
770	NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
771	NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
772	NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
773	NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
774	} NVM_BLBB_t;
775
776	/* Boot lock bits - application section */
777	typedef enum NVM_BLBA_enum
778	{
779	NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
780	NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
781	NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
782	NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
783	} NVM_BLBA_t;
784
785	/* Boot lock bits - application table section */
786	typedef enum NVM_BLBAT_enum
787	{
788	NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
789	NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
790	NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
791	NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
792	} NVM_BLBAT_t;
793
794	/* Lock bits */
795	typedef enum NVM_LB_enum
796	{
797	NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
798	NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
799	NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
800	} NVM_LB_t;
801
802	/* Boot Loader Section Reset Vector */
803	typedef enum BOOTRST_enum
804	{
805	BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */
806	BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */
807	} BOOTRST_t;
808
809	/* BOD operation */
810	typedef enum BOD_enum
811	{
812	BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */
813	BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */
814	BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */
815	} BOD_t;
816
817	/* Watchdog (Window) Timeout Period */
818	typedef enum WD_enum
819	{
820	WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */
821	WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */
822	WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */
823	WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */
824	WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */
825	WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */
826	WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */
827	WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */
828	WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */
829	WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */
830	WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */
831	} WD_t;
832
833	/* Start-up Time */
834	typedef enum SUT_enum
835	{
836	SUT_0MS_gc = (0x03<<2), /* 0 ms */
837	SUT_4MS_gc = (0x01<<2), /* 4 ms */
838	SUT_64MS_gc = (0x00<<2), /* 64 ms */
839	} SUT_t;
840
841	/* Brown Out Detection Voltage Level */
842	typedef enum BODLVL_enum
843	{
844	BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */
845	BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */
846	BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */
847	BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */
848	BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */
849	BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */
850	BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */
851	} BODLVL_t;
852
853
854	/*
855	--------------------------------------------------------------------------
856	AC - Analog Comparator
857	--------------------------------------------------------------------------
858	*/
859
860	/* Analog Comparator */
861	typedef struct AC_struct
862	{
863	register8_t AC0CTRL; /* Comparator 0 Control */
864	register8_t AC1CTRL; /* Comparator 1 Control */
865	register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */
866	register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */
867	register8_t CTRLA; /* Control Register A */
868	register8_t CTRLB; /* Control Register B */
869	register8_t WINCTRL; /* Window Mode Control */
870	register8_t STATUS; /* Status */
871	} AC_t;
872
873	/* Interrupt mode */
874	typedef enum AC_INTMODE_enum
875	{
876	AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
877	AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
878	AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
879	} AC_INTMODE_t;
880
881	/* Interrupt level */
882	typedef enum AC_INTLVL_enum
883	{
884	AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
885	AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
886	AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
887	AC_INTLVL_HI_gc = (0x03<<4), /* High level */
888	} AC_INTLVL_t;
889
890	/* Hysteresis mode selection */
891	typedef enum AC_HYSMODE_enum
892	{
893	AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
894	AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
895	AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
896	} AC_HYSMODE_t;
897
898	/* Positive input multiplexer selection */
899	typedef enum AC_MUXPOS_enum
900	{
901	AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
902	AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
903	AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
904	AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
905	AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
906	AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
907	AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
908	AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
909	} AC_MUXPOS_t;
910
911	/* Negative input multiplexer selection */
912	typedef enum AC_MUXNEG_enum
913	{
914	AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
915	AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
916	AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
917	AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
918	AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
919	AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
920	AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
921	AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
922	} AC_MUXNEG_t;
923
924	/* Windows interrupt mode */
925	typedef enum AC_WINTMODE_enum
926	{
927	AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
928	AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
929	AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
930	AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
931	} AC_WINTMODE_t;
932
933	/* Window interrupt level */
934	typedef enum AC_WINTLVL_enum
935	{
936	AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
937	AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
938	AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
939	AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
940	} AC_WINTLVL_t;
941
942	/* Window mode state */
943	typedef enum AC_WSTATE_enum
944	{
945	AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
946	AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
947	AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
948	} AC_WSTATE_t;
949
950
951	/*
952	--------------------------------------------------------------------------
953	ADC - Analog/Digital Converter
954	--------------------------------------------------------------------------
955	*/
956
957	/* ADC Channel */
958	typedef struct ADC_CH_struct
959	{
960	register8_t CTRL; /* Control Register */
961	register8_t MUXCTRL; /* MUX Control */
962	register8_t INTCTRL; /* Channel Interrupt Control */
963	register8_t INTFLAGS; /* Interrupt Flags */
964	_WORDREGISTER(RES); /* Channel Result */
965	register8_t reserved_0x6;
966	register8_t reserved_0x7;
967	} ADC_CH_t;
968
969	/*
970	--------------------------------------------------------------------------
971	ADC - Analog/Digital Converter
972	--------------------------------------------------------------------------
973	*/
974
975	/* Analog-to-Digital Converter */
976	typedef struct ADC_struct
977	{
978	register8_t CTRLA; /* Control Register A */
979	register8_t CTRLB; /* Control Register B */
980	register8_t REFCTRL; /* Reference Control */
981	register8_t EVCTRL; /* Event Control */
982	register8_t PRESCALER; /* Clock Prescaler */
983	register8_t CALCTRL; /* Calibration Control Register */
984	register8_t INTFLAGS; /* Interrupt Flags */
985	register8_t reserved_0x07;
986	register8_t reserved_0x08;
987	register8_t reserved_0x09;
988	register8_t reserved_0x0A;
989	register8_t reserved_0x0B;
990	_WORDREGISTER(CAL); /* Calibration Value */
991	register8_t reserved_0x0E;
992	register8_t reserved_0x0F;
993	_WORDREGISTER(CH0RES); /* Channel 0 Result */
994	_WORDREGISTER(CMP); /* Compare Value */
995	register8_t reserved_0x1A;
996	register8_t reserved_0x1B;
997	register8_t reserved_0x1C;
998	register8_t reserved_0x1D;
999	register8_t reserved_0x1E;
1000	register8_t reserved_0x1F;
1001	ADC_CH_t CH0; /* ADC Channel 0 */
1002	} ADC_t;
1003
1004	/* Positive input multiplexer selection */
1005	typedef enum ADC_CH_MUXPOS_enum
1006	{
1007	ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
1008	ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
1009	ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
1010	ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
1011	ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
1012	ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
1013	ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
1014	ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
1015	} ADC_CH_MUXPOS_t;
1016
1017	/* Internal input multiplexer selections */
1018	typedef enum ADC_CH_MUXINT_enum
1019	{
1020	ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
1021	ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
1022	ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
1023	ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
1024	} ADC_CH_MUXINT_t;
1025
1026	/* Negative input multiplexer selection */
1027	typedef enum ADC_CH_MUXNEG_enum
1028	{
1029	ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
1030	ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
1031	ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
1032	ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
1033	ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */
1034	ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */
1035	ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */
1036	ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */
1037	} ADC_CH_MUXNEG_t;
1038
1039	/* Input mode */
1040	typedef enum ADC_CH_INPUTMODE_enum
1041	{
1042	ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
1043	ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */
1044	ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
1045	ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */
1046	} ADC_CH_INPUTMODE_t;
1047
1048	/* Gain factor */
1049	typedef enum ADC_CH_GAIN_enum
1050	{
1051	ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
1052	ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
1053	ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
1054	ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
1055	ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
1056	ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
1057	ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
1058	} ADC_CH_GAIN_t;
1059
1060	/* Conversion result resolution */
1061	typedef enum ADC_RESOLUTION_enum
1062	{
1063	ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
1064	ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
1065	ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
1066	} ADC_RESOLUTION_t;
1067
1068	/* Voltage reference selection */
1069	typedef enum ADC_REFSEL_enum
1070	{
1071	ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
1072	ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */
1073	ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
1074	ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
1075	} ADC_REFSEL_t;
1076
1077	/* Channel sweep selection */
1078	typedef enum ADC_SWEEP_enum
1079	{
1080	ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
1081	} ADC_SWEEP_t;
1082
1083	/* Event channel input selection */
1084	typedef enum ADC_EVSEL_enum
1085	{
1086	ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
1087	ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
1088	ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
1089	ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
1090	ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
1091	ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
1092	ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
1093	ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
1094	} ADC_EVSEL_t;
1095
1096	/* Event action selection */
1097	typedef enum ADC_EVACT_enum
1098	{
1099	ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
1100	ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
1101	} ADC_EVACT_t;
1102
1103	/* Interupt mode */
1104	typedef enum ADC_CH_INTMODE_enum
1105	{
1106	ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */
1107	ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */
1108	ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */
1109	} ADC_CH_INTMODE_t;
1110
1111	/* Interrupt level */
1112	typedef enum ADC_CH_INTLVL_enum
1113	{
1114	ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
1115	ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
1116	ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
1117	ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
1118	} ADC_CH_INTLVL_t;
1119
1120	/* Clock prescaler */
1121	typedef enum ADC_PRESCALER_enum
1122	{
1123	ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
1124	ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
1125	ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
1126	ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
1127	ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
1128	ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
1129	ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
1130	ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
1131	} ADC_PRESCALER_t;
1132
1133
1134	/*
1135	--------------------------------------------------------------------------
1136	RTC - Real-Time Clounter
1137	--------------------------------------------------------------------------
1138	*/
1139
1140	/* Real-Time Counter */
1141	typedef struct RTC_struct
1142	{
1143	register8_t CTRL; /* Control Register */
1144	register8_t STATUS; /* Status Register */
1145	register8_t INTCTRL; /* Interrupt Control Register */
1146	register8_t INTFLAGS; /* Interrupt Flags */
1147	register8_t TEMP; /* Temporary register */
1148	register8_t reserved_0x05;
1149	register8_t reserved_0x06;
1150	register8_t reserved_0x07;
1151	_WORDREGISTER(CNT); /* Count Register */
1152	_WORDREGISTER(PER); /* Period Register */
1153	_WORDREGISTER(COMP); /* Compare Register */
1154	} RTC_t;
1155
1156	/* Prescaler Factor */
1157	typedef enum RTC_PRESCALER_enum
1158	{
1159	RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
1160	RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
1161	RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
1162	RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
1163	RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
1164	RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
1165	RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
1166	RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
1167	} RTC_PRESCALER_t;
1168
1169	/* Compare Interrupt level */
1170	typedef enum RTC_COMPINTLVL_enum
1171	{
1172	RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1173	RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
1174	RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1175	RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
1176	} RTC_COMPINTLVL_t;
1177
1178	/* Overflow Interrupt level */
1179	typedef enum RTC_OVFINTLVL_enum
1180	{
1181	RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1182	RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1183	RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1184	RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1185	} RTC_OVFINTLVL_t;
1186
1187
1188	/*
1189	--------------------------------------------------------------------------
1190	EBI - External Bus Interface
1191	--------------------------------------------------------------------------
1192	*/
1193
1194	/* EBI Chip Select Module */
1195	typedef struct EBI_CS_struct
1196	{
1197	register8_t CTRLA; /* Chip Select Control Register A */
1198	register8_t CTRLB; /* Chip Select Control Register B */
1199	_WORDREGISTER(BASEADDR); /* Chip Select Base Address */
1200	} EBI_CS_t;
1201
1202	/*
1203	--------------------------------------------------------------------------
1204	EBI - External Bus Interface
1205	--------------------------------------------------------------------------
1206	*/
1207
1208	/* External Bus Interface */
1209	typedef struct EBI_struct
1210	{
1211	register8_t CTRL; /* Control */
1212	register8_t SDRAMCTRLA; /* SDRAM Control Register A */
1213	register8_t reserved_0x02;
1214	register8_t reserved_0x03;
1215	_WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
1216	_WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
1217	register8_t SDRAMCTRLB; /* SDRAM Control Register B */
1218	register8_t SDRAMCTRLC; /* SDRAM Control Register C */
1219	register8_t reserved_0x0A;
1220	register8_t reserved_0x0B;
1221	register8_t reserved_0x0C;
1222	register8_t reserved_0x0D;
1223	register8_t reserved_0x0E;
1224	register8_t reserved_0x0F;
1225	EBI_CS_t CS0; /* Chip Select 0 */
1226	EBI_CS_t CS1; /* Chip Select 1 */
1227	EBI_CS_t CS2; /* Chip Select 2 */
1228	EBI_CS_t CS3; /* Chip Select 3 */
1229	} EBI_t;
1230
1231	/* Chip Select adress space */
1232	typedef enum EBI_CS_ASPACE_enum
1233	{
1234	EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
1235	EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
1236	EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
1237	EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
1238	EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
1239	EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
1240	EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
1241	EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
1242	EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
1243	EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
1244	EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
1245	EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
1246	EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
1247	EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
1248	EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
1249	EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
1250	EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
1251	} EBI_CS_ASPACE_t;
1252
1253	/* */
1254	typedef enum EBI_CS_SRWS_enum
1255	{
1256	EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
1257	EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
1258	EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
1259	EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
1260	EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
1261	EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
1262	EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
1263	EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
1264	} EBI_CS_SRWS_t;
1265
1266	/* Chip Select address mode */
1267	typedef enum EBI_CS_MODE_enum
1268	{
1269	EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
1270	EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
1271	EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
1272	EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
1273	} EBI_CS_MODE_t;
1274
1275	/* Chip Select SDRAM mode */
1276	typedef enum EBI_CS_SDMODE_enum
1277	{
1278	EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
1279	EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
1280	} EBI_CS_SDMODE_t;
1281
1282	/* */
1283	typedef enum EBI_SDDATAW_enum
1284	{
1285	EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
1286	EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
1287	} EBI_SDDATAW_t;
1288
1289	/* */
1290	typedef enum EBI_LPCMODE_enum
1291	{
1292	EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
1293	EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
1294	} EBI_LPCMODE_t;
1295
1296	/* */
1297	typedef enum EBI_SRMODE_enum
1298	{
1299	EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
1300	EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
1301	EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
1302	EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
1303	} EBI_SRMODE_t;
1304
1305	/* */
1306	typedef enum EBI_IFMODE_enum
1307	{
1308	EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
1309	EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
1310	EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
1311	EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
1312	} EBI_IFMODE_t;
1313
1314	/* */
1315	typedef enum EBI_SDCOL_enum
1316	{
1317	EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
1318	EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
1319	EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
1320	EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
1321	} EBI_SDCOL_t;
1322
1323	/* */
1324	typedef enum EBI_MRDLY_enum
1325	{
1326	EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1327	EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1328	EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1329	EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1330	} EBI_MRDLY_t;
1331
1332	/* */
1333	typedef enum EBI_ROWCYCDLY_enum
1334	{
1335	EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1336	EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1337	EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1338	EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1339	EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1340	EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1341	EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1342	EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1343	} EBI_ROWCYCDLY_t;
1344
1345	/* */
1346	typedef enum EBI_RPDLY_enum
1347	{
1348	EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1349	EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1350	EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1351	EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1352	EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1353	EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1354	EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1355	EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1356	} EBI_RPDLY_t;
1357
1358	/* */
1359	typedef enum EBI_WRDLY_enum
1360	{
1361	EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
1362	EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
1363	EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
1364	EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
1365	} EBI_WRDLY_t;
1366
1367	/* */
1368	typedef enum EBI_ESRDLY_enum
1369	{
1370	EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
1371	EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
1372	EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
1373	EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
1374	EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
1375	EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
1376	EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
1377	EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
1378	} EBI_ESRDLY_t;
1379
1380	/* */
1381	typedef enum EBI_ROWCOLDLY_enum
1382	{
1383	EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
1384	EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
1385	EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
1386	EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
1387	EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
1388	EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
1389	EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
1390	EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
1391	} EBI_ROWCOLDLY_t;
1392
1393
1394	/*
1395	--------------------------------------------------------------------------
1396	TWI - Two-Wire Interface
1397	--------------------------------------------------------------------------
1398	*/
1399
1400	/* */
1401	typedef struct TWI_MASTER_struct
1402	{
1403	register8_t CTRLA; /* Control Register A */
1404	register8_t CTRLB; /* Control Register B */
1405	register8_t CTRLC; /* Control Register C */
1406	register8_t STATUS; /* Status Register */
1407	register8_t BAUD; /* Baurd Rate Control Register */
1408	register8_t ADDR; /* Address Register */
1409	register8_t DATA; /* Data Register */
1410	} TWI_MASTER_t;
1411
1412	/*
1413	--------------------------------------------------------------------------
1414	TWI - Two-Wire Interface
1415	--------------------------------------------------------------------------
1416	*/
1417
1418	/* */
1419	typedef struct TWI_SLAVE_struct
1420	{
1421	register8_t CTRLA; /* Control Register A */
1422	register8_t CTRLB; /* Control Register B */
1423	register8_t STATUS; /* Status Register */
1424	register8_t ADDR; /* Address Register */
1425	register8_t DATA; /* Data Register */
1426	register8_t ADDRMASK; /* Address Mask Register */
1427	} TWI_SLAVE_t;
1428
1429	/*
1430	--------------------------------------------------------------------------
1431	TWI - Two-Wire Interface
1432	--------------------------------------------------------------------------
1433	*/
1434
1435	/* Two-Wire Interface */
1436	typedef struct TWI_struct
1437	{
1438	register8_t CTRL; /* TWI Common Control Register */
1439	TWI_MASTER_t MASTER; /* TWI master module */
1440	TWI_SLAVE_t SLAVE; /* TWI slave module */
1441	} TWI_t;
1442
1443	/* Master Interrupt Level */
1444	typedef enum TWI_MASTER_INTLVL_enum
1445	{
1446	TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1447	TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1448	TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1449	TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
1450	} TWI_MASTER_INTLVL_t;
1451
1452	/* Inactive Timeout */
1453	typedef enum TWI_MASTER_TIMEOUT_enum
1454	{
1455	TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
1456	TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
1457	TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
1458	TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
1459	} TWI_MASTER_TIMEOUT_t;
1460
1461	/* Master Command */
1462	typedef enum TWI_MASTER_CMD_enum
1463	{
1464	TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
1465	TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */
1466	TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
1467	TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
1468	} TWI_MASTER_CMD_t;
1469
1470	/* Master Bus State */
1471	typedef enum TWI_MASTER_BUSSTATE_enum
1472	{
1473	TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
1474	TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
1475	TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */
1476	TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
1477	} TWI_MASTER_BUSSTATE_t;
1478
1479	/* Slave Interrupt Level */
1480	typedef enum TWI_SLAVE_INTLVL_enum
1481	{
1482	TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1483	TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
1484	TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
1485	TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
1486	} TWI_SLAVE_INTLVL_t;
1487
1488	/* Slave Command */
1489	typedef enum TWI_SLAVE_CMD_enum
1490	{
1491	TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
1492	TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */
1493	TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */
1494	} TWI_SLAVE_CMD_t;
1495
1496
1497	/*
1498	--------------------------------------------------------------------------
1499	PORT - Port Configuration
1500	--------------------------------------------------------------------------
1501	*/
1502
1503	/* I/O port Configuration */
1504	typedef struct PORTCFG_struct
1505	{
1506	register8_t MPCMASK; /* Multi-pin Configuration Mask */
1507	register8_t reserved_0x01;
1508	register8_t VPCTRLA; /* Virtual Port Control Register A */
1509	register8_t VPCTRLB; /* Virtual Port Control Register B */
1510	register8_t CLKEVOUT; /* Clock and Event Out Register */
1511	} PORTCFG_t;
1512
1513	/*
1514	--------------------------------------------------------------------------
1515	PORT - Port Configuration
1516	--------------------------------------------------------------------------
1517	*/
1518
1519	/* Virtual Port */
1520	typedef struct VPORT_struct
1521	{
1522	register8_t DIR; /* I/O Port Data Direction */
1523	register8_t OUT; /* I/O Port Output */
1524	register8_t IN; /* I/O Port Input */
1525	register8_t INTFLAGS; /* Interrupt Flag Register */
1526	} VPORT_t;
1527
1528	/*
1529	--------------------------------------------------------------------------
1530	PORT - Port Configuration
1531	--------------------------------------------------------------------------
1532	*/
1533
1534	/* I/O Ports */
1535	typedef struct PORT_struct
1536	{
1537	register8_t DIR; /* I/O Port Data Direction */
1538	register8_t DIRSET; /* I/O Port Data Direction Set */
1539	register8_t DIRCLR; /* I/O Port Data Direction Clear */
1540	register8_t DIRTGL; /* I/O Port Data Direction Toggle */
1541	register8_t OUT; /* I/O Port Output */
1542	register8_t OUTSET; /* I/O Port Output Set */
1543	register8_t OUTCLR; /* I/O Port Output Clear */
1544	register8_t OUTTGL; /* I/O Port Output Toggle */
1545	register8_t IN; /* I/O port Input */
1546	register8_t INTCTRL; /* Interrupt Control Register */
1547	register8_t INT0MASK; /* Port Interrupt 0 Mask */
1548	register8_t INT1MASK; /* Port Interrupt 1 Mask */
1549	register8_t INTFLAGS; /* Interrupt Flag Register */
1550	register8_t reserved_0x0D;
1551	register8_t reserved_0x0E;
1552	register8_t reserved_0x0F;
1553	register8_t PIN0CTRL; /* Pin 0 Control Register */
1554	register8_t PIN1CTRL; /* Pin 1 Control Register */
1555	register8_t PIN2CTRL; /* Pin 2 Control Register */
1556	register8_t PIN3CTRL; /* Pin 3 Control Register */
1557	register8_t PIN4CTRL; /* Pin 4 Control Register */
1558	register8_t PIN5CTRL; /* Pin 5 Control Register */
1559	register8_t PIN6CTRL; /* Pin 6 Control Register */
1560	register8_t PIN7CTRL; /* Pin 7 Control Register */
1561	} PORT_t;
1562
1563	/* Virtual Port 0 Mapping */
1564	typedef enum PORTCFG_VP0MAP_enum
1565	{
1566	PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1567	PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1568	PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1569	PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1570	PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1571	PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1572	PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1573	PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1574	PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1575	PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1576	PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1577	PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1578	PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1579	PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1580	PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1581	PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1582	} PORTCFG_VP0MAP_t;
1583
1584	/* Virtual Port 1 Mapping */
1585	typedef enum PORTCFG_VP1MAP_enum
1586	{
1587	PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1588	PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1589	PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1590	PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1591	PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1592	PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1593	PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1594	PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1595	PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1596	PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1597	PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1598	PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1599	PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1600	PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1601	PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1602	PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1603	} PORTCFG_VP1MAP_t;
1604
1605	/* Virtual Port 2 Mapping */
1606	typedef enum PORTCFG_VP2MAP_enum
1607	{
1608	PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
1609	PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
1610	PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
1611	PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
1612	PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
1613	PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
1614	PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
1615	PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
1616	PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
1617	PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
1618	PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
1619	PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
1620	PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
1621	PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
1622	PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
1623	PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
1624	} PORTCFG_VP2MAP_t;
1625
1626	/* Virtual Port 3 Mapping */
1627	typedef enum PORTCFG_VP3MAP_enum
1628	{
1629	PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
1630	PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
1631	PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
1632	PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
1633	PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
1634	PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
1635	PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
1636	PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
1637	PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
1638	PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
1639	PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
1640	PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
1641	PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
1642	PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
1643	PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
1644	PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
1645	} PORTCFG_VP3MAP_t;
1646
1647	/* Clock Output Port */
1648	typedef enum PORTCFG_CLKOUT_enum
1649	{
1650	PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */
1651	PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */
1652	PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */
1653	PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */
1654	} PORTCFG_CLKOUT_t;
1655
1656	/* Event Output Port */
1657	typedef enum PORTCFG_EVOUT_enum
1658	{
1659	PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
1660	PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */
1661	PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */
1662	PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */
1663	} PORTCFG_EVOUT_t;
1664
1665	/* Port Interrupt 0 Level */
1666	typedef enum PORT_INT0LVL_enum
1667	{
1668	PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1669	PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
1670	PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
1671	PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
1672	} PORT_INT0LVL_t;
1673
1674	/* Port Interrupt 1 Level */
1675	typedef enum PORT_INT1LVL_enum
1676	{
1677	PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1678	PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
1679	PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
1680	PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
1681	} PORT_INT1LVL_t;
1682
1683	/* Output/Pull Configuration */
1684	typedef enum PORT_OPC_enum
1685	{
1686	PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
1687	PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */
1688	PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
1689	PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
1690	PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
1691	PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
1692	PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
1693	PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
1694	} PORT_OPC_t;
1695
1696	/* Input/Sense Configuration */
1697	typedef enum PORT_ISC_enum
1698	{
1699	PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
1700	PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
1701	PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
1702	PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
1703	PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
1704	} PORT_ISC_t;
1705
1706
1707	/*
1708	--------------------------------------------------------------------------
1709	TC - 16-bit Timer/Counter With PWM
1710	--------------------------------------------------------------------------
1711	*/
1712
1713	/* 16-bit Timer/Counter 0 */
1714	typedef struct TC0_struct
1715	{
1716	register8_t CTRLA; /* Control Register A */
1717	register8_t CTRLB; /* Control Register B */
1718	register8_t CTRLC; /* Control register C */
1719	register8_t CTRLD; /* Control Register D */
1720	register8_t CTRLE; /* Control Register E */
1721	register8_t reserved_0x05;
1722	register8_t INTCTRLA; /* Interrupt Control Register A */
1723	register8_t INTCTRLB; /* Interrupt Control Register B */
1724	register8_t CTRLFCLR; /* Control Register F Clear */
1725	register8_t CTRLFSET; /* Control Register F Set */
1726	register8_t CTRLGCLR; /* Control Register G Clear */
1727	register8_t CTRLGSET; /* Control Register G Set */
1728	register8_t INTFLAGS; /* Interrupt Flag Register */
1729	register8_t reserved_0x0D;
1730	register8_t reserved_0x0E;
1731	register8_t TEMP; /* Temporary Register For 16-bit Access */
1732	register8_t reserved_0x10;
1733	register8_t reserved_0x11;
1734	register8_t reserved_0x12;
1735	register8_t reserved_0x13;
1736	register8_t reserved_0x14;
1737	register8_t reserved_0x15;
1738	register8_t reserved_0x16;
1739	register8_t reserved_0x17;
1740	register8_t reserved_0x18;
1741	register8_t reserved_0x19;
1742	register8_t reserved_0x1A;
1743	register8_t reserved_0x1B;
1744	register8_t reserved_0x1C;
1745	register8_t reserved_0x1D;
1746	register8_t reserved_0x1E;
1747	register8_t reserved_0x1F;
1748	_WORDREGISTER(CNT); /* Count */
1749	register8_t reserved_0x22;
1750	register8_t reserved_0x23;
1751	register8_t reserved_0x24;
1752	register8_t reserved_0x25;
1753	_WORDREGISTER(PER); /* Period */
1754	_WORDREGISTER(CCA); /* Compare or Capture A */
1755	_WORDREGISTER(CCB); /* Compare or Capture B */
1756	_WORDREGISTER(CCC); /* Compare or Capture C */
1757	_WORDREGISTER(CCD); /* Compare or Capture D */
1758	register8_t reserved_0x30;
1759	register8_t reserved_0x31;
1760	register8_t reserved_0x32;
1761	register8_t reserved_0x33;
1762	register8_t reserved_0x34;
1763	register8_t reserved_0x35;
1764	_WORDREGISTER(PERBUF); /* Period Buffer */
1765	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1766	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1767	_WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
1768	_WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
1769	} TC0_t;
1770
1771	/*
1772	--------------------------------------------------------------------------
1773	TC - 16-bit Timer/Counter With PWM
1774	--------------------------------------------------------------------------
1775	*/
1776
1777	/* 16-bit Timer/Counter 1 */
1778	typedef struct TC1_struct
1779	{
1780	register8_t CTRLA; /* Control Register A */
1781	register8_t CTRLB; /* Control Register B */
1782	register8_t CTRLC; /* Control register C */
1783	register8_t CTRLD; /* Control Register D */
1784	register8_t CTRLE; /* Control Register E */
1785	register8_t reserved_0x05;
1786	register8_t INTCTRLA; /* Interrupt Control Register A */
1787	register8_t INTCTRLB; /* Interrupt Control Register B */
1788	register8_t CTRLFCLR; /* Control Register F Clear */
1789	register8_t CTRLFSET; /* Control Register F Set */
1790	register8_t CTRLGCLR; /* Control Register G Clear */
1791	register8_t CTRLGSET; /* Control Register G Set */
1792	register8_t INTFLAGS; /* Interrupt Flag Register */
1793	register8_t reserved_0x0D;
1794	register8_t reserved_0x0E;
1795	register8_t TEMP; /* Temporary Register For 16-bit Access */
1796	register8_t reserved_0x10;
1797	register8_t reserved_0x11;
1798	register8_t reserved_0x12;
1799	register8_t reserved_0x13;
1800	register8_t reserved_0x14;
1801	register8_t reserved_0x15;
1802	register8_t reserved_0x16;
1803	register8_t reserved_0x17;
1804	register8_t reserved_0x18;
1805	register8_t reserved_0x19;
1806	register8_t reserved_0x1A;
1807	register8_t reserved_0x1B;
1808	register8_t reserved_0x1C;
1809	register8_t reserved_0x1D;
1810	register8_t reserved_0x1E;
1811	register8_t reserved_0x1F;
1812	_WORDREGISTER(CNT); /* Count */
1813	register8_t reserved_0x22;
1814	register8_t reserved_0x23;
1815	register8_t reserved_0x24;
1816	register8_t reserved_0x25;
1817	_WORDREGISTER(PER); /* Period */
1818	_WORDREGISTER(CCA); /* Compare or Capture A */
1819	_WORDREGISTER(CCB); /* Compare or Capture B */
1820	register8_t reserved_0x2C;
1821	register8_t reserved_0x2D;
1822	register8_t reserved_0x2E;
1823	register8_t reserved_0x2F;
1824	register8_t reserved_0x30;
1825	register8_t reserved_0x31;
1826	register8_t reserved_0x32;
1827	register8_t reserved_0x33;
1828	register8_t reserved_0x34;
1829	register8_t reserved_0x35;
1830	_WORDREGISTER(PERBUF); /* Period Buffer */
1831	_WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
1832	_WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
1833	} TC1_t;
1834
1835	/*
1836	--------------------------------------------------------------------------
1837	TC - 16-bit Timer/Counter With PWM
1838	--------------------------------------------------------------------------
1839	*/
1840
1841	/* Advanced Waveform Extension */
1842	typedef struct AWEX_struct
1843	{
1844	register8_t CTRL; /* Control Register */
1845	register8_t reserved_0x01;
1846	register8_t FDEMASK; /* Fault Detection Event Mask */
1847	register8_t FDCTRL; /* Fault Detection Control Register */
1848	register8_t STATUS; /* Status Register */
1849	register8_t reserved_0x05;
1850	register8_t DTBOTH; /* Dead Time Both Sides */
1851	register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
1852	register8_t DTLS; /* Dead Time Low Side */
1853	register8_t DTHS; /* Dead Time High Side */
1854	register8_t DTLSBUF; /* Dead Time Low Side Buffer */
1855	register8_t DTHSBUF; /* Dead Time High Side Buffer */
1856	register8_t OUTOVEN; /* Output Override Enable */
1857	} AWEX_t;
1858
1859	/*
1860	--------------------------------------------------------------------------
1861	TC - 16-bit Timer/Counter With PWM
1862	--------------------------------------------------------------------------
1863	*/
1864
1865	/* High-Resolution Extension */
1866	typedef struct HIRES_struct
1867	{
1868	register8_t CTRLA; /* Control Register */
1869	} HIRES_t;
1870
1871	/* Clock Selection */
1872	typedef enum TC_CLKSEL_enum
1873	{
1874	TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
1875	TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
1876	TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
1877	TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
1878	TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
1879	TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
1880	TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
1881	TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
1882	TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
1883	TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
1884	TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
1885	TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
1886	TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
1887	TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
1888	TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
1889	TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
1890	} TC_CLKSEL_t;
1891
1892	/* Waveform Generation Mode */
1893	typedef enum TC_WGMODE_enum
1894	{
1895	TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
1896	TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
1897	TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
1898	TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
1899	TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
1900	TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
1901	} TC_WGMODE_t;
1902
1903	/* Event Action */
1904	typedef enum TC_EVACT_enum
1905	{
1906	TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
1907	TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
1908	TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
1909	TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
1910	TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
1911	TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
1912	TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
1913	} TC_EVACT_t;
1914
1915	/* Event Selection */
1916	typedef enum TC_EVSEL_enum
1917	{
1918	TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
1919	TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
1920	TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
1921	TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
1922	TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
1923	TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
1924	TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
1925	TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
1926	TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
1927	} TC_EVSEL_t;
1928
1929	/* Error Interrupt Level */
1930	typedef enum TC_ERRINTLVL_enum
1931	{
1932	TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1933	TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
1934	TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1935	TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
1936	} TC_ERRINTLVL_t;
1937
1938	/* Overflow Interrupt Level */
1939	typedef enum TC_OVFINTLVL_enum
1940	{
1941	TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1942	TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
1943	TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1944	TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
1945	} TC_OVFINTLVL_t;
1946
1947	/* Compare or Capture D Interrupt Level */
1948	typedef enum TC_CCDINTLVL_enum
1949	{
1950	TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
1951	TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
1952	TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
1953	TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
1954	} TC_CCDINTLVL_t;
1955
1956	/* Compare or Capture C Interrupt Level */
1957	typedef enum TC_CCCINTLVL_enum
1958	{
1959	TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
1960	TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
1961	TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
1962	TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
1963	} TC_CCCINTLVL_t;
1964
1965	/* Compare or Capture B Interrupt Level */
1966	typedef enum TC_CCBINTLVL_enum
1967	{
1968	TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
1969	TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
1970	TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
1971	TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
1972	} TC_CCBINTLVL_t;
1973
1974	/* Compare or Capture A Interrupt Level */
1975	typedef enum TC_CCAINTLVL_enum
1976	{
1977	TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
1978	TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
1979	TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
1980	TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
1981	} TC_CCAINTLVL_t;
1982
1983	/* Timer/Counter Command */
1984	typedef enum TC_CMD_enum
1985	{
1986	TC_CMD_NONE_gc = (0x00<<2), /* No Command */
1987	TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
1988	TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
1989	TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
1990	} TC_CMD_t;
1991
1992	/* Fault Detect Action */
1993	typedef enum AWEX_FDACT_enum
1994	{
1995	AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
1996	AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
1997	AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
1998	} AWEX_FDACT_t;
1999
2000	/* High Resolution Enable */
2001	typedef enum HIRES_HREN_enum
2002	{
2003	HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
2004	HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */
2005	HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */
2006	HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */
2007	} HIRES_HREN_t;
2008
2009
2010	/*
2011	--------------------------------------------------------------------------
2012	USART - Universal Asynchronous Receiver-Transmitter
2013	--------------------------------------------------------------------------
2014	*/
2015
2016	/* Universal Synchronous/Asynchronous Receiver/Transmitter */
2017	typedef struct USART_struct
2018	{
2019	register8_t DATA; /* Data Register */
2020	register8_t STATUS; /* Status Register */
2021	register8_t reserved_0x02;
2022	register8_t CTRLA; /* Control Register A */
2023	register8_t CTRLB; /* Control Register B */
2024	register8_t CTRLC; /* Control Register C */
2025	register8_t BAUDCTRLA; /* Baud Rate Control Register A */
2026	register8_t BAUDCTRLB; /* Baud Rate Control Register B */
2027	} USART_t;
2028
2029	/* Receive Complete Interrupt level */
2030	typedef enum USART_RXCINTLVL_enum
2031	{
2032	USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
2033	USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
2034	USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
2035	USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
2036	} USART_RXCINTLVL_t;
2037
2038	/* Transmit Complete Interrupt level */
2039	typedef enum USART_TXCINTLVL_enum
2040	{
2041	USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
2042	USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
2043	USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
2044	USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
2045	} USART_TXCINTLVL_t;
2046
2047	/* Data Register Empty Interrupt level */
2048	typedef enum USART_DREINTLVL_enum
2049	{
2050	USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2051	USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
2052	USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
2053	USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
2054	} USART_DREINTLVL_t;
2055
2056	/* Character Size */
2057	typedef enum USART_CHSIZE_enum
2058	{
2059	USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
2060	USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
2061	USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
2062	USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
2063	USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
2064	} USART_CHSIZE_t;
2065
2066	/* Communication Mode */
2067	typedef enum USART_CMODE_enum
2068	{
2069	USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
2070	USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
2071	USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
2072	USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
2073	} USART_CMODE_t;
2074
2075	/* Parity Mode */
2076	typedef enum USART_PMODE_enum
2077	{
2078	USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
2079	USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
2080	USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
2081	} USART_PMODE_t;
2082
2083
2084	/*
2085	--------------------------------------------------------------------------
2086	SPI - Serial Peripheral Interface
2087	--------------------------------------------------------------------------
2088	*/
2089
2090	/* Serial Peripheral Interface */
2091	typedef struct SPI_struct
2092	{
2093	register8_t CTRL; /* Control Register */
2094	register8_t INTCTRL; /* Interrupt Control Register */
2095	register8_t STATUS; /* Status Register */
2096	register8_t DATA; /* Data Register */
2097	} SPI_t;
2098
2099	/* SPI Mode */
2100	typedef enum SPI_MODE_enum
2101	{
2102	SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
2103	SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
2104	SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
2105	SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
2106	} SPI_MODE_t;
2107
2108	/* Prescaler setting */
2109	typedef enum SPI_PRESCALER_enum
2110	{
2111	SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
2112	SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
2113	SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
2114	SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
2115	} SPI_PRESCALER_t;
2116
2117	/* Interrupt level */
2118	typedef enum SPI_INTLVL_enum
2119	{
2120	SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
2121	SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
2122	SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
2123	SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
2124	} SPI_INTLVL_t;
2125
2126
2127	/*
2128	--------------------------------------------------------------------------
2129	IRCOM - IR Communication Module
2130	--------------------------------------------------------------------------
2131	*/
2132
2133	/* IR Communication Module */
2134	typedef struct IRCOM_struct
2135	{
2136	register8_t CTRL; /* Control Register */
2137	register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
2138	register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
2139	} IRCOM_t;
2140
2141	/* Event channel selection */
2142	typedef enum IRDA_EVSEL_enum
2143	{
2144	IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
2145	IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
2146	IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
2147	IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
2148	IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
2149	IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
2150	IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
2151	IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
2152	IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
2153	} IRDA_EVSEL_t;
2154
2155
2156
2157	/*
2158	==========================================================================
2159	IO Module Instances. Mapped to memory.
2160	==========================================================================
2161	*/
2162
2163	#define GPIO ((GPIO_t ) 0x0000) /* General Purpose IO Registers */
2164	#define VPORT0 ((VPORT_t ) 0x0010) /* Virtual Port 0 */
2165	#define VPORT1 ((VPORT_t ) 0x0014) /* Virtual Port 1 */
2166	#define VPORT2 ((VPORT_t ) 0x0018) /* Virtual Port 2 */
2167	#define VPORT3 ((VPORT_t ) 0x001C) /* Virtual Port 3 */
2168	#define OCD ((OCD_t ) 0x002E) /* On-Chip Debug System */
2169	#define CPU ((CPU_t ) 0x0030) /* CPU Registers */
2170	#define CLK ((CLK_t ) 0x0040) /* Clock System */
2171	#define SLEEP ((SLEEP_t ) 0x0048) /* Sleep Controller */
2172	#define OSC ((OSC_t ) 0x0050) /* Oscillator Control */
2173	#define DFLLRC32M ((DFLL_t ) 0x0060) /* DFLL for 32MHz RC Oscillator */
2174	#define DFLLRC2M ((DFLL_t ) 0x0068) /* DFLL for 2MHz RC Oscillator */
2175	#define PR ((PR_t ) 0x0070) /* Power Reduction */
2176	#define RST ((RST_t ) 0x0078) /* Reset Controller */
2177	#define WDT ((WDT_t ) 0x0080) /* Watch-Dog Timer */
2178	#define MCU ((MCU_t ) 0x0090) /* MCU Control */
2179	#define PMIC ((PMIC_t ) 0x00A0) /* Programmable Interrupt Controller */
2180	#define PORTCFG ((PORTCFG_t ) 0x00B0) /* Port Configuration */
2181	#define EVSYS ((EVSYS_t ) 0x0180) /* Event System */
2182	#define NVM ((NVM_t ) 0x01C0) /* Non Volatile Memory Controller */
2183	#define ADCA ((ADC_t ) 0x0200) /* Analog to Digital Converter A */
2184	#define ACA ((AC_t ) 0x0380) /* Analog Comparator A */
2185	#define RTC ((RTC_t ) 0x0400) /* Real-Time Counter */
2186	#define TWIC ((TWI_t ) 0x0480) /* Two-Wire Interface C */
2187	#define PORTA ((PORT_t ) 0x0600) /* Port A */
2188	#define PORTB ((PORT_t ) 0x0620) /* Port B */
2189	#define PORTC ((PORT_t ) 0x0640) /* Port C */
2190	#define PORTD ((PORT_t ) 0x0660) /* Port D */
2191	#define PORTE ((PORT_t ) 0x0680) /* Port E */
2192	#define PORTF ((PORT_t ) 0x06A0) /* Port F */
2193	#define PORTR ((PORT_t ) 0x07E0) /* Port R */
2194	#define TCC0 ((TC0_t ) 0x0800) /* Timer/Counter C0 */
2195	#define TCC1 ((TC1_t ) 0x0840) /* Timer/Counter C1 */
2196	#define AWEXC ((AWEX_t ) 0x0880) /* Advanced Waveform Extension C */
2197	#define HIRESC ((HIRES_t ) 0x0890) /* High-Resolution Extension C */
2198	#define USARTC0 ((USART_t ) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */
2199	#define SPIC ((SPI_t ) 0x08C0) /* Serial Peripheral Interface C */
2200	#define IRCOM ((IRCOM_t ) 0x08F8) /* IR Communication Module */
2201	#define TCD0 ((TC0_t ) 0x0900) /* Timer/Counter D0 */
2202	#define USARTD0 ((USART_t ) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */
2203	#define SPID ((SPI_t ) 0x09C0) /* Serial Peripheral Interface D */
2204	#define TCE0 ((TC0_t ) 0x0A00) /* Timer/Counter E0 */
2205	#define AWEXE ((AWEX_t ) 0x0A80) /* Advanced Waveform Extension E */
2206	#define USARTE0 ((USART_t ) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */
2207	#define SPIE ((SPI_t ) 0x0AC0) /* Serial Peripheral Interface E */
2208	#define TCF0 ((TC0_t ) 0x0B00) /* Timer/Counter F0 */
2209
2210
2211	#endif /* !defined (__ASSEMBLER__) */
2212
2213
2214	/* ========== Flattened fully qualified IO register names ========== */
2215
2216	/* GPIO - General Purpose IO Registers */
2217	#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
2218	#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
2219	#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
2220	#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
2221	#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
2222	#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
2223	#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
2224	#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
2225	#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
2226	#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
2227	#define GPIO_GPIORA _SFR_MEM8(0x000A)
2228	#define GPIO_GPIORB _SFR_MEM8(0x000B)
2229	#define GPIO_GPIORC _SFR_MEM8(0x000C)
2230	#define GPIO_GPIORD _SFR_MEM8(0x000D)
2231	#define GPIO_GPIORE _SFR_MEM8(0x000E)
2232	#define GPIO_GPIORF _SFR_MEM8(0x000F)
2233
2234	/* VPORT0 - Virtual Port 0 */
2235	#define VPORT0_DIR _SFR_MEM8(0x0010)
2236	#define VPORT0_OUT _SFR_MEM8(0x0011)
2237	#define VPORT0_IN _SFR_MEM8(0x0012)
2238	#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
2239
2240	/* VPORT1 - Virtual Port 1 */
2241	#define VPORT1_DIR _SFR_MEM8(0x0014)
2242	#define VPORT1_OUT _SFR_MEM8(0x0015)
2243	#define VPORT1_IN _SFR_MEM8(0x0016)
2244	#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
2245
2246	/* VPORT2 - Virtual Port 2 */
2247	#define VPORT2_DIR _SFR_MEM8(0x0018)
2248	#define VPORT2_OUT _SFR_MEM8(0x0019)
2249	#define VPORT2_IN _SFR_MEM8(0x001A)
2250	#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
2251
2252	/* VPORT3 - Virtual Port 3 */
2253	#define VPORT3_DIR _SFR_MEM8(0x001C)
2254	#define VPORT3_OUT _SFR_MEM8(0x001D)
2255	#define VPORT3_IN _SFR_MEM8(0x001E)
2256	#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
2257
2258	/* OCD - On-Chip Debug System */
2259	#define OCD_OCDR0 _SFR_MEM8(0x002E)
2260	#define OCD_OCDR1 _SFR_MEM8(0x002F)
2261
2262	/* CPU - CPU Registers */
2263	#define CPU_CCP _SFR_MEM8(0x0034)
2264	#define CPU_RAMPD _SFR_MEM8(0x0038)
2265	#define CPU_RAMPX _SFR_MEM8(0x0039)
2266	#define CPU_RAMPY _SFR_MEM8(0x003A)
2267	#define CPU_RAMPZ _SFR_MEM8(0x003B)
2268	#define CPU_EIND _SFR_MEM8(0x003C)
2269	#define CPU_SPL _SFR_MEM8(0x003D)
2270	#define CPU_SPH _SFR_MEM8(0x003E)
2271	#define CPU_SREG _SFR_MEM8(0x003F)
2272
2273	/* CLK - Clock System */
2274	#define CLK_CTRL _SFR_MEM8(0x0040)
2275	#define CLK_PSCTRL _SFR_MEM8(0x0041)
2276	#define CLK_LOCK _SFR_MEM8(0x0042)
2277	#define CLK_RTCCTRL _SFR_MEM8(0x0043)
2278
2279	/* SLEEP - Sleep Controller */
2280	#define SLEEP_CTRL _SFR_MEM8(0x0048)
2281
2282	/* OSC - Oscillator Control */
2283	#define OSC_CTRL _SFR_MEM8(0x0050)
2284	#define OSC_STATUS _SFR_MEM8(0x0051)
2285	#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
2286	#define OSC_XOSCFAIL _SFR_MEM8(0x0053)
2287	#define OSC_RC32KCAL _SFR_MEM8(0x0054)
2288	#define OSC_PLLCTRL _SFR_MEM8(0x0055)
2289	#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
2290
2291	/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
2292	#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
2293	#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
2294	#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
2295	#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
2296	#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
2297	#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
2298
2299	/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
2300	#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
2301	#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
2302	#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
2303	#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
2304	#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
2305	#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
2306
2307	/* PR - Power Reduction */
2308	#define PR_PRGEN _SFR_MEM8(0x0070)
2309	#define PR_PRPA _SFR_MEM8(0x0071)
2310	#define PR_PRPB _SFR_MEM8(0x0072)
2311	#define PR_PRPC _SFR_MEM8(0x0073)
2312	#define PR_PRPD _SFR_MEM8(0x0074)
2313	#define PR_PRPE _SFR_MEM8(0x0075)
2314	#define PR_PRPF _SFR_MEM8(0x0076)
2315
2316	/* RST - Reset Controller */
2317	#define RST_STATUS _SFR_MEM8(0x0078)
2318	#define RST_CTRL _SFR_MEM8(0x0079)
2319
2320	/* WDT - Watch-Dog Timer */
2321	#define WDT_CTRL _SFR_MEM8(0x0080)
2322	#define WDT_WINCTRL _SFR_MEM8(0x0081)
2323	#define WDT_STATUS _SFR_MEM8(0x0082)
2324
2325	/* MCU - MCU Control */
2326	#define MCU_DEVID0 _SFR_MEM8(0x0090)
2327	#define MCU_DEVID1 _SFR_MEM8(0x0091)
2328	#define MCU_DEVID2 _SFR_MEM8(0x0092)
2329	#define MCU_REVID _SFR_MEM8(0x0093)
2330	#define MCU_JTAGUID _SFR_MEM8(0x0094)
2331	#define MCU_MCUCR _SFR_MEM8(0x0096)
2332	#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
2333	#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
2334
2335	/* PMIC - Programmable Interrupt Controller */
2336	#define PMIC_STATUS _SFR_MEM8(0x00A0)
2337	#define PMIC_INTPRI _SFR_MEM8(0x00A1)
2338	#define PMIC_CTRL _SFR_MEM8(0x00A2)
2339
2340	/* PORTCFG - Port Configuration */
2341	#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
2342	#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
2343	#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
2344	#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
2345
2346	/* EVSYS - Event System */
2347	#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
2348	#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
2349	#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
2350	#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
2351	#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
2352	#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
2353	#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
2354	#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
2355	#define EVSYS_STROBE _SFR_MEM8(0x0190)
2356	#define EVSYS_DATA _SFR_MEM8(0x0191)
2357
2358	/* NVM - Non Volatile Memory Controller */
2359	#define NVM_ADDR0 _SFR_MEM8(0x01C0)
2360	#define NVM_ADDR1 _SFR_MEM8(0x01C1)
2361	#define NVM_ADDR2 _SFR_MEM8(0x01C2)
2362	#define NVM_DATA0 _SFR_MEM8(0x01C4)
2363	#define NVM_DATA1 _SFR_MEM8(0x01C5)
2364	#define NVM_DATA2 _SFR_MEM8(0x01C6)
2365	#define NVM_CMD _SFR_MEM8(0x01CA)
2366	#define NVM_CTRLA _SFR_MEM8(0x01CB)
2367	#define NVM_CTRLB _SFR_MEM8(0x01CC)
2368	#define NVM_INTCTRL _SFR_MEM8(0x01CD)
2369	#define NVM_STATUS _SFR_MEM8(0x01CF)
2370	#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
2371
2372	/* ADCA - Analog to Digital Converter A */
2373	#define ADCA_CTRLA _SFR_MEM8(0x0200)
2374	#define ADCA_CTRLB _SFR_MEM8(0x0201)
2375	#define ADCA_REFCTRL _SFR_MEM8(0x0202)
2376	#define ADCA_EVCTRL _SFR_MEM8(0x0203)
2377	#define ADCA_PRESCALER _SFR_MEM8(0x0204)
2378	#define ADCA_CALCTRL _SFR_MEM8(0x0205)
2379	#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
2380	#define ADCA_CAL _SFR_MEM16(0x020C)
2381	#define ADCA_CH0RES _SFR_MEM16(0x0210)
2382	#define ADCA_CMP _SFR_MEM16(0x0218)
2383	#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
2384	#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
2385	#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
2386	#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
2387	#define ADCA_CH0_RES _SFR_MEM16(0x0224)
2388
2389	/* ACA - Analog Comparator A */
2390	#define ACA_AC0CTRL _SFR_MEM8(0x0380)
2391	#define ACA_AC1CTRL _SFR_MEM8(0x0381)
2392	#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
2393	#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
2394	#define ACA_CTRLA _SFR_MEM8(0x0384)
2395	#define ACA_CTRLB _SFR_MEM8(0x0385)
2396	#define ACA_WINCTRL _SFR_MEM8(0x0386)
2397	#define ACA_STATUS _SFR_MEM8(0x0387)
2398
2399	/* RTC - Real-Time Counter */
2400	#define RTC_CTRL _SFR_MEM8(0x0400)
2401	#define RTC_STATUS _SFR_MEM8(0x0401)
2402	#define RTC_INTCTRL _SFR_MEM8(0x0402)
2403	#define RTC_INTFLAGS _SFR_MEM8(0x0403)
2404	#define RTC_TEMP _SFR_MEM8(0x0404)
2405	#define RTC_CNT _SFR_MEM16(0x0408)
2406	#define RTC_PER _SFR_MEM16(0x040A)
2407	#define RTC_COMP _SFR_MEM16(0x040C)
2408
2409	/* TWIC - Two-Wire Interface C */
2410	#define TWIC_CTRL _SFR_MEM8(0x0480)
2411	#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482)
2412	#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483)
2413	#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484)
2414	#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485)
2415	#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486)
2416	#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487)
2417	#define TWIC_MASTER_DATA _SFR_MEM8(0x0488)
2418	#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
2419	#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
2420	#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
2421	#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
2422	#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
2423	#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
2424
2425	/* PORTA - Port A */
2426	#define PORTA_DIR _SFR_MEM8(0x0600)
2427	#define PORTA_DIRSET _SFR_MEM8(0x0601)
2428	#define PORTA_DIRCLR _SFR_MEM8(0x0602)
2429	#define PORTA_DIRTGL _SFR_MEM8(0x0603)
2430	#define PORTA_OUT _SFR_MEM8(0x0604)
2431	#define PORTA_OUTSET _SFR_MEM8(0x0605)
2432	#define PORTA_OUTCLR _SFR_MEM8(0x0606)
2433	#define PORTA_OUTTGL _SFR_MEM8(0x0607)
2434	#define PORTA_IN _SFR_MEM8(0x0608)
2435	#define PORTA_INTCTRL _SFR_MEM8(0x0609)
2436	#define PORTA_INT0MASK _SFR_MEM8(0x060A)
2437	#define PORTA_INT1MASK _SFR_MEM8(0x060B)
2438	#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
2439	#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
2440	#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
2441	#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
2442	#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
2443	#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
2444	#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
2445	#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
2446	#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
2447
2448	/* PORTB - Port B */
2449	#define PORTB_DIR _SFR_MEM8(0x0620)
2450	#define PORTB_DIRSET _SFR_MEM8(0x0621)
2451	#define PORTB_DIRCLR _SFR_MEM8(0x0622)
2452	#define PORTB_DIRTGL _SFR_MEM8(0x0623)
2453	#define PORTB_OUT _SFR_MEM8(0x0624)
2454	#define PORTB_OUTSET _SFR_MEM8(0x0625)
2455	#define PORTB_OUTCLR _SFR_MEM8(0x0626)
2456	#define PORTB_OUTTGL _SFR_MEM8(0x0627)
2457	#define PORTB_IN _SFR_MEM8(0x0628)
2458	#define PORTB_INTCTRL _SFR_MEM8(0x0629)
2459	#define PORTB_INT0MASK _SFR_MEM8(0x062A)
2460	#define PORTB_INT1MASK _SFR_MEM8(0x062B)
2461	#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
2462	#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
2463	#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
2464	#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
2465	#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
2466	#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
2467	#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
2468	#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
2469	#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
2470
2471	/* PORTC - Port C */
2472	#define PORTC_DIR _SFR_MEM8(0x0640)
2473	#define PORTC_DIRSET _SFR_MEM8(0x0641)
2474	#define PORTC_DIRCLR _SFR_MEM8(0x0642)
2475	#define PORTC_DIRTGL _SFR_MEM8(0x0643)
2476	#define PORTC_OUT _SFR_MEM8(0x0644)
2477	#define PORTC_OUTSET _SFR_MEM8(0x0645)
2478	#define PORTC_OUTCLR _SFR_MEM8(0x0646)
2479	#define PORTC_OUTTGL _SFR_MEM8(0x0647)
2480	#define PORTC_IN _SFR_MEM8(0x0648)
2481	#define PORTC_INTCTRL _SFR_MEM8(0x0649)
2482	#define PORTC_INT0MASK _SFR_MEM8(0x064A)
2483	#define PORTC_INT1MASK _SFR_MEM8(0x064B)
2484	#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
2485	#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
2486	#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
2487	#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
2488	#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
2489	#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
2490	#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
2491	#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
2492	#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
2493
2494	/* PORTD - Port D */
2495	#define PORTD_DIR _SFR_MEM8(0x0660)
2496	#define PORTD_DIRSET _SFR_MEM8(0x0661)
2497	#define PORTD_DIRCLR _SFR_MEM8(0x0662)
2498	#define PORTD_DIRTGL _SFR_MEM8(0x0663)
2499	#define PORTD_OUT _SFR_MEM8(0x0664)
2500	#define PORTD_OUTSET _SFR_MEM8(0x0665)
2501	#define PORTD_OUTCLR _SFR_MEM8(0x0666)
2502	#define PORTD_OUTTGL _SFR_MEM8(0x0667)
2503	#define PORTD_IN _SFR_MEM8(0x0668)
2504	#define PORTD_INTCTRL _SFR_MEM8(0x0669)
2505	#define PORTD_INT0MASK _SFR_MEM8(0x066A)
2506	#define PORTD_INT1MASK _SFR_MEM8(0x066B)
2507	#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
2508	#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
2509	#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
2510	#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
2511	#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
2512	#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
2513	#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
2514	#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
2515	#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
2516
2517	/* PORTE - Port E */
2518	#define PORTE_DIR _SFR_MEM8(0x0680)
2519	#define PORTE_DIRSET _SFR_MEM8(0x0681)
2520	#define PORTE_DIRCLR _SFR_MEM8(0x0682)
2521	#define PORTE_DIRTGL _SFR_MEM8(0x0683)
2522	#define PORTE_OUT _SFR_MEM8(0x0684)
2523	#define PORTE_OUTSET _SFR_MEM8(0x0685)
2524	#define PORTE_OUTCLR _SFR_MEM8(0x0686)
2525	#define PORTE_OUTTGL _SFR_MEM8(0x0687)
2526	#define PORTE_IN _SFR_MEM8(0x0688)
2527	#define PORTE_INTCTRL _SFR_MEM8(0x0689)
2528	#define PORTE_INT0MASK _SFR_MEM8(0x068A)
2529	#define PORTE_INT1MASK _SFR_MEM8(0x068B)
2530	#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
2531	#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
2532	#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
2533	#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
2534	#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
2535	#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
2536	#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
2537	#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
2538	#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
2539
2540	/* PORTF - Port F */
2541	#define PORTF_DIR _SFR_MEM8(0x06A0)
2542	#define PORTF_DIRSET _SFR_MEM8(0x06A1)
2543	#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
2544	#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
2545	#define PORTF_OUT _SFR_MEM8(0x06A4)
2546	#define PORTF_OUTSET _SFR_MEM8(0x06A5)
2547	#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
2548	#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
2549	#define PORTF_IN _SFR_MEM8(0x06A8)
2550	#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
2551	#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
2552	#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
2553	#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
2554	#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
2555	#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
2556	#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
2557	#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
2558	#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
2559	#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
2560	#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
2561	#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
2562
2563	/* PORTR - Port R */
2564	#define PORTR_DIR _SFR_MEM8(0x07E0)
2565	#define PORTR_DIRSET _SFR_MEM8(0x07E1)
2566	#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
2567	#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
2568	#define PORTR_OUT _SFR_MEM8(0x07E4)
2569	#define PORTR_OUTSET _SFR_MEM8(0x07E5)
2570	#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
2571	#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
2572	#define PORTR_IN _SFR_MEM8(0x07E8)
2573	#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
2574	#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
2575	#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
2576	#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
2577	#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
2578	#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
2579	#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
2580	#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
2581	#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
2582	#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
2583	#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
2584	#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
2585
2586	/* TCC0 - Timer/Counter C0 */
2587	#define TCC0_CTRLA _SFR_MEM8(0x0800)
2588	#define TCC0_CTRLB _SFR_MEM8(0x0801)
2589	#define TCC0_CTRLC _SFR_MEM8(0x0802)
2590	#define TCC0_CTRLD _SFR_MEM8(0x0803)
2591	#define TCC0_CTRLE _SFR_MEM8(0x0804)
2592	#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
2593	#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
2594	#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
2595	#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
2596	#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
2597	#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
2598	#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
2599	#define TCC0_TEMP _SFR_MEM8(0x080F)
2600	#define TCC0_CNT _SFR_MEM16(0x0820)
2601	#define TCC0_PER _SFR_MEM16(0x0826)
2602	#define TCC0_CCA _SFR_MEM16(0x0828)
2603	#define TCC0_CCB _SFR_MEM16(0x082A)
2604	#define TCC0_CCC _SFR_MEM16(0x082C)
2605	#define TCC0_CCD _SFR_MEM16(0x082E)
2606	#define TCC0_PERBUF _SFR_MEM16(0x0836)
2607	#define TCC0_CCABUF _SFR_MEM16(0x0838)
2608	#define TCC0_CCBBUF _SFR_MEM16(0x083A)
2609	#define TCC0_CCCBUF _SFR_MEM16(0x083C)
2610	#define TCC0_CCDBUF _SFR_MEM16(0x083E)
2611
2612	/* TCC1 - Timer/Counter C1 */
2613	#define TCC1_CTRLA _SFR_MEM8(0x0840)
2614	#define TCC1_CTRLB _SFR_MEM8(0x0841)
2615	#define TCC1_CTRLC _SFR_MEM8(0x0842)
2616	#define TCC1_CTRLD _SFR_MEM8(0x0843)
2617	#define TCC1_CTRLE _SFR_MEM8(0x0844)
2618	#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
2619	#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
2620	#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
2621	#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
2622	#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
2623	#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
2624	#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
2625	#define TCC1_TEMP _SFR_MEM8(0x084F)
2626	#define TCC1_CNT _SFR_MEM16(0x0860)
2627	#define TCC1_PER _SFR_MEM16(0x0866)
2628	#define TCC1_CCA _SFR_MEM16(0x0868)
2629	#define TCC1_CCB _SFR_MEM16(0x086A)
2630	#define TCC1_PERBUF _SFR_MEM16(0x0876)
2631	#define TCC1_CCABUF _SFR_MEM16(0x0878)
2632	#define TCC1_CCBBUF _SFR_MEM16(0x087A)
2633
2634	/* AWEXC - Advanced Waveform Extension C */
2635	#define AWEXC_CTRL _SFR_MEM8(0x0880)
2636	#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
2637	#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
2638	#define AWEXC_STATUS _SFR_MEM8(0x0884)
2639	#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
2640	#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
2641	#define AWEXC_DTLS _SFR_MEM8(0x0888)
2642	#define AWEXC_DTHS _SFR_MEM8(0x0889)
2643	#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
2644	#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
2645	#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
2646
2647	/* HIRESC - High-Resolution Extension C */
2648	#define HIRESC_CTRLA _SFR_MEM8(0x0890)
2649
2650	/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
2651	#define USARTC0_DATA _SFR_MEM8(0x08A0)
2652	#define USARTC0_STATUS _SFR_MEM8(0x08A1)
2653	#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
2654	#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
2655	#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
2656	#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
2657	#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
2658
2659	/* SPIC - Serial Peripheral Interface C */
2660	#define SPIC_CTRL _SFR_MEM8(0x08C0)
2661	#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
2662	#define SPIC_STATUS _SFR_MEM8(0x08C2)
2663	#define SPIC_DATA _SFR_MEM8(0x08C3)
2664
2665	/* IRCOM - IR Communication Module */
2666	#define IRCOM_CTRL _SFR_MEM8(0x08F8)
2667	#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
2668	#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
2669
2670	/* TCD0 - Timer/Counter D0 */
2671	#define TCD0_CTRLA _SFR_MEM8(0x0900)
2672	#define TCD0_CTRLB _SFR_MEM8(0x0901)
2673	#define TCD0_CTRLC _SFR_MEM8(0x0902)
2674	#define TCD0_CTRLD _SFR_MEM8(0x0903)
2675	#define TCD0_CTRLE _SFR_MEM8(0x0904)
2676	#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
2677	#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
2678	#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
2679	#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
2680	#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
2681	#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
2682	#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
2683	#define TCD0_TEMP _SFR_MEM8(0x090F)
2684	#define TCD0_CNT _SFR_MEM16(0x0920)
2685	#define TCD0_PER _SFR_MEM16(0x0926)
2686	#define TCD0_CCA _SFR_MEM16(0x0928)
2687	#define TCD0_CCB _SFR_MEM16(0x092A)
2688	#define TCD0_CCC _SFR_MEM16(0x092C)
2689	#define TCD0_CCD _SFR_MEM16(0x092E)
2690	#define TCD0_PERBUF _SFR_MEM16(0x0936)
2691	#define TCD0_CCABUF _SFR_MEM16(0x0938)
2692	#define TCD0_CCBBUF _SFR_MEM16(0x093A)
2693	#define TCD0_CCCBUF _SFR_MEM16(0x093C)
2694	#define TCD0_CCDBUF _SFR_MEM16(0x093E)
2695
2696	/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
2697	#define USARTD0_DATA _SFR_MEM8(0x09A0)
2698	#define USARTD0_STATUS _SFR_MEM8(0x09A1)
2699	#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
2700	#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
2701	#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
2702	#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
2703	#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
2704
2705	/* SPID - Serial Peripheral Interface D */
2706	#define SPID_CTRL _SFR_MEM8(0x09C0)
2707	#define SPID_INTCTRL _SFR_MEM8(0x09C1)
2708	#define SPID_STATUS _SFR_MEM8(0x09C2)
2709	#define SPID_DATA _SFR_MEM8(0x09C3)
2710
2711	/* TCE0 - Timer/Counter E0 */
2712	#define TCE0_CTRLA _SFR_MEM8(0x0A00)
2713	#define TCE0_CTRLB _SFR_MEM8(0x0A01)
2714	#define TCE0_CTRLC _SFR_MEM8(0x0A02)
2715	#define TCE0_CTRLD _SFR_MEM8(0x0A03)
2716	#define TCE0_CTRLE _SFR_MEM8(0x0A04)
2717	#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
2718	#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
2719	#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
2720	#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
2721	#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
2722	#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
2723	#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
2724	#define TCE0_TEMP _SFR_MEM8(0x0A0F)
2725	#define TCE0_CNT _SFR_MEM16(0x0A20)
2726	#define TCE0_PER _SFR_MEM16(0x0A26)
2727	#define TCE0_CCA _SFR_MEM16(0x0A28)
2728	#define TCE0_CCB _SFR_MEM16(0x0A2A)
2729	#define TCE0_CCC _SFR_MEM16(0x0A2C)
2730	#define TCE0_CCD _SFR_MEM16(0x0A2E)
2731	#define TCE0_PERBUF _SFR_MEM16(0x0A36)
2732	#define TCE0_CCABUF _SFR_MEM16(0x0A38)
2733	#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
2734	#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
2735	#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
2736
2737	/* AWEXE - Advanced Waveform Extension E */
2738	#define AWEXE_CTRL _SFR_MEM8(0x0A80)
2739	#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
2740	#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
2741	#define AWEXE_STATUS _SFR_MEM8(0x0A84)
2742	#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
2743	#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
2744	#define AWEXE_DTLS _SFR_MEM8(0x0A88)
2745	#define AWEXE_DTHS _SFR_MEM8(0x0A89)
2746	#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
2747	#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
2748	#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
2749
2750	/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
2751	#define USARTE0_DATA _SFR_MEM8(0x0AA0)
2752	#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
2753	#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
2754	#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
2755	#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
2756	#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
2757	#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
2758
2759	/* SPIE - Serial Peripheral Interface E */
2760	#define SPIE_CTRL _SFR_MEM8(0x0AC0)
2761	#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
2762	#define SPIE_STATUS _SFR_MEM8(0x0AC2)
2763	#define SPIE_DATA _SFR_MEM8(0x0AC3)
2764
2765	/* TCF0 - Timer/Counter F0 */
2766	#define TCF0_CTRLA _SFR_MEM8(0x0B00)
2767	#define TCF0_CTRLB _SFR_MEM8(0x0B01)
2768	#define TCF0_CTRLC _SFR_MEM8(0x0B02)
2769	#define TCF0_CTRLD _SFR_MEM8(0x0B03)
2770	#define TCF0_CTRLE _SFR_MEM8(0x0B04)
2771	#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
2772	#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
2773	#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
2774	#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
2775	#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
2776	#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
2777	#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
2778	#define TCF0_TEMP _SFR_MEM8(0x0B0F)
2779	#define TCF0_CNT _SFR_MEM16(0x0B20)
2780	#define TCF0_PER _SFR_MEM16(0x0B26)
2781	#define TCF0_CCA _SFR_MEM16(0x0B28)
2782	#define TCF0_CCB _SFR_MEM16(0x0B2A)
2783	#define TCF0_CCC _SFR_MEM16(0x0B2C)
2784	#define TCF0_CCD _SFR_MEM16(0x0B2E)
2785	#define TCF0_PERBUF _SFR_MEM16(0x0B36)
2786	#define TCF0_CCABUF _SFR_MEM16(0x0B38)
2787	#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
2788	#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
2789	#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
2790
2791
2792
2793	/================== Bitfield Definitions ================== /
2794
2795	/* XOCD - On-Chip Debug System */
2796	/* OCD.OCDR1 bit masks and bit positions */
2797	#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
2798	#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
2799
2800
2801	/* CPU - CPU */
2802	/* CPU.CCP bit masks and bit positions */
2803	#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
2804	#define CPU_CCP_gp 0 /* CCP signature group position. */
2805	#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
2806	#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
2807	#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
2808	#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
2809	#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
2810	#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
2811	#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
2812	#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
2813	#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
2814	#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
2815	#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
2816	#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
2817	#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
2818	#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
2819	#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
2820	#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
2821
2822
2823	/* CPU.SREG bit masks and bit positions */
2824	#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
2825	#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
2826
2827	#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
2828	#define CPU_T_bp 6 /* Transfer Bit bit position. */
2829
2830	#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
2831	#define CPU_H_bp 5 /* Half Carry Flag bit position. */
2832
2833	#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
2834	#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
2835
2836	#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
2837	#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
2838
2839	#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
2840	#define CPU_N_bp 2 /* Negative Flag bit position. */
2841
2842	#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
2843	#define CPU_Z_bp 1 /* Zero Flag bit position. */
2844
2845	#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
2846	#define CPU_C_bp 0 /* Carry Flag bit position. */
2847
2848
2849	/* CLK - Clock System */
2850	/* CLK.CTRL bit masks and bit positions */
2851	#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
2852	#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
2853	#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
2854	#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
2855	#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
2856	#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
2857	#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
2858	#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */
2859
2860
2861	/* CLK.PSCTRL bit masks and bit positions */
2862	#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */
2863	#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */
2864	#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */
2865	#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */
2866	#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */
2867	#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */
2868	#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */
2869	#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */
2870	#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */
2871	#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */
2872	#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */
2873	#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */
2874
2875	#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */
2876	#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */
2877	#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */
2878	#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */
2879	#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */
2880	#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */
2881
2882
2883	/* CLK.LOCK bit masks and bit positions */
2884	#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */
2885	#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */
2886
2887
2888	/* CLK.RTCCTRL bit masks and bit positions */
2889	#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */
2890	#define CLK_RTCSRC_gp 1 /* Clock Source group position. */
2891	#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */
2892	#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */
2893	#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */
2894	#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */
2895	#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */
2896	#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */
2897
2898	#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */
2899	#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */
2900
2901
2902	/* PR.PRGEN bit masks and bit positions */
2903	#define PR_AES_bm 0x10 /* AES bit mask. */
2904	#define PR_AES_bp 4 /* AES bit position. */
2905
2906	#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */
2907	#define PR_EBI_bp 3 /* External Bus Interface bit position. */
2908
2909	#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */
2910	#define PR_RTC_bp 2 /* Real-time Counter bit position. */
2911
2912	#define PR_EVSYS_bm 0x02 /* Event System bit mask. */
2913	#define PR_EVSYS_bp 1 /* Event System bit position. */
2914
2915	#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */
2916	#define PR_DMA_bp 0 /* DMA-Controller bit position. */
2917
2918
2919	/* PR.PRPA bit masks and bit positions */
2920	#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */
2921	#define PR_DAC_bp 2 /* Port A DAC bit position. */
2922
2923	#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */
2924	#define PR_ADC_bp 1 /* Port A ADC bit position. */
2925
2926	#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */
2927	#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */
2928
2929
2930	/* PR.PRPB bit masks and bit positions */
2931	/* PR_DAC_bm Predefined. */
2932	/* PR_DAC_bp Predefined. */
2933
2934	/* PR_ADC_bm Predefined. */
2935	/* PR_ADC_bp Predefined. */
2936
2937	/* PR_AC_bm Predefined. */
2938	/* PR_AC_bp Predefined. */
2939
2940
2941	/* PR.PRPC bit masks and bit positions */
2942	#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */
2943	#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */
2944
2945	#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */
2946	#define PR_USART1_bp 5 /* Port C USART1 bit position. */
2947
2948	#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */
2949	#define PR_USART0_bp 4 /* Port C USART0 bit position. */
2950
2951	#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */
2952	#define PR_SPI_bp 3 /* Port C SPI bit position. */
2953
2954	#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */
2955	#define PR_HIRES_bp 2 /* Port C AWEX bit position. */
2956
2957	#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */
2958	#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */
2959
2960	#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */
2961	#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */
2962
2963
2964	/* PR.PRPD bit masks and bit positions */
2965	/* PR_TWI_bm Predefined. */
2966	/* PR_TWI_bp Predefined. */
2967
2968	/* PR_USART1_bm Predefined. */
2969	/* PR_USART1_bp Predefined. */
2970
2971	/* PR_USART0_bm Predefined. */
2972	/* PR_USART0_bp Predefined. */
2973
2974	/* PR_SPI_bm Predefined. */
2975	/* PR_SPI_bp Predefined. */
2976
2977	/* PR_HIRES_bm Predefined. */
2978	/* PR_HIRES_bp Predefined. */
2979
2980	/* PR_TC1_bm Predefined. */
2981	/* PR_TC1_bp Predefined. */
2982
2983	/* PR_TC0_bm Predefined. */
2984	/* PR_TC0_bp Predefined. */
2985
2986
2987	/* PR.PRPE bit masks and bit positions */
2988	/* PR_TWI_bm Predefined. */
2989	/* PR_TWI_bp Predefined. */
2990
2991	/* PR_USART1_bm Predefined. */
2992	/* PR_USART1_bp Predefined. */
2993
2994	/* PR_USART0_bm Predefined. */
2995	/* PR_USART0_bp Predefined. */
2996
2997	/* PR_SPI_bm Predefined. */
2998	/* PR_SPI_bp Predefined. */
2999
3000	/* PR_HIRES_bm Predefined. */
3001	/* PR_HIRES_bp Predefined. */
3002
3003	/* PR_TC1_bm Predefined. */
3004	/* PR_TC1_bp Predefined. */
3005
3006	/* PR_TC0_bm Predefined. */
3007	/* PR_TC0_bp Predefined. */
3008
3009
3010	/* PR.PRPF bit masks and bit positions */
3011	/* PR_TWI_bm Predefined. */
3012	/* PR_TWI_bp Predefined. */
3013
3014	/* PR_USART1_bm Predefined. */
3015	/* PR_USART1_bp Predefined. */
3016
3017	/* PR_USART0_bm Predefined. */
3018	/* PR_USART0_bp Predefined. */
3019
3020	/* PR_SPI_bm Predefined. */
3021	/* PR_SPI_bp Predefined. */
3022
3023	/* PR_HIRES_bm Predefined. */
3024	/* PR_HIRES_bp Predefined. */
3025
3026	/* PR_TC1_bm Predefined. */
3027	/* PR_TC1_bp Predefined. */
3028
3029	/* PR_TC0_bm Predefined. */
3030	/* PR_TC0_bp Predefined. */
3031
3032
3033	/* SLEEP - Sleep Controller */
3034	/* SLEEP.CTRL bit masks and bit positions */
3035	#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */
3036	#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */
3037	#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */
3038	#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */
3039	#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */
3040	#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */
3041	#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */
3042	#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */
3043
3044	#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */
3045	#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */
3046
3047
3048	/* OSC - Oscillator */
3049	/* OSC.CTRL bit masks and bit positions */
3050	#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */
3051	#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */
3052
3053	#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */
3054	#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */
3055
3056	#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */
3057	#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */
3058
3059	#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */
3060	#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */
3061
3062	#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */
3063	#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */
3064
3065
3066	/* OSC.STATUS bit masks and bit positions */
3067	#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */
3068	#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */
3069
3070	#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */
3071	#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */
3072
3073	#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */
3074	#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */
3075
3076	#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */
3077	#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */
3078
3079	#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */
3080	#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */
3081
3082
3083	/* OSC.XOSCCTRL bit masks and bit positions */
3084	#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */
3085	#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */
3086	#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */
3087	#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */
3088	#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */
3089	#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */
3090
3091	#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */
3092	#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */
3093
3094	#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */
3095	#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */
3096	#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */
3097	#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */
3098	#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */
3099	#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */
3100	#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */
3101	#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */
3102	#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */
3103	#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */
3104
3105
3106	/* OSC.XOSCFAIL bit masks and bit positions */
3107	#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */
3108	#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */
3109
3110	#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */
3111	#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */
3112
3113
3114	/* OSC.PLLCTRL bit masks and bit positions */
3115	#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */
3116	#define OSC_PLLSRC_gp 6 /* Clock Source group position. */
3117	#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */
3118	#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */
3119	#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */
3120	#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */
3121
3122	#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */
3123	#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */
3124	#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */
3125	#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */
3126	#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */
3127	#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */
3128	#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */
3129	#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */
3130	#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */
3131	#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */
3132	#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */
3133	#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */
3134
3135
3136	/* OSC.DFLLCTRL bit masks and bit positions */
3137	#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */
3138	#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */
3139
3140	#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */
3141	#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */
3142
3143
3144	/* DFLL - DFLL */
3145	/* DFLL.CTRL bit masks and bit positions */
3146	#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */
3147	#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */
3148
3149
3150	/* DFLL.CALA bit masks and bit positions */
3151	#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */
3152	#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */
3153	#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */
3154	#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */
3155	#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */
3156	#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */
3157	#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */
3158	#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */
3159	#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */
3160	#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */
3161	#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */
3162	#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */
3163	#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */
3164	#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */
3165	#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */
3166	#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */
3167
3168
3169	/* DFLL.CALB bit masks and bit positions */
3170	#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */
3171	#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */
3172	#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */
3173	#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */
3174	#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */
3175	#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */
3176	#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */
3177	#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */
3178	#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */
3179	#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */
3180	#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */
3181	#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */
3182	#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */
3183	#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */
3184
3185
3186	/* RST - Reset */
3187	/* RST.STATUS bit masks and bit positions */
3188	#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */
3189	#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */
3190
3191	#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */
3192	#define RST_SRF_bp 5 /* Software Reset Flag bit position. */
3193
3194	#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */
3195	#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */
3196
3197	#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */
3198	#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */
3199
3200	#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */
3201	#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */
3202
3203	#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */
3204	#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */
3205
3206	#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */
3207	#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */
3208
3209
3210	/* RST.CTRL bit masks and bit positions */
3211	#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */
3212	#define RST_SWRST_bp 0 /* Software Reset bit position. */
3213
3214
3215	/* WDT - Watch-Dog Timer */
3216	/* WDT.CTRL bit masks and bit positions */
3217	#define WDT_PER_gm 0x3C /* Period group mask. */
3218	#define WDT_PER_gp 2 /* Period group position. */
3219	#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */
3220	#define WDT_PER0_bp 2 /* Period bit 0 position. */
3221	#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */
3222	#define WDT_PER1_bp 3 /* Period bit 1 position. */
3223	#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */
3224	#define WDT_PER2_bp 4 /* Period bit 2 position. */
3225	#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */
3226	#define WDT_PER3_bp 5 /* Period bit 3 position. */
3227
3228	#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */
3229	#define WDT_ENABLE_bp 1 /* Enable bit position. */
3230
3231	#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */
3232	#define WDT_CEN_bp 0 /* Change Enable bit position. */
3233
3234
3235	/* WDT.WINCTRL bit masks and bit positions */
3236	#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */
3237	#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */
3238	#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */
3239	#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */
3240	#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */
3241	#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */
3242	#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */
3243	#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */
3244	#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */
3245	#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */
3246
3247	#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */
3248	#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */
3249
3250	#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */
3251	#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */
3252
3253
3254	/* WDT.STATUS bit masks and bit positions */
3255	#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */
3256	#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */
3257
3258
3259	/* MCU - MCU Control */
3260	/* MCU.MCUCR bit masks and bit positions */
3261	#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */
3262	#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */
3263
3264
3265	/* MCU.EVSYSLOCK bit masks and bit positions */
3266	#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */
3267	#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */
3268
3269	#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */
3270	#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */
3271
3272
3273	/* MCU.AWEXLOCK bit masks and bit positions */
3274	#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */
3275	#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */
3276
3277	#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */
3278	#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */
3279
3280
3281	/* PMIC - Programmable Multi-level Interrupt Controller */
3282	/* PMIC.STATUS bit masks and bit positions */
3283	#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */
3284	#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */
3285
3286	#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */
3287	#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */
3288
3289	#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */
3290	#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */
3291
3292	#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */
3293	#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */
3294
3295
3296	/* PMIC.CTRL bit masks and bit positions */
3297	#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */
3298	#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */
3299
3300	#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */
3301	#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */
3302
3303	#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */
3304	#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */
3305
3306	#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */
3307	#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */
3308
3309	#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */
3310	#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */
3311
3312
3313	/* EVSYS - Event System */
3314	/* EVSYS.CH0MUX bit masks and bit positions */
3315	#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */
3316	#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */
3317	#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */
3318	#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */
3319	#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */
3320	#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */
3321	#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */
3322	#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */
3323	#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */
3324	#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */
3325	#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */
3326	#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */
3327	#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */
3328	#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */
3329	#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */
3330	#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */
3331	#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */
3332	#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */
3333
3334
3335	/* EVSYS.CH1MUX bit masks and bit positions */
3336	/* EVSYS_CHMUX_gm Predefined. */
3337	/* EVSYS_CHMUX_gp Predefined. */
3338	/* EVSYS_CHMUX0_bm Predefined. */
3339	/* EVSYS_CHMUX0_bp Predefined. */
3340	/* EVSYS_CHMUX1_bm Predefined. */
3341	/* EVSYS_CHMUX1_bp Predefined. */
3342	/* EVSYS_CHMUX2_bm Predefined. */
3343	/* EVSYS_CHMUX2_bp Predefined. */
3344	/* EVSYS_CHMUX3_bm Predefined. */
3345	/* EVSYS_CHMUX3_bp Predefined. */
3346	/* EVSYS_CHMUX4_bm Predefined. */
3347	/* EVSYS_CHMUX4_bp Predefined. */
3348	/* EVSYS_CHMUX5_bm Predefined. */
3349	/* EVSYS_CHMUX5_bp Predefined. */
3350	/* EVSYS_CHMUX6_bm Predefined. */
3351	/* EVSYS_CHMUX6_bp Predefined. */
3352	/* EVSYS_CHMUX7_bm Predefined. */
3353	/* EVSYS_CHMUX7_bp Predefined. */
3354
3355
3356	/* EVSYS.CH2MUX bit masks and bit positions */
3357	/* EVSYS_CHMUX_gm Predefined. */
3358	/* EVSYS_CHMUX_gp Predefined. */
3359	/* EVSYS_CHMUX0_bm Predefined. */
3360	/* EVSYS_CHMUX0_bp Predefined. */
3361	/* EVSYS_CHMUX1_bm Predefined. */
3362	/* EVSYS_CHMUX1_bp Predefined. */
3363	/* EVSYS_CHMUX2_bm Predefined. */
3364	/* EVSYS_CHMUX2_bp Predefined. */
3365	/* EVSYS_CHMUX3_bm Predefined. */
3366	/* EVSYS_CHMUX3_bp Predefined. */
3367	/* EVSYS_CHMUX4_bm Predefined. */
3368	/* EVSYS_CHMUX4_bp Predefined. */
3369	/* EVSYS_CHMUX5_bm Predefined. */
3370	/* EVSYS_CHMUX5_bp Predefined. */
3371	/* EVSYS_CHMUX6_bm Predefined. */
3372	/* EVSYS_CHMUX6_bp Predefined. */
3373	/* EVSYS_CHMUX7_bm Predefined. */
3374	/* EVSYS_CHMUX7_bp Predefined. */
3375
3376
3377	/* EVSYS.CH3MUX bit masks and bit positions */
3378	/* EVSYS_CHMUX_gm Predefined. */
3379	/* EVSYS_CHMUX_gp Predefined. */
3380	/* EVSYS_CHMUX0_bm Predefined. */
3381	/* EVSYS_CHMUX0_bp Predefined. */
3382	/* EVSYS_CHMUX1_bm Predefined. */
3383	/* EVSYS_CHMUX1_bp Predefined. */
3384	/* EVSYS_CHMUX2_bm Predefined. */
3385	/* EVSYS_CHMUX2_bp Predefined. */
3386	/* EVSYS_CHMUX3_bm Predefined. */
3387	/* EVSYS_CHMUX3_bp Predefined. */
3388	/* EVSYS_CHMUX4_bm Predefined. */
3389	/* EVSYS_CHMUX4_bp Predefined. */
3390	/* EVSYS_CHMUX5_bm Predefined. */
3391	/* EVSYS_CHMUX5_bp Predefined. */
3392	/* EVSYS_CHMUX6_bm Predefined. */
3393	/* EVSYS_CHMUX6_bp Predefined. */
3394	/* EVSYS_CHMUX7_bm Predefined. */
3395	/* EVSYS_CHMUX7_bp Predefined. */
3396
3397
3398	/* EVSYS.CH0CTRL bit masks and bit positions */
3399	#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */
3400	#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */
3401	#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
3402	#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */
3403	#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
3404	#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */
3405
3406	#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */
3407	#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */
3408
3409	#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */
3410	#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */
3411
3412	#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */
3413	#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */
3414	#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */
3415	#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */
3416	#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */
3417	#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */
3418	#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */
3419	#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */
3420
3421
3422	/* EVSYS.CH1CTRL bit masks and bit positions */
3423	/* EVSYS_DIGFILT_gm Predefined. */
3424	/* EVSYS_DIGFILT_gp Predefined. */
3425	/* EVSYS_DIGFILT0_bm Predefined. */
3426	/* EVSYS_DIGFILT0_bp Predefined. */
3427	/* EVSYS_DIGFILT1_bm Predefined. */
3428	/* EVSYS_DIGFILT1_bp Predefined. */
3429	/* EVSYS_DIGFILT2_bm Predefined. */
3430	/* EVSYS_DIGFILT2_bp Predefined. */
3431
3432
3433	/* EVSYS.CH2CTRL bit masks and bit positions */
3434	/* EVSYS_QDIRM_gm Predefined. */
3435	/* EVSYS_QDIRM_gp Predefined. */
3436	/* EVSYS_QDIRM0_bm Predefined. */
3437	/* EVSYS_QDIRM0_bp Predefined. */
3438	/* EVSYS_QDIRM1_bm Predefined. */
3439	/* EVSYS_QDIRM1_bp Predefined. */
3440
3441	/* EVSYS_QDIEN_bm Predefined. */
3442	/* EVSYS_QDIEN_bp Predefined. */
3443
3444	/* EVSYS_QDEN_bm Predefined. */
3445	/* EVSYS_QDEN_bp Predefined. */
3446
3447	/* EVSYS_DIGFILT_gm Predefined. */
3448	/* EVSYS_DIGFILT_gp Predefined. */
3449	/* EVSYS_DIGFILT0_bm Predefined. */
3450	/* EVSYS_DIGFILT0_bp Predefined. */
3451	/* EVSYS_DIGFILT1_bm Predefined. */
3452	/* EVSYS_DIGFILT1_bp Predefined. */
3453	/* EVSYS_DIGFILT2_bm Predefined. */
3454	/* EVSYS_DIGFILT2_bp Predefined. */
3455
3456
3457	/* EVSYS.CH3CTRL bit masks and bit positions */
3458	/* EVSYS_DIGFILT_gm Predefined. */
3459	/* EVSYS_DIGFILT_gp Predefined. */
3460	/* EVSYS_DIGFILT0_bm Predefined. */
3461	/* EVSYS_DIGFILT0_bp Predefined. */
3462	/* EVSYS_DIGFILT1_bm Predefined. */
3463	/* EVSYS_DIGFILT1_bp Predefined. */
3464	/* EVSYS_DIGFILT2_bm Predefined. */
3465	/* EVSYS_DIGFILT2_bp Predefined. */
3466
3467
3468	/* NVM - Non Volatile Memory Controller */
3469	/* NVM.CMD bit masks and bit positions */
3470	#define NVM_CMD_gm 0xFF /* Command group mask. */
3471	#define NVM_CMD_gp 0 /* Command group position. */
3472	#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */
3473	#define NVM_CMD0_bp 0 /* Command bit 0 position. */
3474	#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */
3475	#define NVM_CMD1_bp 1 /* Command bit 1 position. */
3476	#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */
3477	#define NVM_CMD2_bp 2 /* Command bit 2 position. */
3478	#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */
3479	#define NVM_CMD3_bp 3 /* Command bit 3 position. */
3480	#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */
3481	#define NVM_CMD4_bp 4 /* Command bit 4 position. */
3482	#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */
3483	#define NVM_CMD5_bp 5 /* Command bit 5 position. */
3484	#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */
3485	#define NVM_CMD6_bp 6 /* Command bit 6 position. */
3486	#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */
3487	#define NVM_CMD7_bp 7 /* Command bit 7 position. */
3488
3489
3490	/* NVM.CTRLA bit masks and bit positions */
3491	#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */
3492	#define NVM_CMDEX_bp 0 /* Command Execute bit position. */
3493
3494
3495	/* NVM.CTRLB bit masks and bit positions */
3496	#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */
3497	#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */
3498
3499	#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */
3500	#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */
3501
3502	#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */
3503	#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */
3504
3505	#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */
3506	#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */
3507
3508
3509	/* NVM.INTCTRL bit masks and bit positions */
3510	#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */
3511	#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */
3512	#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */
3513	#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */
3514	#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */
3515	#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */
3516
3517	#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */
3518	#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */
3519	#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */
3520	#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */
3521	#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */
3522	#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */
3523
3524
3525	/* NVM.STATUS bit masks and bit positions */
3526	#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */
3527	#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */
3528
3529	#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */
3530	#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */
3531
3532	#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */
3533	#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */
3534
3535	#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */
3536	#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */
3537
3538
3539	/* NVM.LOCKBITS bit masks and bit positions */
3540	#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3541	#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3542	#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3543	#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3544	#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3545	#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3546
3547	#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3548	#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3549	#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3550	#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3551	#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3552	#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3553
3554	#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3555	#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3556	#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3557	#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3558	#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3559	#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3560
3561	#define NVM_LB_gm 0x03 /* Lock Bits group mask. */
3562	#define NVM_LB_gp 0 /* Lock Bits group position. */
3563	#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3564	#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */
3565	#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3566	#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */
3567
3568
3569	/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */
3570	#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */
3571	#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */
3572	#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */
3573	#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */
3574	#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */
3575	#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */
3576
3577	#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */
3578	#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */
3579	#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */
3580	#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */
3581	#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */
3582	#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */
3583
3584	#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */
3585	#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */
3586	#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */
3587	#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */
3588	#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */
3589	#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */
3590
3591	#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */
3592	#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */
3593	#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */
3594	#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */
3595	#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */
3596	#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */
3597
3598
3599	/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */
3600	#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */
3601	#define NVM_FUSES_USERID_gp 0 /* User ID group position. */
3602	#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */
3603	#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */
3604	#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */
3605	#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */
3606	#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */
3607	#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */
3608	#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */
3609	#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */
3610	#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */
3611	#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */
3612	#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */
3613	#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */
3614	#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */
3615	#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */
3616	#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */
3617	#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */
3618
3619
3620	/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */
3621	#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */
3622	#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */
3623	#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */
3624	#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */
3625	#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */
3626	#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */
3627	#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */
3628	#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */
3629	#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */
3630	#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */
3631
3632	#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */
3633	#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */
3634	#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */
3635	#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */
3636	#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */
3637	#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */
3638	#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */
3639	#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */
3640	#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */
3641	#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */
3642
3643
3644	/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */
3645	#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */
3646	#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */
3647
3648	#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */
3649	#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */
3650
3651	#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */
3652	#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */
3653	#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */
3654	#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */
3655	#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */
3656	#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */
3657
3658
3659	/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */
3660	#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */
3661	#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */
3662	#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */
3663	#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */
3664	#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */
3665	#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */
3666
3667	#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */
3668	#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */
3669
3670
3671	/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */
3672	#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */
3673	#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */
3674	#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */
3675	#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */
3676	#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */
3677	#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */
3678
3679	#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */
3680	#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */
3681
3682	#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */
3683	#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */
3684	#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */
3685	#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */
3686	#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */
3687	#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */
3688	#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */
3689	#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */
3690
3691
3692	/* AC - Analog Comparator */
3693	/* AC.AC0CTRL bit masks and bit positions */
3694	#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */
3695	#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */
3696	#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */
3697	#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */
3698	#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */
3699	#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */
3700
3701	#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */
3702	#define AC_INTLVL_gp 4 /* Interrupt Level group position. */
3703	#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */
3704	#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */
3705	#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */
3706	#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */
3707
3708	#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */
3709	#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */
3710
3711	#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */
3712	#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */
3713	#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */
3714	#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */
3715	#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */
3716	#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */
3717
3718	#define AC_ENABLE_bm 0x01 /* Enable bit mask. */
3719	#define AC_ENABLE_bp 0 /* Enable bit position. */
3720
3721
3722	/* AC.AC1CTRL bit masks and bit positions */
3723	/* AC_INTMODE_gm Predefined. */
3724	/* AC_INTMODE_gp Predefined. */
3725	/* AC_INTMODE0_bm Predefined. */
3726	/* AC_INTMODE0_bp Predefined. */
3727	/* AC_INTMODE1_bm Predefined. */
3728	/* AC_INTMODE1_bp Predefined. */
3729
3730	/* AC_INTLVL_gm Predefined. */
3731	/* AC_INTLVL_gp Predefined. */
3732	/* AC_INTLVL0_bm Predefined. */
3733	/* AC_INTLVL0_bp Predefined. */
3734	/* AC_INTLVL1_bm Predefined. */
3735	/* AC_INTLVL1_bp Predefined. */
3736
3737	/* AC_HSMODE_bm Predefined. */
3738	/* AC_HSMODE_bp Predefined. */
3739
3740	/* AC_HYSMODE_gm Predefined. */
3741	/* AC_HYSMODE_gp Predefined. */
3742	/* AC_HYSMODE0_bm Predefined. */
3743	/* AC_HYSMODE0_bp Predefined. */
3744	/* AC_HYSMODE1_bm Predefined. */
3745	/* AC_HYSMODE1_bp Predefined. */
3746
3747	/* AC_ENABLE_bm Predefined. */
3748	/* AC_ENABLE_bp Predefined. */
3749
3750
3751	/* AC.AC0MUXCTRL bit masks and bit positions */
3752	#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */
3753	#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */
3754	#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */
3755	#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */
3756	#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */
3757	#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */
3758	#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */
3759	#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */
3760
3761	#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */
3762	#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */
3763	#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */
3764	#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */
3765	#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */
3766	#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */
3767	#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */
3768	#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */
3769
3770
3771	/* AC.AC1MUXCTRL bit masks and bit positions */
3772	/* AC_MUXPOS_gm Predefined. */
3773	/* AC_MUXPOS_gp Predefined. */
3774	/* AC_MUXPOS0_bm Predefined. */
3775	/* AC_MUXPOS0_bp Predefined. */
3776	/* AC_MUXPOS1_bm Predefined. */
3777	/* AC_MUXPOS1_bp Predefined. */
3778	/* AC_MUXPOS2_bm Predefined. */
3779	/* AC_MUXPOS2_bp Predefined. */
3780
3781	/* AC_MUXNEG_gm Predefined. */
3782	/* AC_MUXNEG_gp Predefined. */
3783	/* AC_MUXNEG0_bm Predefined. */
3784	/* AC_MUXNEG0_bp Predefined. */
3785	/* AC_MUXNEG1_bm Predefined. */
3786	/* AC_MUXNEG1_bp Predefined. */
3787	/* AC_MUXNEG2_bm Predefined. */
3788	/* AC_MUXNEG2_bp Predefined. */
3789
3790
3791	/* AC.CTRLA bit masks and bit positions */
3792	#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */
3793	#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */
3794
3795
3796	/* AC.CTRLB bit masks and bit positions */
3797	#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */
3798	#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */
3799	#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */
3800	#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */
3801	#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */
3802	#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */
3803	#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */
3804	#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */
3805	#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */
3806	#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */
3807	#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */
3808	#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */
3809	#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */
3810	#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */
3811
3812
3813	/* AC.WINCTRL bit masks and bit positions */
3814	#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */
3815	#define AC_WEN_bp 4 /* Window Mode Enable bit position. */
3816
3817	#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */
3818	#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */
3819	#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */
3820	#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */
3821	#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */
3822	#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */
3823
3824	#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */
3825	#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */
3826	#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */
3827	#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */
3828	#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */
3829	#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */
3830
3831
3832	/* AC.STATUS bit masks and bit positions */
3833	#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */
3834	#define AC_WSTATE_gp 6 /* Window Mode State group position. */
3835	#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */
3836	#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */
3837	#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */
3838	#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */
3839
3840	#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */
3841	#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */
3842
3843	#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */
3844	#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */
3845
3846	#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */
3847	#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */
3848
3849	#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */
3850	#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */
3851
3852	#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */
3853	#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */
3854
3855
3856	/* ADC - Analog/Digital Converter */
3857	/* ADC_CH.CTRL bit masks and bit positions */
3858	#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */
3859	#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */
3860
3861	#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */
3862	#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */
3863	#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */
3864	#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */
3865	#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */
3866	#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */
3867	#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */
3868	#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */
3869
3870	#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */
3871	#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */
3872	#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */
3873	#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */
3874	#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */
3875	#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */
3876
3877
3878	/* ADC_CH.MUXCTRL bit masks and bit positions */
3879	#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */
3880	#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */
3881	#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */
3882	#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */
3883	#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */
3884	#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */
3885	#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */
3886	#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */
3887	#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */
3888	#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */
3889
3890	#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */
3891	#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */
3892	#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */
3893	#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */
3894	#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */
3895	#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */
3896	#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */
3897	#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */
3898	#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */
3899	#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */
3900
3901	#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */
3902	#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */
3903	#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */
3904	#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */
3905	#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */
3906	#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */
3907
3908
3909	/* ADC_CH.INTCTRL bit masks and bit positions */
3910	#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */
3911	#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */
3912	#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */
3913	#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */
3914	#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */
3915	#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */
3916
3917	#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */
3918	#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */
3919	#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */
3920	#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */
3921	#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */
3922	#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */
3923
3924
3925	/* ADC_CH.INTFLAGS bit masks and bit positions */
3926	#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */
3927	#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */
3928
3929
3930	/* ADC.CTRLA bit masks and bit positions */
3931	#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */
3932	#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */
3933
3934	#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */
3935	#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */
3936
3937
3938	/* ADC.CTRLB bit masks and bit positions */
3939	#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */
3940	#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */
3941
3942	#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */
3943	#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */
3944
3945	#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */
3946	#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */
3947	#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */
3948	#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */
3949	#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */
3950	#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */
3951
3952
3953	/* ADC.REFCTRL bit masks and bit positions */
3954	#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */
3955	#define ADC_REFSEL_gp 4 /* Reference Selection group position. */
3956	#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */
3957	#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */
3958	#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */
3959	#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */
3960
3961	#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */
3962	#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */
3963
3964	#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */
3965	#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */
3966
3967
3968	/* ADC.EVCTRL bit masks and bit positions */
3969	#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */
3970	#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */
3971	#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */
3972	#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */
3973	#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */
3974	#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */
3975
3976	#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */
3977	#define ADC_EVSEL_gp 3 /* Event Input Select group position. */
3978	#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */
3979	#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */
3980	#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */
3981	#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */
3982	#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */
3983	#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */
3984
3985	#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */
3986	#define ADC_EVACT_gp 0 /* Event Action Select group position. */
3987	#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */
3988	#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */
3989	#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */
3990	#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */
3991	#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */
3992	#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */
3993
3994
3995	/* ADC.PRESCALER bit masks and bit positions */
3996	#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */
3997	#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */
3998	#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */
3999	#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */
4000	#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */
4001	#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */
4002	#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */
4003	#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */
4004
4005
4006	/* ADC.CALCTRL bit masks and bit positions */
4007	#define ADC_CAL_bm 0x01 /* ADC Calibration Start bit mask. */
4008	#define ADC_CAL_bp 0 /* ADC Calibration Start bit position. */
4009
4010
4011	/* ADC.INTFLAGS bit masks and bit positions */
4012	#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */
4013	#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */
4014
4015
4016	/* RTC - Real-Time Clounter */
4017	/* RTC.CTRL bit masks and bit positions */
4018	#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */
4019	#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */
4020	#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */
4021	#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */
4022	#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */
4023	#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */
4024	#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */
4025	#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */
4026
4027
4028	/* RTC.STATUS bit masks and bit positions */
4029	#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */
4030	#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */
4031
4032
4033	/* RTC.INTCTRL bit masks and bit positions */
4034	#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */
4035	#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */
4036	#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */
4037	#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */
4038	#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */
4039	#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */
4040
4041	#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */
4042	#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */
4043	#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */
4044	#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */
4045	#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */
4046	#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */
4047
4048
4049	/* RTC.INTFLAGS bit masks and bit positions */
4050	#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */
4051	#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */
4052
4053	#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4054	#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4055
4056
4057	/* EBI - External Bus Interface */
4058	/* EBI_CS.CTRLA bit masks and bit positions */
4059	#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */
4060	#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */
4061	#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */
4062	#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */
4063	#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */
4064	#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */
4065	#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */
4066	#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */
4067	#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */
4068	#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */
4069	#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */
4070	#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */
4071
4072	#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */
4073	#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */
4074	#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */
4075	#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */
4076	#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */
4077	#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */
4078
4079
4080	/* EBI_CS.CTRLB bit masks and bit positions */
4081	#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */
4082	#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */
4083	#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */
4084	#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */
4085	#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */
4086	#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */
4087	#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */
4088	#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */
4089
4090	#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */
4091	#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */
4092
4093	#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */
4094	#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */
4095
4096	#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */
4097	#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */
4098	#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */
4099	#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */
4100	#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */
4101	#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */
4102
4103
4104	/* EBI.CTRL bit masks and bit positions */
4105	#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */
4106	#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */
4107	#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */
4108	#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */
4109	#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */
4110	#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */
4111
4112	#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */
4113	#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */
4114	#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */
4115	#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */
4116	#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */
4117	#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */
4118
4119	#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */
4120	#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */
4121	#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */
4122	#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */
4123	#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */
4124	#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */
4125
4126	#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */
4127	#define EBI_IFMODE_gp 0 /* Interface Mode group position. */
4128	#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */
4129	#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */
4130	#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */
4131	#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */
4132
4133
4134	/* EBI.SDRAMCTRLA bit masks and bit positions */
4135	#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */
4136	#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */
4137
4138	#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */
4139	#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */
4140
4141	#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */
4142	#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */
4143	#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */
4144	#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */
4145	#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */
4146	#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */
4147
4148
4149	/* EBI.SDRAMCTRLB bit masks and bit positions */
4150	#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */
4151	#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */
4152	#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */
4153	#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */
4154	#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */
4155	#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */
4156
4157	#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */
4158	#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */
4159	#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */
4160	#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */
4161	#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */
4162	#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */
4163	#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */
4164	#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */
4165
4166	#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */
4167	#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */
4168	#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */
4169	#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */
4170	#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */
4171	#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */
4172	#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */
4173	#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */
4174
4175
4176	/* EBI.SDRAMCTRLC bit masks and bit positions */
4177	#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */
4178	#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */
4179	#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */
4180	#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */
4181	#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */
4182	#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */
4183
4184	#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
4185	#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
4186	#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
4187	#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
4188	#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
4189	#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
4190	#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
4191	#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
4192
4193	#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */
4194	#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */
4195	#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */
4196	#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */
4197	#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */
4198	#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */
4199	#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */
4200	#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */
4201
4202
4203	/* TWI - Two-Wire Interface */
4204	/* TWI_MASTER.CTRLA bit masks and bit positions */
4205	#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4206	#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */
4207	#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4208	#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4209	#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4210	#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4211
4212	#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */
4213	#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */
4214
4215	#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */
4216	#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */
4217
4218	#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */
4219	#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */
4220
4221
4222	/* TWI_MASTER.CTRLB bit masks and bit positions */
4223	#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */
4224	#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */
4225	#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */
4226	#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */
4227	#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */
4228	#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */
4229
4230	#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */
4231	#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */
4232
4233	#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4234	#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */
4235
4236
4237	/* TWI_MASTER.CTRLC bit masks and bit positions */
4238	#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4239	#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */
4240
4241	#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */
4242	#define TWI_MASTER_CMD_gp 0 /* Command group position. */
4243	#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */
4244	#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */
4245	#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */
4246	#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */
4247
4248
4249	/* TWI_MASTER.STATUS bit masks and bit positions */
4250	#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */
4251	#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */
4252
4253	#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */
4254	#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */
4255
4256	#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4257	#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */
4258
4259	#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4260	#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */
4261
4262	#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */
4263	#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */
4264
4265	#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */
4266	#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */
4267
4268	#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */
4269	#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */
4270	#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */
4271	#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */
4272	#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */
4273	#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */
4274
4275
4276	/* TWI_SLAVE.CTRLA bit masks and bit positions */
4277	#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */
4278	#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */
4279	#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */
4280	#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */
4281	#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */
4282	#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */
4283
4284	#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */
4285	#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */
4286
4287	#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */
4288	#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */
4289
4290	#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */
4291	#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */
4292
4293	#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */
4294	#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */
4295
4296	#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */
4297	#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */
4298
4299	#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */
4300	#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */
4301
4302
4303	/* TWI_SLAVE.CTRLB bit masks and bit positions */
4304	#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */
4305	#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */
4306
4307	#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */
4308	#define TWI_SLAVE_CMD_gp 0 /* Command group position. */
4309	#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */
4310	#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */
4311	#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */
4312	#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */
4313
4314
4315	/* TWI_SLAVE.STATUS bit masks and bit positions */
4316	#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */
4317	#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */
4318
4319	#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */
4320	#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */
4321
4322	#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */
4323	#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */
4324
4325	#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */
4326	#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */
4327
4328	#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */
4329	#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */
4330
4331	#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */
4332	#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */
4333
4334	#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */
4335	#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */
4336
4337	#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */
4338	#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */
4339
4340
4341	/* TWI_SLAVE.ADDRMASK bit masks and bit positions */
4342	#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */
4343	#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */
4344	#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */
4345	#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */
4346	#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */
4347	#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */
4348	#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */
4349	#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */
4350	#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */
4351	#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */
4352	#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */
4353	#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */
4354	#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */
4355	#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */
4356	#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */
4357	#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */
4358
4359	#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */
4360	#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */
4361
4362
4363	/* TWI.CTRL bit masks and bit positions */
4364	#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */
4365	#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */
4366
4367	#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */
4368	#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */
4369
4370
4371	/* PORT - Port Configuration */
4372	/* PORTCFG.VPCTRLA bit masks and bit positions */
4373	#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */
4374	#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */
4375	#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */
4376	#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */
4377	#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */
4378	#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */
4379	#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */
4380	#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */
4381	#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */
4382	#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */
4383
4384	#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */
4385	#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */
4386	#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */
4387	#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */
4388	#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */
4389	#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */
4390	#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */
4391	#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */
4392	#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */
4393	#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */
4394
4395
4396	/* PORTCFG.VPCTRLB bit masks and bit positions */
4397	#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */
4398	#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */
4399	#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */
4400	#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */
4401	#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */
4402	#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */
4403	#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */
4404	#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */
4405	#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */
4406	#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */
4407
4408	#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */
4409	#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */
4410	#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */
4411	#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */
4412	#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */
4413	#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */
4414	#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */
4415	#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */
4416	#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */
4417	#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */
4418
4419
4420	/* PORTCFG.CLKEVOUT bit masks and bit positions */
4421	#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */
4422	#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */
4423	#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */
4424	#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */
4425	#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */
4426	#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */
4427
4428	#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */
4429	#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */
4430	#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */
4431	#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */
4432	#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */
4433	#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */
4434
4435
4436	/* VPORT.INTFLAGS bit masks and bit positions */
4437	#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4438	#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4439
4440	#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4441	#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4442
4443
4444	/* PORT.INTCTRL bit masks and bit positions */
4445	#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */
4446	#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */
4447	#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */
4448	#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */
4449	#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */
4450	#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */
4451
4452	#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */
4453	#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */
4454	#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */
4455	#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */
4456	#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */
4457	#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */
4458
4459
4460	/* PORT.INTFLAGS bit masks and bit positions */
4461	#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
4462	#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
4463
4464	#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
4465	#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
4466
4467
4468	/* PORT.PIN0CTRL bit masks and bit positions */
4469	#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */
4470	#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */
4471
4472	#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */
4473	#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */
4474
4475	#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */
4476	#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */
4477	#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */
4478	#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */
4479	#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */
4480	#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */
4481	#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */
4482	#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */
4483
4484	#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */
4485	#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */
4486	#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */
4487	#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */
4488	#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */
4489	#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */
4490	#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */
4491	#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */
4492
4493
4494	/* PORT.PIN1CTRL bit masks and bit positions */
4495	/* PORT_SRLEN_bm Predefined. */
4496	/* PORT_SRLEN_bp Predefined. */
4497
4498	/* PORT_INVEN_bm Predefined. */
4499	/* PORT_INVEN_bp Predefined. */
4500
4501	/* PORT_OPC_gm Predefined. */
4502	/* PORT_OPC_gp Predefined. */
4503	/* PORT_OPC0_bm Predefined. */
4504	/* PORT_OPC0_bp Predefined. */
4505	/* PORT_OPC1_bm Predefined. */
4506	/* PORT_OPC1_bp Predefined. */
4507	/* PORT_OPC2_bm Predefined. */
4508	/* PORT_OPC2_bp Predefined. */
4509
4510	/* PORT_ISC_gm Predefined. */
4511	/* PORT_ISC_gp Predefined. */
4512	/* PORT_ISC0_bm Predefined. */
4513	/* PORT_ISC0_bp Predefined. */
4514	/* PORT_ISC1_bm Predefined. */
4515	/* PORT_ISC1_bp Predefined. */
4516	/* PORT_ISC2_bm Predefined. */
4517	/* PORT_ISC2_bp Predefined. */
4518
4519
4520	/* PORT.PIN2CTRL bit masks and bit positions */
4521	/* PORT_SRLEN_bm Predefined. */
4522	/* PORT_SRLEN_bp Predefined. */
4523
4524	/* PORT_INVEN_bm Predefined. */
4525	/* PORT_INVEN_bp Predefined. */
4526
4527	/* PORT_OPC_gm Predefined. */
4528	/* PORT_OPC_gp Predefined. */
4529	/* PORT_OPC0_bm Predefined. */
4530	/* PORT_OPC0_bp Predefined. */
4531	/* PORT_OPC1_bm Predefined. */
4532	/* PORT_OPC1_bp Predefined. */
4533	/* PORT_OPC2_bm Predefined. */
4534	/* PORT_OPC2_bp Predefined. */
4535
4536	/* PORT_ISC_gm Predefined. */
4537	/* PORT_ISC_gp Predefined. */
4538	/* PORT_ISC0_bm Predefined. */
4539	/* PORT_ISC0_bp Predefined. */
4540	/* PORT_ISC1_bm Predefined. */
4541	/* PORT_ISC1_bp Predefined. */
4542	/* PORT_ISC2_bm Predefined. */
4543	/* PORT_ISC2_bp Predefined. */
4544
4545
4546	/* PORT.PIN3CTRL bit masks and bit positions */
4547	/* PORT_SRLEN_bm Predefined. */
4548	/* PORT_SRLEN_bp Predefined. */
4549
4550	/* PORT_INVEN_bm Predefined. */
4551	/* PORT_INVEN_bp Predefined. */
4552
4553	/* PORT_OPC_gm Predefined. */
4554	/* PORT_OPC_gp Predefined. */
4555	/* PORT_OPC0_bm Predefined. */
4556	/* PORT_OPC0_bp Predefined. */
4557	/* PORT_OPC1_bm Predefined. */
4558	/* PORT_OPC1_bp Predefined. */
4559	/* PORT_OPC2_bm Predefined. */
4560	/* PORT_OPC2_bp Predefined. */
4561
4562	/* PORT_ISC_gm Predefined. */
4563	/* PORT_ISC_gp Predefined. */
4564	/* PORT_ISC0_bm Predefined. */
4565	/* PORT_ISC0_bp Predefined. */
4566	/* PORT_ISC1_bm Predefined. */
4567	/* PORT_ISC1_bp Predefined. */
4568	/* PORT_ISC2_bm Predefined. */
4569	/* PORT_ISC2_bp Predefined. */
4570
4571
4572	/* PORT.PIN4CTRL bit masks and bit positions */
4573	/* PORT_SRLEN_bm Predefined. */
4574	/* PORT_SRLEN_bp Predefined. */
4575
4576	/* PORT_INVEN_bm Predefined. */
4577	/* PORT_INVEN_bp Predefined. */
4578
4579	/* PORT_OPC_gm Predefined. */
4580	/* PORT_OPC_gp Predefined. */
4581	/* PORT_OPC0_bm Predefined. */
4582	/* PORT_OPC0_bp Predefined. */
4583	/* PORT_OPC1_bm Predefined. */
4584	/* PORT_OPC1_bp Predefined. */
4585	/* PORT_OPC2_bm Predefined. */
4586	/* PORT_OPC2_bp Predefined. */
4587
4588	/* PORT_ISC_gm Predefined. */
4589	/* PORT_ISC_gp Predefined. */
4590	/* PORT_ISC0_bm Predefined. */
4591	/* PORT_ISC0_bp Predefined. */
4592	/* PORT_ISC1_bm Predefined. */
4593	/* PORT_ISC1_bp Predefined. */
4594	/* PORT_ISC2_bm Predefined. */
4595	/* PORT_ISC2_bp Predefined. */
4596
4597
4598	/* PORT.PIN5CTRL bit masks and bit positions */
4599	/* PORT_SRLEN_bm Predefined. */
4600	/* PORT_SRLEN_bp Predefined. */
4601
4602	/* PORT_INVEN_bm Predefined. */
4603	/* PORT_INVEN_bp Predefined. */
4604
4605	/* PORT_OPC_gm Predefined. */
4606	/* PORT_OPC_gp Predefined. */
4607	/* PORT_OPC0_bm Predefined. */
4608	/* PORT_OPC0_bp Predefined. */
4609	/* PORT_OPC1_bm Predefined. */
4610	/* PORT_OPC1_bp Predefined. */
4611	/* PORT_OPC2_bm Predefined. */
4612	/* PORT_OPC2_bp Predefined. */
4613
4614	/* PORT_ISC_gm Predefined. */
4615	/* PORT_ISC_gp Predefined. */
4616	/* PORT_ISC0_bm Predefined. */
4617	/* PORT_ISC0_bp Predefined. */
4618	/* PORT_ISC1_bm Predefined. */
4619	/* PORT_ISC1_bp Predefined. */
4620	/* PORT_ISC2_bm Predefined. */
4621	/* PORT_ISC2_bp Predefined. */
4622
4623
4624	/* PORT.PIN6CTRL bit masks and bit positions */
4625	/* PORT_SRLEN_bm Predefined. */
4626	/* PORT_SRLEN_bp Predefined. */
4627
4628	/* PORT_INVEN_bm Predefined. */
4629	/* PORT_INVEN_bp Predefined. */
4630
4631	/* PORT_OPC_gm Predefined. */
4632	/* PORT_OPC_gp Predefined. */
4633	/* PORT_OPC0_bm Predefined. */
4634	/* PORT_OPC0_bp Predefined. */
4635	/* PORT_OPC1_bm Predefined. */
4636	/* PORT_OPC1_bp Predefined. */
4637	/* PORT_OPC2_bm Predefined. */
4638	/* PORT_OPC2_bp Predefined. */
4639
4640	/* PORT_ISC_gm Predefined. */
4641	/* PORT_ISC_gp Predefined. */
4642	/* PORT_ISC0_bm Predefined. */
4643	/* PORT_ISC0_bp Predefined. */
4644	/* PORT_ISC1_bm Predefined. */
4645	/* PORT_ISC1_bp Predefined. */
4646	/* PORT_ISC2_bm Predefined. */
4647	/* PORT_ISC2_bp Predefined. */
4648
4649
4650	/* PORT.PIN7CTRL bit masks and bit positions */
4651	/* PORT_SRLEN_bm Predefined. */
4652	/* PORT_SRLEN_bp Predefined. */
4653
4654	/* PORT_INVEN_bm Predefined. */
4655	/* PORT_INVEN_bp Predefined. */
4656
4657	/* PORT_OPC_gm Predefined. */
4658	/* PORT_OPC_gp Predefined. */
4659	/* PORT_OPC0_bm Predefined. */
4660	/* PORT_OPC0_bp Predefined. */
4661	/* PORT_OPC1_bm Predefined. */
4662	/* PORT_OPC1_bp Predefined. */
4663	/* PORT_OPC2_bm Predefined. */
4664	/* PORT_OPC2_bp Predefined. */
4665
4666	/* PORT_ISC_gm Predefined. */
4667	/* PORT_ISC_gp Predefined. */
4668	/* PORT_ISC0_bm Predefined. */
4669	/* PORT_ISC0_bp Predefined. */
4670	/* PORT_ISC1_bm Predefined. */
4671	/* PORT_ISC1_bp Predefined. */
4672	/* PORT_ISC2_bm Predefined. */
4673	/* PORT_ISC2_bp Predefined. */
4674
4675
4676	/* TC - 16-bit Timer/Counter With PWM */
4677	/* TC0.CTRLA bit masks and bit positions */
4678	#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4679	#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */
4680	#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4681	#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4682	#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4683	#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4684	#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4685	#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4686	#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4687	#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4688
4689
4690	/* TC0.CTRLB bit masks and bit positions */
4691	#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */
4692	#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */
4693
4694	#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */
4695	#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */
4696
4697	#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4698	#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4699
4700	#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4701	#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4702
4703	#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4704	#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */
4705	#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4706	#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4707	#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4708	#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4709	#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4710	#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4711
4712
4713	/* TC0.CTRLC bit masks and bit positions */
4714	#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */
4715	#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */
4716
4717	#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */
4718	#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */
4719
4720	#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4721	#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */
4722
4723	#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4724	#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */
4725
4726
4727	/* TC0.CTRLD bit masks and bit positions */
4728	#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */
4729	#define TC0_EVACT_gp 5 /* Event Action group position. */
4730	#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4731	#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */
4732	#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4733	#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */
4734	#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4735	#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */
4736
4737	#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */
4738	#define TC0_EVDLY_bp 4 /* Event Delay bit position. */
4739
4740	#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */
4741	#define TC0_EVSEL_gp 0 /* Event Source Select group position. */
4742	#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4743	#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4744	#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4745	#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4746	#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4747	#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4748	#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4749	#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4750
4751
4752	/* TC0.CTRLE bit masks and bit positions */
4753	#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4754	#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */
4755
4756
4757	/* TC0.INTCTRLA bit masks and bit positions */
4758	#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4759	#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4760	#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4761	#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4762	#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4763	#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4764
4765	#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4766	#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4767	#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4768	#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4769	#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4770	#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4771
4772
4773	/* TC0.INTCTRLB bit masks and bit positions */
4774	#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */
4775	#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */
4776	#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */
4777	#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */
4778	#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */
4779	#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */
4780
4781	#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */
4782	#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */
4783	#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */
4784	#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */
4785	#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */
4786	#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */
4787
4788	#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4789	#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4790	#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4791	#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4792	#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4793	#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4794
4795	#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4796	#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4797	#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4798	#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4799	#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4800	#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4801
4802
4803	/* TC0.CTRLFCLR bit masks and bit positions */
4804	#define TC0_CMD_gm 0x0C /* Command group mask. */
4805	#define TC0_CMD_gp 2 /* Command group position. */
4806	#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */
4807	#define TC0_CMD0_bp 2 /* Command bit 0 position. */
4808	#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */
4809	#define TC0_CMD1_bp 3 /* Command bit 1 position. */
4810
4811	#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */
4812	#define TC0_LUPD_bp 1 /* Lock Update bit position. */
4813
4814	#define TC0_DIR_bm 0x01 /* Direction bit mask. */
4815	#define TC0_DIR_bp 0 /* Direction bit position. */
4816
4817
4818	/* TC0.CTRLFSET bit masks and bit positions */
4819	/* TC0_CMD_gm Predefined. */
4820	/* TC0_CMD_gp Predefined. */
4821	/* TC0_CMD0_bm Predefined. */
4822	/* TC0_CMD0_bp Predefined. */
4823	/* TC0_CMD1_bm Predefined. */
4824	/* TC0_CMD1_bp Predefined. */
4825
4826	/* TC0_LUPD_bm Predefined. */
4827	/* TC0_LUPD_bp Predefined. */
4828
4829	/* TC0_DIR_bm Predefined. */
4830	/* TC0_DIR_bp Predefined. */
4831
4832
4833	/* TC0.CTRLGCLR bit masks and bit positions */
4834	#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */
4835	#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */
4836
4837	#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */
4838	#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */
4839
4840	#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
4841	#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
4842
4843	#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
4844	#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
4845
4846	#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
4847	#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */
4848
4849
4850	/* TC0.CTRLGSET bit masks and bit positions */
4851	/* TC0_CCDBV_bm Predefined. */
4852	/* TC0_CCDBV_bp Predefined. */
4853
4854	/* TC0_CCCBV_bm Predefined. */
4855	/* TC0_CCCBV_bp Predefined. */
4856
4857	/* TC0_CCBBV_bm Predefined. */
4858	/* TC0_CCBBV_bp Predefined. */
4859
4860	/* TC0_CCABV_bm Predefined. */
4861	/* TC0_CCABV_bp Predefined. */
4862
4863	/* TC0_PERBV_bm Predefined. */
4864	/* TC0_PERBV_bp Predefined. */
4865
4866
4867	/* TC0.INTFLAGS bit masks and bit positions */
4868	#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */
4869	#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */
4870
4871	#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */
4872	#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */
4873
4874	#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
4875	#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
4876
4877	#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
4878	#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
4879
4880	#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
4881	#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
4882
4883	#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
4884	#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
4885
4886
4887	/* TC1.CTRLA bit masks and bit positions */
4888	#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */
4889	#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */
4890	#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */
4891	#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */
4892	#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */
4893	#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */
4894	#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */
4895	#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */
4896	#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */
4897	#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */
4898
4899
4900	/* TC1.CTRLB bit masks and bit positions */
4901	#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */
4902	#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */
4903
4904	#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */
4905	#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */
4906
4907	#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */
4908	#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */
4909	#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */
4910	#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */
4911	#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */
4912	#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */
4913	#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */
4914	#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */
4915
4916
4917	/* TC1.CTRLC bit masks and bit positions */
4918	#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */
4919	#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */
4920
4921	#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */
4922	#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */
4923
4924
4925	/* TC1.CTRLD bit masks and bit positions */
4926	#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */
4927	#define TC1_EVACT_gp 5 /* Event Action group position. */
4928	#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */
4929	#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */
4930	#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */
4931	#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */
4932	#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */
4933	#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */
4934
4935	#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */
4936	#define TC1_EVDLY_bp 4 /* Event Delay bit position. */
4937
4938	#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */
4939	#define TC1_EVSEL_gp 0 /* Event Source Select group position. */
4940	#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */
4941	#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */
4942	#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */
4943	#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */
4944	#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */
4945	#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */
4946	#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */
4947	#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */
4948
4949
4950	/* TC1.CTRLE bit masks and bit positions */
4951	#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */
4952	#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */
4953
4954
4955	/* TC1.INTCTRLA bit masks and bit positions */
4956	#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */
4957	#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */
4958	#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */
4959	#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */
4960	#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */
4961	#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */
4962
4963	#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */
4964	#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */
4965	#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */
4966	#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */
4967	#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */
4968	#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */
4969
4970
4971	/* TC1.INTCTRLB bit masks and bit positions */
4972	#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */
4973	#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */
4974	#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */
4975	#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */
4976	#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */
4977	#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */
4978
4979	#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */
4980	#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */
4981	#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */
4982	#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */
4983	#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */
4984	#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */
4985
4986
4987	/* TC1.CTRLFCLR bit masks and bit positions */
4988	#define TC1_CMD_gm 0x0C /* Command group mask. */
4989	#define TC1_CMD_gp 2 /* Command group position. */
4990	#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */
4991	#define TC1_CMD0_bp 2 /* Command bit 0 position. */
4992	#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */
4993	#define TC1_CMD1_bp 3 /* Command bit 1 position. */
4994
4995	#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */
4996	#define TC1_LUPD_bp 1 /* Lock Update bit position. */
4997
4998	#define TC1_DIR_bm 0x01 /* Direction bit mask. */
4999	#define TC1_DIR_bp 0 /* Direction bit position. */
5000
5001
5002	/* TC1.CTRLFSET bit masks and bit positions */
5003	/* TC1_CMD_gm Predefined. */
5004	/* TC1_CMD_gp Predefined. */
5005	/* TC1_CMD0_bm Predefined. */
5006	/* TC1_CMD0_bp Predefined. */
5007	/* TC1_CMD1_bm Predefined. */
5008	/* TC1_CMD1_bp Predefined. */
5009
5010	/* TC1_LUPD_bm Predefined. */
5011	/* TC1_LUPD_bp Predefined. */
5012
5013	/* TC1_DIR_bm Predefined. */
5014	/* TC1_DIR_bp Predefined. */
5015
5016
5017	/* TC1.CTRLGCLR bit masks and bit positions */
5018	#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */
5019	#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */
5020
5021	#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */
5022	#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */
5023
5024	#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */
5025	#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */
5026
5027
5028	/* TC1.CTRLGSET bit masks and bit positions */
5029	/* TC1_CCBBV_bm Predefined. */
5030	/* TC1_CCBBV_bp Predefined. */
5031
5032	/* TC1_CCABV_bm Predefined. */
5033	/* TC1_CCABV_bp Predefined. */
5034
5035	/* TC1_PERBV_bm Predefined. */
5036	/* TC1_PERBV_bp Predefined. */
5037
5038
5039	/* TC1.INTFLAGS bit masks and bit positions */
5040	#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */
5041	#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */
5042
5043	#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */
5044	#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */
5045
5046	#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */
5047	#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */
5048
5049	#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */
5050	#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */
5051
5052
5053	/* AWEX.CTRL bit masks and bit positions */
5054	#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */
5055	#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */
5056
5057	#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */
5058	#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */
5059
5060	#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */
5061	#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */
5062
5063	#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */
5064	#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */
5065
5066	#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */
5067	#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */
5068
5069	#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */
5070	#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */
5071
5072
5073	/* AWEX.FDCTRL bit masks and bit positions */
5074	#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */
5075	#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */
5076
5077	#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */
5078	#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */
5079
5080	#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */
5081	#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */
5082	#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */
5083	#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */
5084	#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */
5085	#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */
5086
5087
5088	/* AWEX.STATUS bit masks and bit positions */
5089	#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */
5090	#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */
5091
5092	#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */
5093	#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */
5094
5095	#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */
5096	#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */
5097
5098
5099	/* HIRES.CTRLA bit masks and bit positions */
5100	#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */
5101	#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */
5102	#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */
5103	#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */
5104	#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */
5105	#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */
5106
5107
5108	/* USART - Universal Asynchronous Receiver-Transmitter */
5109	/* USART.STATUS bit masks and bit positions */
5110	#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */
5111	#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */
5112
5113	#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */
5114	#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */
5115
5116	#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */
5117	#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */
5118
5119	#define USART_FERR_bm 0x10 /* Frame Error bit mask. */
5120	#define USART_FERR_bp 4 /* Frame Error bit position. */
5121
5122	#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */
5123	#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */
5124
5125	#define USART_PERR_bm 0x04 /* Parity Error bit mask. */
5126	#define USART_PERR_bp 2 /* Parity Error bit position. */
5127
5128	#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */
5129	#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */
5130
5131
5132	/* USART.CTRLA bit masks and bit positions */
5133	#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */
5134	#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */
5135	#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */
5136	#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */
5137	#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */
5138	#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */
5139
5140	#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */
5141	#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */
5142	#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */
5143	#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */
5144	#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */
5145	#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */
5146
5147	#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */
5148	#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */
5149	#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */
5150	#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */
5151	#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */
5152	#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */
5153
5154
5155	/* USART.CTRLB bit masks and bit positions */
5156	#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */
5157	#define USART_RXEN_bp 4 /* Receiver Enable bit position. */
5158
5159	#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */
5160	#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */
5161
5162	#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */
5163	#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */
5164
5165	#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */
5166	#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */
5167
5168	#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */
5169	#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */
5170
5171
5172	/* USART.CTRLC bit masks and bit positions */
5173	#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */
5174	#define USART_CMODE_gp 6 /* Communication Mode group position. */
5175	#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */
5176	#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */
5177	#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */
5178	#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */
5179
5180	#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */
5181	#define USART_PMODE_gp 4 /* Parity Mode group position. */
5182	#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */
5183	#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */
5184	#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */
5185	#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */
5186
5187	#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */
5188	#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */
5189
5190	#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */
5191	#define USART_CHSIZE_gp 0 /* Character Size group position. */
5192	#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */
5193	#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */
5194	#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */
5195	#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */
5196	#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */
5197	#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */
5198
5199
5200	/* USART.BAUDCTRLA bit masks and bit positions */
5201	#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */
5202	#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */
5203	#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */
5204	#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */
5205	#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */
5206	#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */
5207	#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */
5208	#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */
5209	#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */
5210	#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */
5211	#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */
5212	#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */
5213	#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */
5214	#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */
5215	#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */
5216	#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */
5217	#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */
5218	#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */
5219
5220
5221	/* USART.BAUDCTRLB bit masks and bit positions */
5222	#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */
5223	#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */
5224	#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */
5225	#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */
5226	#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */
5227	#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */
5228	#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */
5229	#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */
5230	#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */
5231	#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */
5232
5233	/* USART_BSEL_gm Predefined. */
5234	/* USART_BSEL_gp Predefined. */
5235	/* USART_BSEL0_bm Predefined. */
5236	/* USART_BSEL0_bp Predefined. */
5237	/* USART_BSEL1_bm Predefined. */
5238	/* USART_BSEL1_bp Predefined. */
5239	/* USART_BSEL2_bm Predefined. */
5240	/* USART_BSEL2_bp Predefined. */
5241	/* USART_BSEL3_bm Predefined. */
5242	/* USART_BSEL3_bp Predefined. */
5243
5244
5245	/* SPI - Serial Peripheral Interface */
5246	/* SPI.CTRL bit masks and bit positions */
5247	#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */
5248	#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */
5249
5250	#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */
5251	#define SPI_ENABLE_bp 6 /* Enable Module bit position. */
5252
5253	#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */
5254	#define SPI_DORD_bp 5 /* Data Order Setting bit position. */
5255
5256	#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */
5257	#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */
5258
5259	#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */
5260	#define SPI_MODE_gp 2 /* SPI Mode group position. */
5261	#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */
5262	#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */
5263	#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */
5264	#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */
5265
5266	#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */
5267	#define SPI_PRESCALER_gp 0 /* Prescaler group position. */
5268	#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */
5269	#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */
5270	#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */
5271	#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */
5272
5273
5274	/* SPI.INTCTRL bit masks and bit positions */
5275	#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */
5276	#define SPI_INTLVL_gp 0 /* Interrupt level group position. */
5277	#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */
5278	#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */
5279	#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */
5280	#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */
5281
5282
5283	/* SPI.STATUS bit masks and bit positions */
5284	#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */
5285	#define SPI_IF_bp 7 /* Interrupt Flag bit position. */
5286
5287	#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */
5288	#define SPI_WRCOL_bp 6 /* Write Collision bit position. */
5289
5290
5291	/* IRCOM - IR Communication Module */
5292	/* IRCOM.CTRL bit masks and bit positions */
5293	#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */
5294	#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */
5295	#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */
5296	#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */
5297	#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */
5298	#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */
5299	#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */
5300	#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */
5301	#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */
5302	#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */
5303
5304
5305
5306	// Generic Port Pins
5307
5308	#define PIN0_bm 0x01
5309	#define PIN0_bp 0
5310	#define PIN1_bm 0x02
5311	#define PIN1_bp 1
5312	#define PIN2_bm 0x04
5313	#define PIN2_bp 2
5314	#define PIN3_bm 0x08
5315	#define PIN3_bp 3
5316	#define PIN4_bm 0x10
5317	#define PIN4_bp 4
5318	#define PIN5_bm 0x20
5319	#define PIN5_bp 5
5320	#define PIN6_bm 0x40
5321	#define PIN6_bp 6
5322	#define PIN7_bm 0x80
5323	#define PIN7_bp 7
5324
5325
5326	/* ========== Interrupt Vector Definitions ========== */
5327	/* Vector 0 is the reset vector */
5328
5329	/* OSC interrupt vectors */
5330	#define OSC_XOSCF_vect_num 1
5331	#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */
5332
5333	/* PORTC interrupt vectors */
5334	#define PORTC_INT0_vect_num 2
5335	#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */
5336	#define PORTC_INT1_vect_num 3
5337	#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */
5338
5339	/* PORTR interrupt vectors */
5340	#define PORTR_INT0_vect_num 4
5341	#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */
5342	#define PORTR_INT1_vect_num 5
5343	#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */
5344
5345	/* RTC interrupt vectors */
5346	#define RTC_OVF_vect_num 10
5347	#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */
5348	#define RTC_COMP_vect_num 11
5349	#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */
5350
5351	/* TWIC interrupt vectors */
5352	#define TWIC_TWIS_vect_num 12
5353	#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */
5354	#define TWIC_TWIM_vect_num 13
5355	#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */
5356
5357	/* TCC0 interrupt vectors */
5358	#define TCC0_OVF_vect_num 14
5359	#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */
5360	#define TCC0_ERR_vect_num 15
5361	#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */
5362	#define TCC0_CCA_vect_num 16
5363	#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */
5364	#define TCC0_CCB_vect_num 17
5365	#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */
5366	#define TCC0_CCC_vect_num 18
5367	#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */
5368	#define TCC0_CCD_vect_num 19
5369	#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */
5370
5371	/* TCC1 interrupt vectors */
5372	#define TCC1_OVF_vect_num 20
5373	#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */
5374	#define TCC1_ERR_vect_num 21
5375	#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */
5376	#define TCC1_CCA_vect_num 22
5377	#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */
5378	#define TCC1_CCB_vect_num 23
5379	#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */
5380
5381	/* SPIC interrupt vectors */
5382	#define SPIC_INT_vect_num 24
5383	#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */
5384
5385	/* USARTC0 interrupt vectors */
5386	#define USARTC0_RXC_vect_num 25
5387	#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */
5388	#define USARTC0_DRE_vect_num 26
5389	#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */
5390	#define USARTC0_TXC_vect_num 27
5391	#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */
5392
5393	/* NVM interrupt vectors */
5394	#define NVM_EE_vect_num 32
5395	#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */
5396	#define NVM_SPM_vect_num 33
5397	#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */
5398
5399	/* PORTB interrupt vectors */
5400	#define PORTB_INT0_vect_num 34
5401	#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */
5402	#define PORTB_INT1_vect_num 35
5403	#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */
5404
5405	/* PORTE interrupt vectors */
5406	#define PORTE_INT0_vect_num 43
5407	#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */
5408	#define PORTE_INT1_vect_num 44
5409	#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */
5410
5411	/* TCE0 interrupt vectors */
5412	#define TCE0_OVF_vect_num 47
5413	#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */
5414	#define TCE0_ERR_vect_num 48
5415	#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */
5416	#define TCE0_CCA_vect_num 49
5417	#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */
5418	#define TCE0_CCB_vect_num 50
5419	#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */
5420	#define TCE0_CCC_vect_num 51
5421	#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */
5422	#define TCE0_CCD_vect_num 52
5423	#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */
5424
5425	/* USARTE0 interrupt vectors */
5426	#define USARTE0_RXC_vect_num 58
5427	#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */
5428	#define USARTE0_DRE_vect_num 59
5429	#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */
5430	#define USARTE0_TXC_vect_num 60
5431	#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */
5432
5433	/* PORTD interrupt vectors */
5434	#define PORTD_INT0_vect_num 64
5435	#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */
5436	#define PORTD_INT1_vect_num 65
5437	#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */
5438
5439	/* PORTA interrupt vectors */
5440	#define PORTA_INT0_vect_num 66
5441	#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */
5442	#define PORTA_INT1_vect_num 67
5443	#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */
5444
5445	/* ACA interrupt vectors */
5446	#define ACA_AC0_vect_num 68
5447	#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */
5448	#define ACA_AC1_vect_num 69
5449	#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */
5450	#define ACA_ACW_vect_num 70
5451	#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */
5452
5453	/* ADCA interrupt vectors */
5454	#define ADCA_CH0_vect_num 71
5455	#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */
5456
5457	/* TCD0 interrupt vectors */
5458	#define TCD0_OVF_vect_num 77
5459	#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */
5460	#define TCD0_ERR_vect_num 78
5461	#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */
5462	#define TCD0_CCA_vect_num 79
5463	#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */
5464	#define TCD0_CCB_vect_num 80
5465	#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */
5466	#define TCD0_CCC_vect_num 81
5467	#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */
5468	#define TCD0_CCD_vect_num 82
5469	#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */
5470
5471	/* SPID interrupt vectors */
5472	#define SPID_INT_vect_num 87
5473	#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */
5474
5475	/* USARTD0 interrupt vectors */
5476	#define USARTD0_RXC_vect_num 88
5477	#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */
5478	#define USARTD0_DRE_vect_num 89
5479	#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */
5480	#define USARTD0_TXC_vect_num 90
5481	#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */
5482
5483	/* PORTF interrupt vectors */
5484	#define PORTF_INT0_vect_num 104
5485	#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */
5486	#define PORTF_INT1_vect_num 105
5487	#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */
5488
5489	/* TCF0 interrupt vectors */
5490	#define TCF0_OVF_vect_num 108
5491	#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */
5492	#define TCF0_ERR_vect_num 109
5493	#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */
5494	#define TCF0_CCA_vect_num 110
5495	#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */
5496	#define TCF0_CCB_vect_num 111
5497	#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */
5498	#define TCF0_CCC_vect_num 112
5499	#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */
5500	#define TCF0_CCD_vect_num 113
5501	#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */
5502
5503
5504	#define _VECTOR_SIZE 4 /* Size of individual vector. */
5505	#define _VECTORS_SIZE (114 * _VECTOR_SIZE)
5506
5507
5508	/* ========== Constants ========== */
5509
5510	#define PROGMEM_START (0x0000)
5511	#define PROGMEM_SIZE (204800)
5512	#define PROGMEM_PAGE_SIZE (512)
5513	#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1)
5514
5515	#define APP_SECTION_START (0x0000)
5516	#define APP_SECTION_SIZE (196608)
5517	#define APP_SECTION_PAGE_SIZE (512)
5518	#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1)
5519
5520	#define APPTABLE_SECTION_START (0x2E000)
5521	#define APPTABLE_SECTION_SIZE (8192)
5522	#define APPTABLE_SECTION_PAGE_SIZE (512)
5523	#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
5524
5525	#define BOOT_SECTION_START (0x30000)
5526	#define BOOT_SECTION_SIZE (8192)
5527	#define BOOT_SECTION_PAGE_SIZE (512)
5528	#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1)
5529
5530	#define DATAMEM_START (0x0000)
5531	#define DATAMEM_SIZE (24576)
5532	#define DATAMEM_PAGE_SIZE (0)
5533	#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1)
5534
5535	#define IO_START (0x0000)
5536	#define IO_SIZE (4096)
5537	#define IO_PAGE_SIZE (0)
5538	#define IO_END (IO_START + IO_SIZE - 1)
5539
5540	#define MAPPED_EEPROM_START (0x1000)
5541	#define MAPPED_EEPROM_SIZE (2048)
5542	#define MAPPED_EEPROM_PAGE_SIZE (0)
5543	#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1)
5544
5545	#define INTERNAL_SRAM_START (0x2000)
5546	#define INTERNAL_SRAM_SIZE (16384)
5547	#define INTERNAL_SRAM_PAGE_SIZE (0)
5548	#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1)
5549
5550	#define EEPROM_START (0x0000)
5551	#define EEPROM_SIZE (2048)
5552	#define EEPROM_PAGE_SIZE (32)
5553	#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1)
5554
5555	#define FUSE_START (0x0000)
5556	#define FUSE_SIZE (6)
5557	#define FUSE_PAGE_SIZE (0)
5558	#define FUSE_END (FUSE_START + FUSE_SIZE - 1)
5559
5560	#define LOCKBIT_START (0x0000)
5561	#define LOCKBIT_SIZE (1)
5562	#define LOCKBIT_PAGE_SIZE (0)
5563	#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1)
5564
5565	#define SIGNATURES_START (0x0000)
5566	#define SIGNATURES_SIZE (3)
5567	#define SIGNATURES_PAGE_SIZE (0)
5568	#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1)
5569
5570	#define USER_SIGNATURES_START (0x0000)
5571	#define USER_SIGNATURES_SIZE (512)
5572	#define USER_SIGNATURES_PAGE_SIZE (0)
5573	#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
5574
5575	#define PROD_SIGNATURES_START (0x0000)
5576	#define PROD_SIGNATURES_SIZE (52)
5577	#define PROD_SIGNATURES_PAGE_SIZE (0)
5578	#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
5579
5580	#define FLASHEND PROGMEM_END
5581	#define SPM_PAGESIZE PROGMEM_PAGE_SIZE
5582	#define RAMSTART INTERNAL_SRAM_START
5583	#define RAMSIZE INTERNAL_SRAM_SIZE
5584	#define RAMEND INTERNAL_SRAM_END
5585	#define XRAMSTART EXTERNAL_SRAM_START
5586	#define XRAMSIZE EXTERNAL_SRAM_SIZE
5587	#define XRAMEND INTERNAL_SRAM_END
5588	#define E2END EEPROM_END
5589	#define E2PAGESIZE EEPROM_PAGE_SIZE
5590
5591
5592	/* ========== Fuses ========== */
5593	#define FUSE_MEMORY_SIZE 6
5594
5595	/* Fuse Byte 0 */
5596	#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */
5597	#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */
5598	#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */
5599	#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */
5600	#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */
5601	#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */
5602	#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */
5603	#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */
5604	#define FUSE0_DEFAULT (0xFF)
5605
5606	/* Fuse Byte 1 */
5607	#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */
5608	#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */
5609	#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */
5610	#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */
5611	#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */
5612	#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */
5613	#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */
5614	#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */
5615	#define FUSE1_DEFAULT (0xFF)
5616
5617	/* Fuse Byte 2 */
5618	#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */
5619	#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */
5620	#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */
5621	#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */
5622	#define FUSE2_DEFAULT (0xFF)
5623
5624	/* Fuse Byte 3 Reserved */
5625
5626	/* Fuse Byte 4 */
5627	#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */
5628	#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */
5629	#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */
5630	#define FUSE4_DEFAULT (0xFF)
5631
5632	/* Fuse Byte 5 */
5633	#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */
5634	#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */
5635	#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */
5636	#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */
5637	#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */
5638	#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */
5639	#define FUSE5_DEFAULT (0xFF)
5640
5641
5642	/* ========== Lock Bits ========== */
5643	#define __LOCK_BITS_EXIST
5644	#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
5645	#define __BOOT_LOCK_APPLICATION_BITS_EXIST
5646	#define __BOOT_LOCK_BOOT_BITS_EXIST
5647
5648
5649	/* ========== Signature ========== */
5650	#define SIGNATURE_0 0x1E
5651	#define SIGNATURE_1 0x97
5652	#define SIGNATURE_2 0x49
5653
5654	/*@}/
5655	#endif /* _AVR_ATxmega192D3_H_ */

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