1 | /* Copyright (c) 2006, Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 |
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34 | and AT90USB1287 */ |
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35 | |
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36 | #ifndef _AVR_IOUSBXX6_7_H_ |
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37 | #define _AVR_IOUSBXX6_7_H_ 1 |
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38 | |
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39 | /* This file should only be included from <avr/io.h>, never directly. */ |
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40 | |
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41 | #ifndef _AVR_IO_H_ |
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42 | # error "Include <avr/io.h> instead of this file." |
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43 | #endif |
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44 | |
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45 | #ifndef _AVR_IOXXX_H_ |
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46 | # define _AVR_IOXXX_H_ "iousbxx6_7.h" |
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47 | #else |
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48 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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49 | #endif |
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50 | |
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51 | #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) |
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52 | # define __AT90USBxx6__ 1 |
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53 | #elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) |
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54 | # define __AT90USBxx7__ 1 |
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55 | #endif |
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56 | |
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57 | /* Registers and associated bit numbers */ |
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58 | |
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59 | #define PINA _SFR_IO8(0X00) |
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60 | #define PINA7 7 |
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61 | #define PINA6 6 |
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62 | #define PINA5 5 |
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63 | #define PINA4 4 |
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64 | #define PINA3 3 |
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65 | #define PINA2 2 |
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66 | #define PINA1 1 |
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67 | #define PINA0 0 |
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68 | |
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69 | #define DDRA _SFR_IO8(0X01) |
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70 | #define DDA7 7 |
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71 | #define DDA6 6 |
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72 | #define DDA5 5 |
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73 | #define DDA4 4 |
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74 | #define DDA3 3 |
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75 | #define DDA2 2 |
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76 | #define DDA1 1 |
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77 | #define DDA0 0 |
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78 | |
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79 | #define PORTA _SFR_IO8(0X02) |
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80 | #define PA7 7 |
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81 | #define PA6 6 |
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82 | #define PA5 5 |
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83 | #define PA4 4 |
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84 | #define PA3 3 |
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85 | #define PA2 2 |
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86 | #define PA1 1 |
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87 | #define PA0 0 |
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88 | |
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89 | #define PINB _SFR_IO8(0X03) |
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90 | #define PINB7 7 |
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91 | #define PINB6 6 |
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92 | #define PINB5 5 |
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93 | #define PINB4 4 |
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94 | #define PINB3 3 |
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95 | #define PINB2 2 |
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96 | #define PINB1 1 |
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97 | #define PINB0 0 |
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98 | |
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99 | #define DDRB _SFR_IO8(0x04) |
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100 | #define DDB7 7 |
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101 | #define DDB6 6 |
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102 | #define DDB5 5 |
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103 | #define DDB4 4 |
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104 | #define DDB3 3 |
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105 | #define DDB2 2 |
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106 | #define DDB1 1 |
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107 | #define DDB0 0 |
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108 | |
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109 | #define PORTB _SFR_IO8(0x05) |
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110 | #define PB7 7 |
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111 | #define PB6 6 |
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112 | #define PB5 5 |
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113 | #define PB4 4 |
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114 | #define PB3 3 |
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115 | #define PB2 2 |
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116 | #define PB1 1 |
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117 | #define PB0 0 |
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118 | |
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119 | #define PINC _SFR_IO8(0x06) |
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120 | #define PINC7 7 |
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121 | #define PINC6 6 |
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122 | #define PINC5 5 |
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123 | #define PINC4 4 |
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124 | #define PINC3 3 |
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125 | #define PINC2 2 |
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126 | #define PINC1 1 |
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127 | #define PINC0 0 |
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128 | |
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129 | #define DDRC _SFR_IO8(0x07) |
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130 | #define DDC7 7 |
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131 | #define DDC6 6 |
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132 | #define DDC5 5 |
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133 | #define DDC4 4 |
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134 | #define DDC3 3 |
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135 | #define DDC2 2 |
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136 | #define DDC1 1 |
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137 | #define DDC0 0 |
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138 | |
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139 | #define PORTC _SFR_IO8(0x08) |
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140 | #define PC7 7 |
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141 | #define PC6 6 |
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142 | #define PC5 5 |
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143 | #define PC4 4 |
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144 | #define PC3 3 |
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145 | #define PC2 2 |
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146 | #define PC1 1 |
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147 | #define PC0 0 |
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148 | |
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149 | #define PIND _SFR_IO8(0x09) |
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150 | #define PIND7 7 |
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151 | #define PIND6 6 |
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152 | #define PIND5 5 |
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153 | #define PIND4 4 |
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154 | #define PIND3 3 |
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155 | #define PIND2 2 |
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156 | #define PIND1 1 |
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157 | #define PIND0 0 |
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158 | |
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159 | #define DDRD _SFR_IO8(0x0A) |
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160 | #define DDD7 7 |
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161 | #define DDD6 6 |
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162 | #define DDD5 5 |
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163 | #define DDD4 4 |
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164 | #define DDD3 3 |
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165 | #define DDD2 2 |
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166 | #define DDD1 1 |
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167 | #define DDD0 0 |
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168 | |
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169 | #define PORTD _SFR_IO8(0x0B) |
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170 | #define PD7 7 |
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171 | #define PD6 6 |
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172 | #define PD5 5 |
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173 | #define PD4 4 |
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174 | #define PD3 3 |
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175 | #define PD2 2 |
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176 | #define PD1 1 |
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177 | #define PD0 0 |
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178 | |
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179 | #define PINE _SFR_IO8(0x0C) |
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180 | #define PINE7 7 |
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181 | #define PINE6 6 |
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182 | #define PINE5 5 |
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183 | #define PINE4 4 |
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184 | #define PINE3 3 |
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185 | #define PINE2 2 |
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186 | #define PINE1 1 |
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187 | #define PINE0 0 |
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188 | |
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189 | #define DDRE _SFR_IO8(0x0D) |
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190 | #define DDE7 7 |
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191 | #define DDE6 6 |
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192 | #define DDE5 5 |
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193 | #define DDE4 4 |
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194 | #define DDE3 3 |
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195 | #define DDE2 2 |
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196 | #define DDE1 1 |
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197 | #define DDE0 0 |
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198 | |
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199 | #define PORTE _SFR_IO8(0x0E) |
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200 | #define PE7 7 |
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201 | #define PE6 6 |
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202 | #define PE5 5 |
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203 | #define PE4 4 |
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204 | #define PE3 3 |
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205 | #define PE2 2 |
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206 | #define PE1 1 |
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207 | #define PE0 0 |
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208 | |
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209 | #define PINF _SFR_IO8(0x0F) |
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210 | #define PINF7 7 |
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211 | #define PINF6 6 |
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212 | #define PINF5 5 |
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213 | #define PINF4 4 |
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214 | #define PINF3 3 |
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215 | #define PINF2 2 |
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216 | #define PINF1 1 |
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217 | #define PINF0 0 |
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218 | |
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219 | #define DDRF _SFR_IO8(0x10) |
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220 | #define DDF7 7 |
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221 | #define DDF6 6 |
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222 | #define DDF5 5 |
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223 | #define DDF4 4 |
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224 | #define DDF3 3 |
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225 | #define DDF2 2 |
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226 | #define DDF1 1 |
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227 | #define DDF0 0 |
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228 | |
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229 | #define PORTF _SFR_IO8(0x11) |
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230 | #define PF7 7 |
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231 | #define PF6 6 |
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232 | #define PF5 5 |
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233 | #define PF4 4 |
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234 | #define PF3 3 |
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235 | #define PF2 2 |
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236 | #define PF1 1 |
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237 | #define PF0 0 |
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238 | |
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239 | /* Reserved [0x12..0x14] */ |
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240 | |
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241 | #define TIFR0 _SFR_IO8(0x15) |
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242 | #define OCF0B 2 |
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243 | #define OCF0A 1 |
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244 | #define TOV0 0 |
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245 | |
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246 | #define TIFR1 _SFR_IO8(0x16) |
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247 | #define ICF1 5 |
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248 | #define OCF1C 3 |
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249 | #define OCF1B 2 |
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250 | #define OCF1A 1 |
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251 | #define TOV1 0 |
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252 | |
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253 | #define TIFR2 _SFR_IO8(0x17) |
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254 | #define OCF2B 2 |
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255 | #define OCF2A 1 |
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256 | #define TOV2 0 |
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257 | |
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258 | #define TIFR3 _SFR_IO8(0x18) |
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259 | #define ICF3 5 |
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260 | #define OCF3C 3 |
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261 | #define OCF3B 2 |
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262 | #define OCF3A 1 |
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263 | #define TOV3 0 |
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264 | |
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265 | /* Reserved [0x19..0x1A] */ |
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266 | |
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267 | #define PCIFR _SFR_IO8(0x1B) |
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268 | #define PCIF0 0 |
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269 | |
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270 | #define EIFR _SFR_IO8(0x1C) |
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271 | #define INTF7 7 |
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272 | #define INTF6 6 |
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273 | #define INTF5 5 |
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274 | #define INTF4 4 |
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275 | #define INTF3 3 |
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276 | #define INTF2 2 |
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277 | #define INTF1 1 |
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278 | #define INTF0 0 |
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279 | |
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280 | #define EIMSK _SFR_IO8(0x1D) |
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281 | #define INT7 7 |
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282 | #define INT6 6 |
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283 | #define INT5 5 |
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284 | #define INT4 4 |
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285 | #define INT3 3 |
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286 | #define INT2 2 |
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287 | #define INT1 1 |
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288 | #define INT0 0 |
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289 | |
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290 | #define GPIOR0 _SFR_IO8(0x1E) |
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291 | |
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292 | #define EECR _SFR_IO8(0x1F) |
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293 | #define EEPM1 5 |
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294 | #define EEPM0 4 |
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295 | #define EERIE 3 |
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296 | #define EEMPE 2 |
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297 | #define EEPE 1 |
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298 | #define EERE 0 |
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299 | |
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300 | #define EEDR _SFR_IO8(0x20) |
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301 | |
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302 | #define EEAR _SFR_IO16(0x21) |
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303 | #define EEARL _SFR_IO8(0x21) |
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304 | #define EEARH _SFR_IO8(0x22) |
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305 | |
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306 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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307 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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308 | subroutines. |
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309 | First two letters: EECR address. |
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310 | Second two letters: EEDR address. |
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311 | Last two letters: EEAR address. */ |
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312 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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313 | |
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314 | #define GTCCR _SFR_IO8(0x23) |
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315 | #define TSM 7 |
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316 | #define PSRASY 1 |
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317 | #define PSRSYNC 0 |
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318 | |
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319 | #define TCCR0A _SFR_IO8(0x24) |
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320 | #define COM0A1 7 |
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321 | #define COM0A0 6 |
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322 | #define COM0B1 5 |
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323 | #define COM0B0 4 |
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324 | #define WGM01 1 |
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325 | #define WGM00 0 |
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326 | |
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327 | #define TCCR0B _SFR_IO8(0x25) |
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328 | #define FOC0A 7 |
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329 | #define FOC0B 6 |
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330 | #define WGM02 3 |
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331 | #define CS02 2 |
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332 | #define CS01 1 |
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333 | #define CS00 0 |
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334 | |
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335 | #define TCNT0 _SFR_IO8(0X26) |
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336 | |
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337 | #define OCR0A _SFR_IO8(0x27) |
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338 | |
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339 | #define OCR0B _SFR_IO8(0X28) |
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340 | |
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341 | #define PLLCSR _SFR_IO8(0x29) |
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342 | #define PLLP2 4 |
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343 | #define PLLP1 3 |
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344 | #define PLLP0 2 |
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345 | #define PLLE 1 |
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346 | #define PLOCK 0 |
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347 | |
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348 | #define GPIOR1 _SFR_IO8(0x2A) |
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349 | |
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350 | #define GPIOR2 _SFR_IO8(0x2B) |
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351 | |
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352 | #define SPCR _SFR_IO8(0x2C) |
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353 | #define SPIE 7 |
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354 | #define SPE 6 |
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355 | #define DORD 5 |
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356 | #define MSTR 4 |
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357 | #define CPOL 3 |
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358 | #define CPHA 2 |
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359 | #define SPR1 1 |
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360 | #define SPR0 0 |
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361 | |
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362 | #define SPSR _SFR_IO8(0x2D) |
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363 | #define SPIF 7 |
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364 | #define WCOL 6 |
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365 | #define SPI2X 0 |
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366 | |
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367 | #define SPDR _SFR_IO8(0x2E) |
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368 | |
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369 | /* Reserved [0x2F] */ |
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370 | |
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371 | #define ACSR _SFR_IO8(0x30) |
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372 | #define ACD 7 |
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373 | #define ACBG 6 |
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374 | #define ACO 5 |
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375 | #define ACI 4 |
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376 | #define ACIE 3 |
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377 | #define ACIC 2 |
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378 | #define ACIS1 1 |
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379 | #define ACIS0 0 |
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380 | |
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381 | #define MONDR _SFR_IO8(0x31) |
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382 | #define OCDR _SFR_IO8(0x31) |
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383 | #define IDRD 7 |
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384 | #define OCDR7 7 |
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385 | #define OCDR6 6 |
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386 | #define OCDR5 5 |
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387 | #define OCDR4 4 |
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388 | #define OCDR3 3 |
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389 | #define OCDR2 2 |
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390 | #define OCDR1 1 |
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391 | #define OCDR0 0 |
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392 | |
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393 | /* Reserved [0x32] */ |
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394 | |
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395 | #define SMCR _SFR_IO8(0x33) |
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396 | #define SM2 3 |
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397 | #define SM1 2 |
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398 | #define SM0 1 |
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399 | #define SE 0 |
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400 | |
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401 | #define MCUSR _SFR_IO8(0x34) |
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402 | #define JTRF 4 |
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403 | #define WDRF 3 |
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404 | #define BORF 2 |
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405 | #define EXTRF 1 |
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406 | #define PORF 0 |
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407 | |
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408 | #define MCUCR _SFR_IO8(0x35) |
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409 | #define JTD 7 |
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410 | #define PUD 4 |
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411 | #define IVSEL 1 |
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412 | #define IVCE 0 |
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413 | |
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414 | /* Reserved [0x36] */ |
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415 | |
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416 | #define SPMCSR _SFR_IO8(0x37) |
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417 | #define SPMIE 7 |
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418 | #define RWWSB 6 |
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419 | #define SIGRD 5 |
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420 | #define RWWSRE 4 |
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421 | #define BLBSET 3 |
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422 | #define PGWRT 2 |
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423 | #define PGERS 1 |
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424 | #define SPMEN 0 |
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425 | |
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426 | /* Reserved [0x38..0x3A] */ |
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427 | |
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428 | #if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) |
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429 | #define RAMPZ _SFR_IO8(0x3B) |
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430 | #endif |
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431 | |
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432 | /* Reserved [0x3C] */ |
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433 | |
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434 | /* SP [0x3D..0x3E] */ |
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435 | /* SREG [0x3F] */ |
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436 | |
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437 | #define WDTCSR _SFR_MEM8(0x60) |
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438 | #define WDIF 7 |
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439 | #define WDIE 6 |
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440 | #define WDP3 5 |
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441 | #define WDCE 4 |
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442 | #define WDE 3 |
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443 | #define WDP2 2 |
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444 | #define WDP1 1 |
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445 | #define WDP0 0 |
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446 | |
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447 | #define CLKPR _SFR_MEM8(0x61) |
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448 | #define CLKPCE 7 |
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449 | #define CLKPS3 3 |
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450 | #define CLKPS2 2 |
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451 | #define CLKPS1 1 |
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452 | #define CLKPS0 0 |
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453 | |
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454 | /* Reserved [0x62..0x63] */ |
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455 | |
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456 | #define PRR0 _SFR_MEM8(0x64) |
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457 | #define PRTWI 7 |
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458 | #define PRTIM2 6 |
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459 | #define PRTIM0 5 |
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460 | #define PRTIM1 3 |
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461 | #define PRSPI 2 |
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462 | #define PRADC 0 |
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463 | |
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464 | #define PRR1 _SFR_MEM8(0x65) |
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465 | #define PRUSB 7 |
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466 | #define PRTIM3 3 |
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467 | #define PRUSART1 0 |
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468 | |
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469 | #define OSCCAL _SFR_MEM8(0x66) |
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470 | |
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471 | /* Reserved [0x67] */ |
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472 | |
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473 | #define PCICR _SFR_MEM8(0x68) |
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474 | #define PCIE0 0 |
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475 | |
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476 | #define EICRA _SFR_MEM8(0x69) |
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477 | #define ISC31 7 |
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478 | #define ISC30 6 |
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479 | #define ISC21 5 |
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480 | #define ISC20 4 |
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481 | #define ISC11 3 |
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482 | #define ISC10 2 |
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483 | #define ISC01 1 |
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484 | #define ISC00 0 |
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485 | |
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486 | #define EICRB _SFR_MEM8(0x6A) |
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487 | #define ISC71 7 |
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488 | #define ISC70 6 |
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489 | #define ISC61 5 |
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490 | #define ISC60 4 |
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491 | #define ISC51 3 |
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492 | #define ISC50 2 |
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493 | #define ISC41 1 |
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494 | #define ISC40 0 |
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495 | |
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496 | #define PCMSK0 _SFR_MEM8(0x6B) |
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497 | #define PCINT7 7 |
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498 | #define PCINT6 6 |
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499 | #define PCINT5 5 |
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500 | #define PCINT4 4 |
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501 | #define PCINT3 3 |
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502 | #define PCINT2 2 |
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503 | #define PCINT1 1 |
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504 | #define PCINT0 0 |
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505 | |
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506 | /* Reserved [0x6C..0x6D] */ |
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507 | |
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508 | #define TIMSK0 _SFR_MEM8(0x6E) |
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509 | #define OCIE0B 2 |
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510 | #define OCIE0A 1 |
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511 | #define TOIE0 0 |
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512 | |
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513 | #define TIMSK1 _SFR_MEM8(0x6F) |
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514 | #define ICIE1 5 |
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515 | #define OCIE1C 3 |
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516 | #define OCIE1B 2 |
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517 | #define OCIE1A 1 |
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518 | #define TOIE1 0 |
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519 | |
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520 | #define TIMSK2 _SFR_MEM8(0x70) |
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521 | #define OCIE2B 2 |
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522 | #define OCIE2A 1 |
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523 | #define TOIE2 0 |
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524 | |
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525 | #define TIMSK3 _SFR_MEM8(0x71) |
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526 | #define ICIE3 5 |
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527 | #define OCIE3C 3 |
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528 | #define OCIE3B 2 |
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529 | #define OCIE3A 1 |
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530 | #define TOIE3 0 |
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531 | |
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532 | /* Reserved [0x72..0x73] */ |
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533 | |
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534 | #define XMCRA _SFR_MEM8(0x74) |
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535 | #define SRE 7 |
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536 | #define SRL2 6 |
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537 | #define SRL1 5 |
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538 | #define SRL0 4 |
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539 | #define SRW11 3 |
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540 | #define SRW10 2 |
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541 | #define SRW01 1 |
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542 | #define SRW00 0 |
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543 | |
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544 | #define XMCRB _SFR_MEM8(0x75) |
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545 | #define XMBK 7 |
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546 | #define XMM2 2 |
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547 | #define XMM1 1 |
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548 | #define XMM0 0 |
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549 | |
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550 | /* Reserved [0x76..0x77] */ |
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551 | |
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552 | /* RegDef: ADC Data Register */ |
---|
553 | #ifndef __ASSEMBLER__ |
---|
554 | #define ADC _SFR_MEM16(0x78) |
---|
555 | #endif |
---|
556 | #define ADCW _SFR_MEM16(0x78) |
---|
557 | #define ADCL _SFR_MEM8(0x78) |
---|
558 | #define ADCH _SFR_MEM8(0x79) |
---|
559 | |
---|
560 | #define ADCSRA _SFR_MEM8(0x7A) |
---|
561 | #define ADEN 7 |
---|
562 | #define ADSC 6 |
---|
563 | #define ADATE 5 |
---|
564 | #define ADIF 4 |
---|
565 | #define ADIE 3 |
---|
566 | #define ADPS2 2 |
---|
567 | #define ADPS1 1 |
---|
568 | #define ADPS0 0 |
---|
569 | |
---|
570 | #define ADCSRB _SFR_MEM8(0x7B) |
---|
571 | #define ACME 6 |
---|
572 | #define ADTS2 2 |
---|
573 | #define ADTS1 1 |
---|
574 | #define ADTS0 0 |
---|
575 | |
---|
576 | #define ADMUX _SFR_MEM8(0x7C) |
---|
577 | #define REFS1 7 |
---|
578 | #define REFS0 6 |
---|
579 | #define ADLAR 5 |
---|
580 | #define MUX4 4 |
---|
581 | #define MUX3 3 |
---|
582 | #define MUX2 2 |
---|
583 | #define MUX1 1 |
---|
584 | #define MUX0 0 |
---|
585 | |
---|
586 | /* Reserved [0x7D] */ |
---|
587 | |
---|
588 | #define DIDR0 _SFR_MEM8(0x7E) |
---|
589 | #define ADC7D 7 |
---|
590 | #define ADC6D 6 |
---|
591 | #define ADC5D 5 |
---|
592 | #define ADC4D 4 |
---|
593 | #define ADC3D 3 |
---|
594 | #define ADC2D 2 |
---|
595 | #define ADC1D 1 |
---|
596 | #define ADC0D 0 |
---|
597 | |
---|
598 | #define DIDR1 _SFR_MEM8(0x7F) |
---|
599 | #define AIN1D 1 |
---|
600 | #define AIN0D 0 |
---|
601 | |
---|
602 | #define TCCR1A _SFR_MEM8(0x80) |
---|
603 | #define COM1A1 7 |
---|
604 | #define COM1A0 6 |
---|
605 | #define COM1B1 5 |
---|
606 | #define COM1B0 4 |
---|
607 | #define COM1C1 3 |
---|
608 | #define COM1C0 2 |
---|
609 | #define WGM11 1 |
---|
610 | #define WGM10 0 |
---|
611 | |
---|
612 | #define TCCR1B _SFR_MEM8(0x81) |
---|
613 | #define ICNC1 7 |
---|
614 | #define ICES1 6 |
---|
615 | #define WGM13 4 |
---|
616 | #define WGM12 3 |
---|
617 | #define CS12 2 |
---|
618 | #define CS11 1 |
---|
619 | #define CS10 0 |
---|
620 | |
---|
621 | #define TCCR1C _SFR_MEM8(0x82) |
---|
622 | #define FOC1A 7 |
---|
623 | #define FOC1B 6 |
---|
624 | #define FOC1C 5 |
---|
625 | |
---|
626 | /* Reserved [0x83] */ |
---|
627 | |
---|
628 | /* Combine TCNT1L and TCNT1H */ |
---|
629 | #define TCNT1 _SFR_MEM16(0x84) |
---|
630 | |
---|
631 | #define TCNT1L _SFR_MEM8(0x84) |
---|
632 | #define TCNT1H _SFR_MEM8(0x85) |
---|
633 | |
---|
634 | /* Combine ICR1L and ICR1H */ |
---|
635 | #define ICR1 _SFR_MEM16(0x86) |
---|
636 | |
---|
637 | #define ICR1L _SFR_MEM8(0x86) |
---|
638 | #define ICR1H _SFR_MEM8(0x87) |
---|
639 | |
---|
640 | /* Combine OCR1AL and OCR1AH */ |
---|
641 | #define OCR1A _SFR_MEM16(0x88) |
---|
642 | |
---|
643 | #define OCR1AL _SFR_MEM8(0x88) |
---|
644 | #define OCR1AH _SFR_MEM8(0x89) |
---|
645 | |
---|
646 | /* Combine OCR1BL and OCR1BH */ |
---|
647 | #define OCR1B _SFR_MEM16(0x8A) |
---|
648 | |
---|
649 | #define OCR1BL _SFR_MEM8(0x8A) |
---|
650 | #define OCR1BH _SFR_MEM8(0x8B) |
---|
651 | |
---|
652 | /* Combine OCR1CL and OCR1CH */ |
---|
653 | #define OCR1C _SFR_MEM16(0x8C) |
---|
654 | |
---|
655 | #define OCR1CL _SFR_MEM8(0x8C) |
---|
656 | #define OCR1CH _SFR_MEM8(0x8D) |
---|
657 | |
---|
658 | /* Reserved [0x8E..0x8F] */ |
---|
659 | |
---|
660 | #define TCCR3A _SFR_MEM8(0x90) |
---|
661 | #define COM3A1 7 |
---|
662 | #define COM3A0 6 |
---|
663 | #define COM3B1 5 |
---|
664 | #define COM3B0 4 |
---|
665 | #define COM3C1 3 |
---|
666 | #define COM3C0 2 |
---|
667 | #define WGM31 1 |
---|
668 | #define WGM30 0 |
---|
669 | |
---|
670 | #define TCCR3B _SFR_MEM8(0x91) |
---|
671 | #define ICNC3 7 |
---|
672 | #define ICES3 6 |
---|
673 | #define WGM33 4 |
---|
674 | #define WGM32 3 |
---|
675 | #define CS32 2 |
---|
676 | #define CS31 1 |
---|
677 | #define CS30 0 |
---|
678 | |
---|
679 | #define TCCR3C _SFR_MEM8(0x92) |
---|
680 | #define FOC3A 7 |
---|
681 | #define FOC3B 6 |
---|
682 | #define FOC3C 5 |
---|
683 | |
---|
684 | /* Reserved [0x93] */ |
---|
685 | |
---|
686 | /* Combine TCNT3L and TCNT3H */ |
---|
687 | #define TCNT3 _SFR_MEM16(0x94) |
---|
688 | |
---|
689 | #define TCNT3L _SFR_MEM8(0x94) |
---|
690 | #define TCNT3H _SFR_MEM8(0x95) |
---|
691 | |
---|
692 | /* Combine ICR3L and ICR3H */ |
---|
693 | #define ICR3 _SFR_MEM16(0x96) |
---|
694 | |
---|
695 | #define ICR3L _SFR_MEM8(0x96) |
---|
696 | #define ICR3H _SFR_MEM8(0x97) |
---|
697 | |
---|
698 | /* Combine OCR3AL and OCR3AH */ |
---|
699 | #define OCR3A _SFR_MEM16(0x98) |
---|
700 | |
---|
701 | #define OCR3AL _SFR_MEM8(0x98) |
---|
702 | #define OCR3AH _SFR_MEM8(0x99) |
---|
703 | |
---|
704 | /* Combine OCR3BL and OCR3BH */ |
---|
705 | #define OCR3B _SFR_MEM16(0x9A) |
---|
706 | |
---|
707 | #define OCR3BL _SFR_MEM8(0x9A) |
---|
708 | #define OCR3BH _SFR_MEM8(0x9B) |
---|
709 | |
---|
710 | /* Combine OCR3CL and OCR3CH */ |
---|
711 | #define OCR3C _SFR_MEM16(0x9C) |
---|
712 | |
---|
713 | #define OCR3CL _SFR_MEM8(0x9C) |
---|
714 | #define OCR3CH _SFR_MEM8(0x9D) |
---|
715 | |
---|
716 | #if defined(__AT90USBxx7__) |
---|
717 | |
---|
718 | #define UHCON _SFR_MEM8(0x9E) |
---|
719 | #define RESUME 2 |
---|
720 | #define RESET 1 |
---|
721 | #define SOFEN 0 |
---|
722 | |
---|
723 | #define UHINT _SFR_MEM8(0x9F) |
---|
724 | #define HWUPI 6 |
---|
725 | #define HSOFI 5 |
---|
726 | #define RXRSMI 4 |
---|
727 | #define RSMEDI 3 |
---|
728 | #define RSTI 2 |
---|
729 | #define DDISCI 1 |
---|
730 | #define DCONNI 0 |
---|
731 | |
---|
732 | #define UHIEN _SFR_MEM8(0xA0) |
---|
733 | #define HWUPE 6 |
---|
734 | #define HSOFE 5 |
---|
735 | #define RXRSME 4 |
---|
736 | #define RSMEDE 3 |
---|
737 | #define RSTE 2 |
---|
738 | #define DDISCE 1 |
---|
739 | #define DCONNE 0 |
---|
740 | |
---|
741 | #define UHADDR _SFR_MEM8(0xA1) |
---|
742 | |
---|
743 | /* Combine UHFNUML and UHFNUMH */ |
---|
744 | #define UHFNUM _SFR_MEM16(0xA2) |
---|
745 | |
---|
746 | #define UHFNUML _SFR_MEM8(0xA2) |
---|
747 | #define UHFNUMH _SFR_MEM8(0xA3) |
---|
748 | |
---|
749 | #define UHFLEN _SFR_MEM8(0xA4) |
---|
750 | |
---|
751 | #define UPINRQX _SFR_MEM8(0xA5) |
---|
752 | |
---|
753 | #define UPINTX _SFR_MEM8(0xA6) |
---|
754 | #define FIFOCON 7 |
---|
755 | #define NAKEDI 6 |
---|
756 | #define RWAL 5 |
---|
757 | #define PERRI 4 |
---|
758 | #define TXSTPI 3 |
---|
759 | #define TXOUTI 2 |
---|
760 | #define RXSTALLI 1 |
---|
761 | #define RXINI 0 |
---|
762 | |
---|
763 | #define UPNUM _SFR_MEM8(0xA7) |
---|
764 | |
---|
765 | #define UPRST _SFR_MEM8(0xA8) |
---|
766 | #define PRST6 6 |
---|
767 | #define PRST5 5 |
---|
768 | #define PRST4 4 |
---|
769 | #define PRST3 3 |
---|
770 | #define PRST2 2 |
---|
771 | #define PRST1 1 |
---|
772 | #define PRST0 0 |
---|
773 | |
---|
774 | #define UPCONX _SFR_MEM8(0xA9) |
---|
775 | #define PFREEZE 6 |
---|
776 | #define INMODE 5 |
---|
777 | /* #define AUTOSW 4 */ /* Reserved */ |
---|
778 | #define RSTDT 3 |
---|
779 | #define PEN 0 |
---|
780 | |
---|
781 | #define UPCFG0X _SFR_MEM8(0XAA) |
---|
782 | #define PTYPE1 7 |
---|
783 | #define PTYPE0 6 |
---|
784 | #define PTOKEN1 5 |
---|
785 | #define PTOKEN0 4 |
---|
786 | #define PEPNUM3 3 |
---|
787 | #define PEPNUM2 2 |
---|
788 | #define PEPNUM1 1 |
---|
789 | #define PEPNUM0 0 |
---|
790 | |
---|
791 | #define UPCFG1X _SFR_MEM8(0XAB) |
---|
792 | #define PSIZE2 6 |
---|
793 | #define PSIZE1 5 |
---|
794 | #define PSIZE0 4 |
---|
795 | #define PBK1 3 |
---|
796 | #define PBK0 2 |
---|
797 | #define ALLOC 1 |
---|
798 | |
---|
799 | #define UPSTAX _SFR_MEM8(0XAC) |
---|
800 | #define CFGOK 7 |
---|
801 | #define OVERFI 6 |
---|
802 | #define UNDERFI 5 |
---|
803 | #define DTSEQ1 3 |
---|
804 | #define DTSEQ0 2 |
---|
805 | #define NBUSYBK1 1 |
---|
806 | #define NBUSYBK0 0 |
---|
807 | |
---|
808 | #define UPCFG2X _SFR_MEM8(0XAD) |
---|
809 | |
---|
810 | #define UPIENX _SFR_MEM8(0XAE) |
---|
811 | #define FLERRE 7 |
---|
812 | #define NAKEDE 6 |
---|
813 | #define PERRE 4 |
---|
814 | #define TXSTPE 3 |
---|
815 | #define TXOUTE 2 |
---|
816 | #define RXSTALLE 1 |
---|
817 | #define RXINE 0 |
---|
818 | |
---|
819 | #define UPDATX _SFR_MEM8(0XAF) |
---|
820 | |
---|
821 | #endif /* __AT90USBxx7__ */ |
---|
822 | |
---|
823 | #define TCCR2A _SFR_MEM8(0xB0) |
---|
824 | #define COM2A1 7 |
---|
825 | #define COM2A0 6 |
---|
826 | #define COM2B1 5 |
---|
827 | #define COM2B0 4 |
---|
828 | #define WGM21 1 |
---|
829 | #define WGM20 0 |
---|
830 | |
---|
831 | #define TCCR2B _SFR_MEM8(0xB1) |
---|
832 | #define FOC2A 7 |
---|
833 | #define FOC2B 6 |
---|
834 | #define WGM22 3 |
---|
835 | #define CS22 2 |
---|
836 | #define CS21 1 |
---|
837 | #define CS20 0 |
---|
838 | |
---|
839 | #define TCNT2 _SFR_MEM8(0xB2) |
---|
840 | |
---|
841 | #define OCR2A _SFR_MEM8(0xB3) |
---|
842 | |
---|
843 | #define OCR2B _SFR_MEM8(0xB4) |
---|
844 | |
---|
845 | /* Reserved [0xB5] */ |
---|
846 | |
---|
847 | #define ASSR _SFR_MEM8(0xB6) |
---|
848 | #define EXCLK 6 |
---|
849 | #define AS2 5 |
---|
850 | #define TCN2UB 4 |
---|
851 | #define OCR2AUB 3 |
---|
852 | #define OCR2BUB 2 |
---|
853 | #define TCR2AUB 1 |
---|
854 | #define TCR2BUB 0 |
---|
855 | |
---|
856 | /* Reserved [0xB7] */ |
---|
857 | |
---|
858 | #define TWBR _SFR_MEM8(0xB8) |
---|
859 | |
---|
860 | #define TWSR _SFR_MEM8(0xB9) |
---|
861 | #define TWS7 7 |
---|
862 | #define TWS6 6 |
---|
863 | #define TWS5 5 |
---|
864 | #define TWS4 4 |
---|
865 | #define TWS3 3 |
---|
866 | #define TWPS1 1 |
---|
867 | #define TWPS0 0 |
---|
868 | |
---|
869 | #define TWAR _SFR_MEM8(0xBA) |
---|
870 | #define TWA6 7 |
---|
871 | #define TWA5 6 |
---|
872 | #define TWA4 5 |
---|
873 | #define TWA3 4 |
---|
874 | #define TWA2 3 |
---|
875 | #define TWA1 2 |
---|
876 | #define TWA0 1 |
---|
877 | #define TWGCE 0 |
---|
878 | |
---|
879 | #define TWDR _SFR_MEM8(0xBB) |
---|
880 | |
---|
881 | #define TWCR _SFR_MEM8(0xBC) |
---|
882 | #define TWINT 7 |
---|
883 | #define TWEA 6 |
---|
884 | #define TWSTA 5 |
---|
885 | #define TWSTO 4 |
---|
886 | #define TWWC 3 |
---|
887 | #define TWEN 2 |
---|
888 | #define TWIE 0 |
---|
889 | |
---|
890 | #define TWAMR _SFR_MEM8(0xBD) |
---|
891 | #define TWAM6 7 |
---|
892 | #define TWAM5 6 |
---|
893 | #define TWAM4 5 |
---|
894 | #define TWAM3 4 |
---|
895 | #define TWAM2 3 |
---|
896 | #define TWAM1 2 |
---|
897 | #define TWAM0 1 |
---|
898 | |
---|
899 | /* Reserved [0xBE..0xC7] */ |
---|
900 | |
---|
901 | #define UCSR1A _SFR_MEM8(0xC8) |
---|
902 | #define RXC1 7 |
---|
903 | #define TXC1 6 |
---|
904 | #define UDRE1 5 |
---|
905 | #define FE1 4 |
---|
906 | #define DOR1 3 |
---|
907 | #define UPE1 2 |
---|
908 | #define U2X1 1 |
---|
909 | #define MPCM1 0 |
---|
910 | |
---|
911 | #define UCSR1B _SFR_MEM8(0XC9) |
---|
912 | #define RXCIE1 7 |
---|
913 | #define TXCIE1 6 |
---|
914 | #define UDRIE1 5 |
---|
915 | #define RXEN1 4 |
---|
916 | #define TXEN1 3 |
---|
917 | #define UCSZ12 2 |
---|
918 | #define RXB81 1 |
---|
919 | #define TXB81 0 |
---|
920 | |
---|
921 | #define UCSR1C _SFR_MEM8(0xCA) |
---|
922 | #define UMSEL11 7 |
---|
923 | #define UMSEL10 6 |
---|
924 | #define UPM11 5 |
---|
925 | #define UPM10 4 |
---|
926 | #define USBS1 3 |
---|
927 | #define UCSZ11 2 |
---|
928 | #define UCSZ10 1 |
---|
929 | #define UCPOL1 0 |
---|
930 | |
---|
931 | /* Reserved [0xCB] */ |
---|
932 | |
---|
933 | /* Combine UBRR1L and UBRR1H */ |
---|
934 | #define UBRR1 _SFR_MEM16(0xCC) |
---|
935 | |
---|
936 | #define UBRR1L _SFR_MEM8(0xCC) |
---|
937 | #define UBRR1H _SFR_MEM8(0xCD) |
---|
938 | |
---|
939 | #define UDR1 _SFR_MEM8(0XCE) |
---|
940 | |
---|
941 | /* Reserved [0xCF..0xD6] */ |
---|
942 | |
---|
943 | #define UHWCON _SFR_MEM8(0XD7) |
---|
944 | #define UIMOD 7 |
---|
945 | #define UIDE 6 |
---|
946 | #define UVCONE 4 |
---|
947 | #define UVREGE 0 |
---|
948 | |
---|
949 | #define USBCON _SFR_MEM8(0XD8) |
---|
950 | #define USBE 7 |
---|
951 | #define HOST 6 |
---|
952 | #define FRZCLK 5 |
---|
953 | #define OTGPADE 4 |
---|
954 | #define IDTE 1 |
---|
955 | #define VBUSTE 0 |
---|
956 | |
---|
957 | #define USBSTA _SFR_MEM8(0XD9) |
---|
958 | #define SPEED 3 |
---|
959 | #define ID 1 |
---|
960 | #define VBUS 0 |
---|
961 | |
---|
962 | #define USBINT _SFR_MEM8(0XDA) |
---|
963 | #define IDTI 1 |
---|
964 | #define VBUSTI 0 |
---|
965 | |
---|
966 | /* Combine UDPADDL and UDPADDH */ |
---|
967 | #define UDPADD _SFR_MEM16(0xDB) |
---|
968 | |
---|
969 | #define UDPADDL _SFR_MEM8(0xDB) |
---|
970 | #define UDPADDH _SFR_MEM8(0xDC) |
---|
971 | #define DPACC 7 |
---|
972 | |
---|
973 | #if defined(__AT90USBxx7__) |
---|
974 | |
---|
975 | #define OTGCON _SFR_MEM8(0XDD) |
---|
976 | #define HNPREQ 5 |
---|
977 | #define SRPREQ 4 |
---|
978 | #define SRPSEL 3 |
---|
979 | #define VBUSHWC 2 |
---|
980 | #define VBUSREQ 1 |
---|
981 | #define VBUSRQC 0 |
---|
982 | |
---|
983 | #define OTGIEN _SFR_MEM8(0XDE) |
---|
984 | #define STOE 5 |
---|
985 | #define HNPERRE 4 |
---|
986 | #define ROLEEXE 3 |
---|
987 | #define BCERRE 2 |
---|
988 | #define VBERRE 1 |
---|
989 | #define SRPE 0 |
---|
990 | |
---|
991 | #define OTGINT _SFR_MEM8(0XDF) |
---|
992 | #define STOI 5 |
---|
993 | #define HNPERRI 4 |
---|
994 | #define ROLEEXI 3 |
---|
995 | #define BCERRI 2 |
---|
996 | #define VBERRI 1 |
---|
997 | #define SRPI 0 |
---|
998 | |
---|
999 | #endif /* __AT90USBxx7__ */ |
---|
1000 | |
---|
1001 | #define UDCON _SFR_MEM8(0XE0) |
---|
1002 | #define LSM 2 |
---|
1003 | #define RMWKUP 1 |
---|
1004 | #define DETACH 0 |
---|
1005 | |
---|
1006 | #define UDINT _SFR_MEM8(0XE1) |
---|
1007 | #define UPRSMI 6 |
---|
1008 | #define EORSMI 5 |
---|
1009 | #define WAKEUPI 4 |
---|
1010 | #define EORSTI 3 |
---|
1011 | #define SOFI 2 |
---|
1012 | /* #define MSOFI 1 */ /* Reserved */ |
---|
1013 | #define SUSPI 0 |
---|
1014 | |
---|
1015 | #define UDIEN _SFR_MEM8(0XE2) |
---|
1016 | #define UPRSME 6 |
---|
1017 | #define EORSME 5 |
---|
1018 | #define WAKEUPE 4 |
---|
1019 | #define EORSTE 3 |
---|
1020 | #define SOFE 2 |
---|
1021 | /* #define MSOFE 1 */ /* Reserved */ |
---|
1022 | #define SUSPE 0 |
---|
1023 | |
---|
1024 | #define UDADDR _SFR_MEM8(0XE3) |
---|
1025 | #define ADDEN 7 |
---|
1026 | |
---|
1027 | /* Combine UDFNUML and UDFNUMH */ |
---|
1028 | #define UDFNUM _SFR_MEM16(0xE4) |
---|
1029 | |
---|
1030 | #define UDFNUML _SFR_MEM8(0xE4) |
---|
1031 | #define UDFNUMH _SFR_MEM8(0xE5) |
---|
1032 | |
---|
1033 | #define UDMFN _SFR_MEM8(0XE6) |
---|
1034 | #define FNCERR 4 |
---|
1035 | |
---|
1036 | #define UDTST _SFR_MEM8(0XE7) |
---|
1037 | #define OPMODE2 5 |
---|
1038 | #define TSTPCKT 4 |
---|
1039 | #define TSTK 3 |
---|
1040 | #define TSTJ 2 |
---|
1041 | |
---|
1042 | #define UEINTX _SFR_MEM8(0XE8) |
---|
1043 | #define FIFOCON 7 |
---|
1044 | #define NAKINI 6 |
---|
1045 | #define RWAL 5 |
---|
1046 | #define NAKOUTI 4 |
---|
1047 | #define RXSTPI 3 |
---|
1048 | #define RXOUTI 2 |
---|
1049 | #define STALLEDI 1 |
---|
1050 | #define TXINI 0 |
---|
1051 | |
---|
1052 | #define UENUM _SFR_MEM8(0XE9) |
---|
1053 | |
---|
1054 | #define UERST _SFR_MEM8(0XEA) |
---|
1055 | #define EPRST6 6 |
---|
1056 | #define EPRST5 5 |
---|
1057 | #define EPRST4 4 |
---|
1058 | #define EPRST3 3 |
---|
1059 | #define EPRST2 2 |
---|
1060 | #define EPRST1 1 |
---|
1061 | #define EPRST0 0 |
---|
1062 | |
---|
1063 | #define UECONX _SFR_MEM8(0XEB) |
---|
1064 | #define STALLRQ 5 |
---|
1065 | #define STALLRQC 4 |
---|
1066 | #define RSTDT 3 |
---|
1067 | #define EPEN 0 |
---|
1068 | |
---|
1069 | #define UECFG0X _SFR_MEM8(0XEC) |
---|
1070 | #define EPTYPE1 7 |
---|
1071 | #define EPTYPE0 6 |
---|
1072 | /* #define ISOSW 3 */ /* Reserved */ |
---|
1073 | /* #define AUTOSW 2 */ /* Reserved */ |
---|
1074 | /* #define NYETSDIS 1 */ /* Reserved */ |
---|
1075 | #define EPDIR 0 |
---|
1076 | |
---|
1077 | #define UECFG1X _SFR_MEM8(0XED) |
---|
1078 | #define EPSIZE2 6 |
---|
1079 | #define EPSIZE1 5 |
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1080 | #define EPSIZE0 4 |
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1081 | #define EPBK1 3 |
---|
1082 | #define EPBK0 2 |
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1083 | #define ALLOC 1 |
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1084 | |
---|
1085 | #define UESTA0X _SFR_MEM8(0XEE) |
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1086 | #define CFGOK 7 |
---|
1087 | #define OVERFI 6 |
---|
1088 | #define UNDERFI 5 |
---|
1089 | #define ZLPSEEN 4 |
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1090 | #define DTSEQ1 3 |
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1091 | #define DTSEQ0 2 |
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1092 | #define NBUSYBK1 1 |
---|
1093 | #define NBUSYBK0 0 |
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1094 | |
---|
1095 | #define UESTA1X _SFR_MEM8(0XEF) |
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1096 | #define CTRLDIR 2 |
---|
1097 | #define CURRBK1 1 |
---|
1098 | #define CURRBK0 0 |
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1099 | |
---|
1100 | #define UEIENX _SFR_MEM8(0XF0) |
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1101 | #define FLERRE 7 |
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1102 | #define NAKINE 6 |
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1103 | #define NAKOUTE 4 |
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1104 | #define RXSTPE 3 |
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1105 | #define RXOUTE 2 |
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1106 | #define STALLEDE 1 |
---|
1107 | #define TXINE 0 |
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1108 | |
---|
1109 | #define UEDATX _SFR_MEM8(0XF1) |
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1110 | |
---|
1111 | /* Combine UEBCLX and UEBCHX */ |
---|
1112 | #define UEBCX _SFR_MEM16(0xF2) |
---|
1113 | |
---|
1114 | #define UEBCLX _SFR_MEM8(0xF2) |
---|
1115 | #define UEBCHX _SFR_MEM8(0xF3) |
---|
1116 | |
---|
1117 | #define UEINT _SFR_MEM8(0XF4) |
---|
1118 | #define EPINT6 6 |
---|
1119 | #define EPINT5 5 |
---|
1120 | #define EPINT4 4 |
---|
1121 | #define EPINT3 3 |
---|
1122 | #define EPINT2 2 |
---|
1123 | #define EPINT1 1 |
---|
1124 | #define EPINT0 0 |
---|
1125 | |
---|
1126 | #if defined(__AT90USBxx7__) |
---|
1127 | |
---|
1128 | #define UPERRX _SFR_MEM8(0XF5) |
---|
1129 | #define COUNTER1 6 |
---|
1130 | #define COUNTER0 5 |
---|
1131 | #define CRC16 4 |
---|
1132 | #define TIMEOUT 3 |
---|
1133 | #define PID 2 |
---|
1134 | #define DATAPID 1 |
---|
1135 | #define DATATGL 0 |
---|
1136 | |
---|
1137 | /* Combine UPBCLX and UPBCHX */ |
---|
1138 | #define UPBCX _SFR_MEM16(0xF6) |
---|
1139 | |
---|
1140 | #define UPBCLX _SFR_MEM8(0xF6) |
---|
1141 | #define UPBCHX _SFR_MEM8(0xF7) |
---|
1142 | |
---|
1143 | #define UPINT _SFR_MEM8(0XF8) |
---|
1144 | #define PINT6 6 |
---|
1145 | #define PINT5 5 |
---|
1146 | #define PINT4 4 |
---|
1147 | #define PINT3 3 |
---|
1148 | #define PINT2 2 |
---|
1149 | #define PINT1 1 |
---|
1150 | #define PINT0 0 |
---|
1151 | |
---|
1152 | #define OTGTCON _SFR_MEM8(0XF9) |
---|
1153 | #define PAGE1 6 |
---|
1154 | #define PAGE0 5 |
---|
1155 | #define VALUE1 1 |
---|
1156 | #define VALUE0 0 |
---|
1157 | |
---|
1158 | #endif /* __AT90USBxx7__ */ |
---|
1159 | |
---|
1160 | /* Reserved [0xFA..0xFF] */ |
---|
1161 | |
---|
1162 | /* Interrupt vectors */ |
---|
1163 | |
---|
1164 | /* External Interrupt Request 0 */ |
---|
1165 | #define INT0_vect _VECTOR(1) |
---|
1166 | |
---|
1167 | /* External Interrupt Request 1 */ |
---|
1168 | #define INT1_vect _VECTOR(2) |
---|
1169 | |
---|
1170 | /* External Interrupt Request 2 */ |
---|
1171 | #define INT2_vect _VECTOR(3) |
---|
1172 | |
---|
1173 | /* External Interrupt Request 3 */ |
---|
1174 | #define INT3_vect _VECTOR(4) |
---|
1175 | |
---|
1176 | /* External Interrupt Request 4 */ |
---|
1177 | #define INT4_vect _VECTOR(5) |
---|
1178 | |
---|
1179 | /* External Interrupt Request 5 */ |
---|
1180 | #define INT5_vect _VECTOR(6) |
---|
1181 | |
---|
1182 | /* External Interrupt Request 6 */ |
---|
1183 | #define INT6_vect _VECTOR(7) |
---|
1184 | |
---|
1185 | /* External Interrupt Request 7 */ |
---|
1186 | #define INT7_vect _VECTOR(8) |
---|
1187 | |
---|
1188 | /* Pin Change Interrupt Request 0 */ |
---|
1189 | #define PCINT0_vect _VECTOR(9) |
---|
1190 | |
---|
1191 | /* USB General Interrupt Request */ |
---|
1192 | #define USB_GEN_vect _VECTOR(10) |
---|
1193 | |
---|
1194 | /* USB Endpoint/Pipe Interrupt Communication Request */ |
---|
1195 | #define USB_COM_vect _VECTOR(11) |
---|
1196 | |
---|
1197 | /* Watchdog Time-out Interrupt */ |
---|
1198 | #define WDT_vect _VECTOR(12) |
---|
1199 | |
---|
1200 | /* Timer/Counter2 Compare Match A */ |
---|
1201 | #define TIMER2_COMPA_vect _VECTOR(13) |
---|
1202 | |
---|
1203 | /* Timer/Counter2 Compare Match B */ |
---|
1204 | #define TIMER2_COMPB_vect _VECTOR(14) |
---|
1205 | |
---|
1206 | /* Timer/Counter2 Overflow */ |
---|
1207 | #define TIMER2_OVF_vect _VECTOR(15) |
---|
1208 | |
---|
1209 | /* Timer/Counter1 Capture Event */ |
---|
1210 | #define TIMER1_CAPT_vect _VECTOR(16) |
---|
1211 | |
---|
1212 | /* Timer/Counter1 Compare Match A */ |
---|
1213 | #define TIMER1_COMPA_vect _VECTOR(17) |
---|
1214 | |
---|
1215 | /* Timer/Counter1 Compare Match B */ |
---|
1216 | #define TIMER1_COMPB_vect _VECTOR(18) |
---|
1217 | |
---|
1218 | /* Timer/Counter1 Compare Match C */ |
---|
1219 | #define TIMER1_COMPC_vect _VECTOR(19) |
---|
1220 | |
---|
1221 | /* Timer/Counter1 Overflow */ |
---|
1222 | #define TIMER1_OVF_vect _VECTOR(20) |
---|
1223 | |
---|
1224 | /* Timer/Counter0 Compare Match A */ |
---|
1225 | #define TIMER0_COMPA_vect _VECTOR(21) |
---|
1226 | |
---|
1227 | /* Timer/Counter0 Compare Match B */ |
---|
1228 | #define TIMER0_COMPB_vect _VECTOR(22) |
---|
1229 | |
---|
1230 | /* Timer/Counter0 Overflow */ |
---|
1231 | #define TIMER0_OVF_vect _VECTOR(23) |
---|
1232 | |
---|
1233 | /* SPI Serial Transfer Complete */ |
---|
1234 | #define SPI_STC_vect _VECTOR(24) |
---|
1235 | |
---|
1236 | /* USART1, Rx Complete */ |
---|
1237 | #define USART1_RX_vect _VECTOR(25) |
---|
1238 | |
---|
1239 | /* USART1 Data register Empty */ |
---|
1240 | #define USART1_UDRE_vect _VECTOR(26) |
---|
1241 | |
---|
1242 | /* USART1, Tx Complete */ |
---|
1243 | #define USART1_TX_vect _VECTOR(27) |
---|
1244 | |
---|
1245 | /* Analog Comparator */ |
---|
1246 | #define ANALOG_COMP_vect _VECTOR(28) |
---|
1247 | |
---|
1248 | /* ADC Conversion Complete */ |
---|
1249 | #define ADC_vect _VECTOR(29) |
---|
1250 | |
---|
1251 | /* EEPROM Ready */ |
---|
1252 | #define EE_READY_vect _VECTOR(30) |
---|
1253 | |
---|
1254 | /* Timer/Counter3 Capture Event */ |
---|
1255 | #define TIMER3_CAPT_vect _VECTOR(31) |
---|
1256 | |
---|
1257 | /* Timer/Counter3 Compare Match A */ |
---|
1258 | #define TIMER3_COMPA_vect _VECTOR(32) |
---|
1259 | |
---|
1260 | /* Timer/Counter3 Compare Match B */ |
---|
1261 | #define TIMER3_COMPB_vect _VECTOR(33) |
---|
1262 | |
---|
1263 | /* Timer/Counter3 Compare Match C */ |
---|
1264 | #define TIMER3_COMPC_vect _VECTOR(34) |
---|
1265 | |
---|
1266 | /* Timer/Counter3 Overflow */ |
---|
1267 | #define TIMER3_OVF_vect _VECTOR(35) |
---|
1268 | |
---|
1269 | /* 2-wire Serial Interface */ |
---|
1270 | #define TWI_vect _VECTOR(36) |
---|
1271 | |
---|
1272 | /* Store Program Memory Read */ |
---|
1273 | #define SPM_READY_vect _VECTOR(37) |
---|
1274 | |
---|
1275 | #define _VECTORS_SIZE 152 |
---|
1276 | |
---|
1277 | #if defined(__AT90USBxx6__) |
---|
1278 | # undef __AT90USBxx6__ |
---|
1279 | #endif /* __AT90USBxx6__ */ |
---|
1280 | |
---|
1281 | #if defined(__AT90USBxx7__) |
---|
1282 | # undef __AT90USBxx7__ |
---|
1283 | #endif /* __AT90USBxx7__ */ |
---|
1284 | |
---|
1285 | #endif /* _AVR_IOUSBXX6_7_H_ */ |
---|