source: rtems/cpukit/score/cpu/avr/avr/iousbxx6_7.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 24.3 KB
Line 
1/* Copyright (c) 2006, Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286
34   and AT90USB1287 */
35
36#ifndef _AVR_IOUSBXX6_7_H_
37#define _AVR_IOUSBXX6_7_H_ 1
38
39/* This file should only be included from <avr/io.h>, never directly. */
40
41#ifndef _AVR_IO_H_
42#  error "Include <avr/io.h> instead of this file."
43#endif
44
45#ifndef _AVR_IOXXX_H_
46#  define _AVR_IOXXX_H_ "iousbxx6_7.h"
47#else
48#  error "Attempt to include more than one <avr/ioXXX.h> file."
49#endif
50
51#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
52#  define __AT90USBxx6__ 1
53#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__)
54#  define __AT90USBxx7__ 1
55#endif
56
57/* Registers and associated bit numbers */
58
59#define PINA    _SFR_IO8(0X00)
60#define PINA7   7
61#define PINA6   6
62#define PINA5   5
63#define PINA4   4
64#define PINA3   3
65#define PINA2   2
66#define PINA1   1
67#define PINA0   0
68
69#define DDRA    _SFR_IO8(0X01)
70#define DDA7    7
71#define DDA6    6
72#define DDA5    5
73#define DDA4    4
74#define DDA3    3
75#define DDA2    2
76#define DDA1    1
77#define DDA0    0
78
79#define PORTA   _SFR_IO8(0X02)
80#define PA7  7
81#define PA6  6
82#define PA5  5
83#define PA4  4
84#define PA3  3
85#define PA2  2
86#define PA1  1
87#define PA0  0
88
89#define PINB    _SFR_IO8(0X03)
90#define PINB7   7
91#define PINB6   6
92#define PINB5   5
93#define PINB4   4
94#define PINB3   3
95#define PINB2   2
96#define PINB1   1
97#define PINB0   0
98
99#define DDRB    _SFR_IO8(0x04)
100#define DDB7    7
101#define DDB6    6
102#define DDB5    5
103#define DDB4    4
104#define DDB3    3
105#define DDB2    2
106#define DDB1    1
107#define DDB0    0
108
109#define PORTB   _SFR_IO8(0x05)
110#define PB7  7
111#define PB6  6
112#define PB5  5
113#define PB4  4
114#define PB3  3
115#define PB2  2
116#define PB1  1
117#define PB0  0
118
119#define PINC    _SFR_IO8(0x06)
120#define PINC7   7
121#define PINC6   6
122#define PINC5   5
123#define PINC4   4
124#define PINC3   3
125#define PINC2   2
126#define PINC1   1
127#define PINC0   0
128
129#define DDRC    _SFR_IO8(0x07)
130#define DDC7    7
131#define DDC6    6
132#define DDC5    5
133#define DDC4    4
134#define DDC3    3
135#define DDC2    2
136#define DDC1    1
137#define DDC0    0
138
139#define PORTC   _SFR_IO8(0x08)
140#define PC7  7
141#define PC6  6
142#define PC5  5
143#define PC4  4
144#define PC3  3
145#define PC2  2
146#define PC1  1
147#define PC0  0
148
149#define PIND    _SFR_IO8(0x09)
150#define PIND7   7
151#define PIND6   6
152#define PIND5   5
153#define PIND4   4
154#define PIND3   3
155#define PIND2   2
156#define PIND1   1
157#define PIND0   0
158
159#define DDRD    _SFR_IO8(0x0A)
160#define DDD7    7
161#define DDD6    6
162#define DDD5    5
163#define DDD4    4
164#define DDD3    3
165#define DDD2    2
166#define DDD1    1
167#define DDD0    0
168
169#define PORTD   _SFR_IO8(0x0B)
170#define PD7  7
171#define PD6  6
172#define PD5  5
173#define PD4  4
174#define PD3  3
175#define PD2  2
176#define PD1  1
177#define PD0  0
178
179#define PINE    _SFR_IO8(0x0C)
180#define PINE7   7
181#define PINE6   6
182#define PINE5   5
183#define PINE4   4
184#define PINE3   3
185#define PINE2   2
186#define PINE1   1
187#define PINE0   0
188
189#define DDRE    _SFR_IO8(0x0D)
190#define DDE7    7
191#define DDE6    6
192#define DDE5    5
193#define DDE4    4
194#define DDE3    3
195#define DDE2    2
196#define DDE1    1
197#define DDE0    0
198
199#define PORTE   _SFR_IO8(0x0E)
200#define PE7  7
201#define PE6  6
202#define PE5  5
203#define PE4  4
204#define PE3  3
205#define PE2  2
206#define PE1  1
207#define PE0  0
208
209#define PINF    _SFR_IO8(0x0F)
210#define PINF7   7
211#define PINF6   6
212#define PINF5   5
213#define PINF4   4
214#define PINF3   3
215#define PINF2   2
216#define PINF1   1
217#define PINF0   0
218
219#define DDRF    _SFR_IO8(0x10)
220#define DDF7    7
221#define DDF6    6
222#define DDF5    5
223#define DDF4    4
224#define DDF3    3
225#define DDF2    2
226#define DDF1    1
227#define DDF0    0
228
229#define PORTF   _SFR_IO8(0x11)
230#define PF7  7
231#define PF6  6
232#define PF5  5
233#define PF4  4
234#define PF3  3
235#define PF2  2
236#define PF1  1
237#define PF0  0
238
239/* Reserved [0x12..0x14] */
240
241#define TIFR0   _SFR_IO8(0x15)
242#define OCF0B   2
243#define OCF0A   1
244#define TOV0    0
245
246#define TIFR1   _SFR_IO8(0x16)
247#define ICF1    5
248#define OCF1C   3
249#define OCF1B   2
250#define OCF1A   1
251#define TOV1    0
252
253#define TIFR2   _SFR_IO8(0x17)
254#define OCF2B   2
255#define OCF2A   1
256#define TOV2    0
257
258#define TIFR3   _SFR_IO8(0x18)
259#define ICF3    5
260#define OCF3C   3
261#define OCF3B   2
262#define OCF3A   1
263#define TOV3    0
264
265/* Reserved [0x19..0x1A] */
266
267#define PCIFR   _SFR_IO8(0x1B)
268#define PCIF0   0
269
270#define EIFR    _SFR_IO8(0x1C)
271#define INTF7   7
272#define INTF6   6
273#define INTF5   5
274#define INTF4   4
275#define INTF3   3
276#define INTF2   2
277#define INTF1   1
278#define INTF0   0
279
280#define EIMSK   _SFR_IO8(0x1D)
281#define INT7    7
282#define INT6    6
283#define INT5    5
284#define INT4    4
285#define INT3    3
286#define INT2    2
287#define INT1    1
288#define INT0    0
289
290#define GPIOR0  _SFR_IO8(0x1E)
291
292#define EECR    _SFR_IO8(0x1F)
293#define EEPM1   5
294#define EEPM0   4
295#define EERIE   3
296#define EEMPE   2
297#define EEPE    1
298#define EERE    0
299
300#define EEDR    _SFR_IO8(0x20)
301
302#define EEAR    _SFR_IO16(0x21)
303#define EEARL   _SFR_IO8(0x21)
304#define EEARH   _SFR_IO8(0x22)
305
306/* 6-char sequence denoting where to find the EEPROM registers in memory space.
307   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
308   subroutines.
309   First two letters:  EECR address.
310   Second two letters: EEDR address.
311   Last two letters:   EEAR address.  */
312#define __EEPROM_REG_LOCATIONS__ 1F2021
313
314#define GTCCR   _SFR_IO8(0x23)
315#define TSM     7
316#define PSRASY  1
317#define PSRSYNC 0
318
319#define TCCR0A  _SFR_IO8(0x24)
320#define COM0A1  7
321#define COM0A0  6
322#define COM0B1  5
323#define COM0B0  4
324#define WGM01   1
325#define WGM00   0
326
327#define TCCR0B  _SFR_IO8(0x25)
328#define FOC0A   7
329#define FOC0B   6
330#define WGM02   3
331#define CS02    2
332#define CS01    1
333#define CS00    0
334
335#define TCNT0   _SFR_IO8(0X26)
336
337#define OCR0A   _SFR_IO8(0x27)
338
339#define OCR0B   _SFR_IO8(0X28)
340
341#define PLLCSR  _SFR_IO8(0x29)
342#define PLLP2   4
343#define PLLP1   3
344#define PLLP0   2
345#define PLLE    1
346#define PLOCK   0
347
348#define GPIOR1  _SFR_IO8(0x2A)
349
350#define GPIOR2  _SFR_IO8(0x2B)
351
352#define SPCR    _SFR_IO8(0x2C)
353#define SPIE    7
354#define SPE     6
355#define DORD    5
356#define MSTR    4
357#define CPOL    3
358#define CPHA    2
359#define SPR1    1
360#define SPR0    0
361
362#define SPSR    _SFR_IO8(0x2D)
363#define SPIF    7
364#define WCOL    6
365#define SPI2X   0
366
367#define SPDR    _SFR_IO8(0x2E)
368
369/* Reserved [0x2F] */
370
371#define ACSR    _SFR_IO8(0x30)
372#define ACD     7
373#define ACBG    6
374#define ACO     5
375#define ACI     4
376#define ACIE    3
377#define ACIC    2
378#define ACIS1   1
379#define ACIS0   0
380
381#define MONDR   _SFR_IO8(0x31)
382#define OCDR    _SFR_IO8(0x31)
383#define IDRD    7
384#define OCDR7   7
385#define OCDR6   6
386#define OCDR5   5
387#define OCDR4   4
388#define OCDR3   3
389#define OCDR2   2
390#define OCDR1   1
391#define OCDR0   0
392
393/* Reserved [0x32] */
394
395#define SMCR    _SFR_IO8(0x33)
396#define SM2     3
397#define SM1     2
398#define SM0     1
399#define SE      0
400
401#define MCUSR   _SFR_IO8(0x34)
402#define JTRF    4
403#define WDRF    3
404#define BORF    2
405#define EXTRF   1
406#define PORF    0
407
408#define MCUCR   _SFR_IO8(0x35)
409#define JTD     7
410#define PUD     4
411#define IVSEL   1
412#define IVCE    0
413
414/* Reserved [0x36] */
415
416#define SPMCSR  _SFR_IO8(0x37)
417#define SPMIE   7
418#define RWWSB   6
419#define SIGRD   5
420#define RWWSRE  4
421#define BLBSET  3
422#define PGWRT   2
423#define PGERS   1
424#define SPMEN   0
425
426/* Reserved [0x38..0x3A] */
427
428#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__)
429#define RAMPZ   _SFR_IO8(0x3B)
430#endif
431
432/* Reserved [0x3C] */
433
434/* SP [0x3D..0x3E] */
435/* SREG [0x3F] */
436
437#define WDTCSR  _SFR_MEM8(0x60)
438#define WDIF    7
439#define WDIE    6
440#define WDP3    5
441#define WDCE    4
442#define WDE     3
443#define WDP2    2
444#define WDP1    1
445#define WDP0    0
446
447#define CLKPR   _SFR_MEM8(0x61)
448#define CLKPCE  7
449#define CLKPS3  3
450#define CLKPS2  2
451#define CLKPS1  1
452#define CLKPS0  0
453
454/* Reserved [0x62..0x63] */
455
456#define PRR0    _SFR_MEM8(0x64)
457#define PRTWI   7
458#define PRTIM2  6
459#define PRTIM0  5
460#define PRTIM1  3
461#define PRSPI   2
462#define PRADC   0
463
464#define PRR1    _SFR_MEM8(0x65)
465#define PRUSB   7
466#define PRTIM3  3
467#define PRUSART1 0
468
469#define OSCCAL  _SFR_MEM8(0x66)
470
471/* Reserved [0x67] */
472
473#define PCICR   _SFR_MEM8(0x68)
474#define PCIE0   0
475
476#define EICRA   _SFR_MEM8(0x69)
477#define ISC31   7
478#define ISC30   6
479#define ISC21   5
480#define ISC20   4
481#define ISC11   3
482#define ISC10   2
483#define ISC01   1
484#define ISC00   0
485
486#define EICRB   _SFR_MEM8(0x6A)
487#define ISC71   7
488#define ISC70   6
489#define ISC61   5
490#define ISC60   4
491#define ISC51   3
492#define ISC50   2
493#define ISC41   1
494#define ISC40   0
495
496#define PCMSK0  _SFR_MEM8(0x6B)
497#define PCINT7  7
498#define PCINT6  6
499#define PCINT5  5
500#define PCINT4  4
501#define PCINT3  3
502#define PCINT2  2
503#define PCINT1  1
504#define PCINT0  0
505
506/* Reserved [0x6C..0x6D] */
507
508#define TIMSK0  _SFR_MEM8(0x6E)
509#define OCIE0B  2
510#define OCIE0A  1
511#define TOIE0   0
512
513#define TIMSK1  _SFR_MEM8(0x6F)
514#define ICIE1   5
515#define OCIE1C  3
516#define OCIE1B  2
517#define OCIE1A  1
518#define TOIE1   0
519
520#define TIMSK2  _SFR_MEM8(0x70)
521#define OCIE2B  2
522#define OCIE2A  1
523#define TOIE2   0
524
525#define TIMSK3  _SFR_MEM8(0x71)
526#define ICIE3   5
527#define OCIE3C  3
528#define OCIE3B  2
529#define OCIE3A  1
530#define TOIE3   0
531
532/* Reserved [0x72..0x73] */
533
534#define XMCRA   _SFR_MEM8(0x74)
535#define SRE     7
536#define SRL2    6
537#define SRL1    5
538#define SRL0    4
539#define SRW11   3
540#define SRW10   2
541#define SRW01   1
542#define SRW00   0
543
544#define XMCRB   _SFR_MEM8(0x75)
545#define XMBK    7
546#define XMM2    2
547#define XMM1    1
548#define XMM0    0
549
550/* Reserved [0x76..0x77] */
551
552/* RegDef:  ADC Data Register */
553#ifndef __ASSEMBLER__
554#define ADC    _SFR_MEM16(0x78)
555#endif
556#define ADCW   _SFR_MEM16(0x78)
557#define ADCL   _SFR_MEM8(0x78)
558#define ADCH   _SFR_MEM8(0x79)
559
560#define ADCSRA  _SFR_MEM8(0x7A)
561#define ADEN    7
562#define ADSC    6
563#define ADATE   5
564#define ADIF    4
565#define ADIE    3
566#define ADPS2   2
567#define ADPS1   1
568#define ADPS0   0
569
570#define ADCSRB  _SFR_MEM8(0x7B)
571#define ACME    6
572#define ADTS2   2
573#define ADTS1   1
574#define ADTS0   0
575
576#define ADMUX   _SFR_MEM8(0x7C)
577#define REFS1   7
578#define REFS0   6
579#define ADLAR   5
580#define MUX4    4
581#define MUX3    3
582#define MUX2    2
583#define MUX1    1
584#define MUX0    0
585
586/* Reserved [0x7D] */
587
588#define DIDR0   _SFR_MEM8(0x7E)
589#define ADC7D   7
590#define ADC6D   6
591#define ADC5D   5
592#define ADC4D   4
593#define ADC3D   3
594#define ADC2D   2
595#define ADC1D   1
596#define ADC0D   0
597
598#define DIDR1   _SFR_MEM8(0x7F)
599#define AIN1D   1
600#define AIN0D   0
601
602#define TCCR1A  _SFR_MEM8(0x80)
603#define COM1A1  7
604#define COM1A0  6
605#define COM1B1  5
606#define COM1B0  4
607#define COM1C1  3
608#define COM1C0  2
609#define WGM11   1
610#define WGM10   0
611
612#define TCCR1B  _SFR_MEM8(0x81)
613#define ICNC1   7
614#define ICES1   6
615#define WGM13   4
616#define WGM12   3
617#define CS12    2
618#define CS11    1
619#define CS10    0
620
621#define TCCR1C  _SFR_MEM8(0x82)
622#define FOC1A   7
623#define FOC1B   6
624#define FOC1C   5
625
626/* Reserved [0x83] */
627
628/* Combine TCNT1L and TCNT1H */
629#define TCNT1   _SFR_MEM16(0x84)
630
631#define TCNT1L  _SFR_MEM8(0x84)
632#define TCNT1H  _SFR_MEM8(0x85)
633
634/* Combine ICR1L and ICR1H */
635#define ICR1    _SFR_MEM16(0x86)
636
637#define ICR1L   _SFR_MEM8(0x86)
638#define ICR1H   _SFR_MEM8(0x87)
639
640/* Combine OCR1AL and OCR1AH */
641#define OCR1A   _SFR_MEM16(0x88)
642
643#define OCR1AL  _SFR_MEM8(0x88)
644#define OCR1AH  _SFR_MEM8(0x89)
645
646/* Combine OCR1BL and OCR1BH */
647#define OCR1B   _SFR_MEM16(0x8A)
648
649#define OCR1BL  _SFR_MEM8(0x8A)
650#define OCR1BH  _SFR_MEM8(0x8B)
651
652/* Combine OCR1CL and OCR1CH */
653#define OCR1C   _SFR_MEM16(0x8C)
654
655#define OCR1CL  _SFR_MEM8(0x8C)
656#define OCR1CH  _SFR_MEM8(0x8D)
657
658/* Reserved [0x8E..0x8F] */
659
660#define TCCR3A  _SFR_MEM8(0x90)
661#define COM3A1  7
662#define COM3A0  6
663#define COM3B1  5
664#define COM3B0  4
665#define COM3C1  3
666#define COM3C0  2
667#define WGM31   1
668#define WGM30   0
669
670#define TCCR3B  _SFR_MEM8(0x91)
671#define ICNC3   7
672#define ICES3   6
673#define WGM33   4
674#define WGM32   3
675#define CS32    2
676#define CS31    1
677#define CS30    0
678
679#define TCCR3C  _SFR_MEM8(0x92)
680#define FOC3A   7
681#define FOC3B   6
682#define FOC3C   5
683
684/* Reserved [0x93] */
685
686/* Combine TCNT3L and TCNT3H */
687#define TCNT3   _SFR_MEM16(0x94)
688
689#define TCNT3L  _SFR_MEM8(0x94)
690#define TCNT3H  _SFR_MEM8(0x95)
691
692/* Combine ICR3L and ICR3H */
693#define ICR3    _SFR_MEM16(0x96)
694
695#define ICR3L   _SFR_MEM8(0x96)
696#define ICR3H   _SFR_MEM8(0x97)
697
698/* Combine OCR3AL and OCR3AH */
699#define OCR3A   _SFR_MEM16(0x98)
700
701#define OCR3AL  _SFR_MEM8(0x98)
702#define OCR3AH  _SFR_MEM8(0x99)
703
704/* Combine OCR3BL and OCR3BH */
705#define OCR3B   _SFR_MEM16(0x9A)
706
707#define OCR3BL  _SFR_MEM8(0x9A)
708#define OCR3BH  _SFR_MEM8(0x9B)
709
710/* Combine OCR3CL and OCR3CH */
711#define OCR3C   _SFR_MEM16(0x9C)
712
713#define OCR3CL  _SFR_MEM8(0x9C)
714#define OCR3CH  _SFR_MEM8(0x9D)
715
716#if defined(__AT90USBxx7__)
717
718#define UHCON   _SFR_MEM8(0x9E)
719#define RESUME  2
720#define RESET   1
721#define SOFEN   0
722
723#define UHINT   _SFR_MEM8(0x9F)
724#define HWUPI   6
725#define HSOFI   5
726#define RXRSMI  4
727#define RSMEDI  3
728#define RSTI    2
729#define DDISCI  1
730#define DCONNI  0
731
732#define UHIEN   _SFR_MEM8(0xA0)
733#define HWUPE   6
734#define HSOFE   5
735#define RXRSME  4
736#define RSMEDE  3
737#define RSTE    2
738#define DDISCE  1
739#define DCONNE  0
740
741#define UHADDR  _SFR_MEM8(0xA1)
742
743/* Combine UHFNUML and UHFNUMH */
744#define UHFNUM  _SFR_MEM16(0xA2)
745
746#define UHFNUML _SFR_MEM8(0xA2)
747#define UHFNUMH _SFR_MEM8(0xA3)
748
749#define UHFLEN  _SFR_MEM8(0xA4)
750
751#define UPINRQX _SFR_MEM8(0xA5)
752
753#define UPINTX  _SFR_MEM8(0xA6)
754#define FIFOCON 7
755#define NAKEDI  6
756#define RWAL    5
757#define PERRI   4
758#define TXSTPI  3
759#define TXOUTI  2
760#define RXSTALLI 1
761#define RXINI   0
762
763#define UPNUM   _SFR_MEM8(0xA7)
764
765#define UPRST   _SFR_MEM8(0xA8)
766#define PRST6   6
767#define PRST5   5
768#define PRST4   4
769#define PRST3   3
770#define PRST2   2
771#define PRST1   1
772#define PRST0   0
773
774#define UPCONX  _SFR_MEM8(0xA9)
775#define PFREEZE 6
776#define INMODE  5
777/* #define AUTOSW  4 */ /* Reserved */
778#define RSTDT   3
779#define PEN     0
780
781#define UPCFG0X _SFR_MEM8(0XAA)
782#define PTYPE1  7
783#define PTYPE0  6
784#define PTOKEN1 5
785#define PTOKEN0 4
786#define PEPNUM3 3
787#define PEPNUM2 2
788#define PEPNUM1 1
789#define PEPNUM0 0
790
791#define UPCFG1X _SFR_MEM8(0XAB)
792#define PSIZE2  6
793#define PSIZE1  5
794#define PSIZE0  4
795#define PBK1    3
796#define PBK0    2
797#define ALLOC   1
798
799#define UPSTAX  _SFR_MEM8(0XAC)
800#define CFGOK   7
801#define OVERFI  6
802#define UNDERFI 5
803#define DTSEQ1  3
804#define DTSEQ0  2
805#define NBUSYBK1 1
806#define NBUSYBK0 0
807
808#define UPCFG2X _SFR_MEM8(0XAD)
809
810#define UPIENX  _SFR_MEM8(0XAE)
811#define FLERRE  7
812#define NAKEDE  6
813#define PERRE   4
814#define TXSTPE  3
815#define TXOUTE  2
816#define RXSTALLE 1
817#define RXINE   0
818
819#define UPDATX  _SFR_MEM8(0XAF)
820
821#endif /* __AT90USBxx7__ */
822
823#define TCCR2A  _SFR_MEM8(0xB0)
824#define COM2A1  7
825#define COM2A0  6
826#define COM2B1  5
827#define COM2B0  4
828#define WGM21   1
829#define WGM20   0
830
831#define TCCR2B  _SFR_MEM8(0xB1)
832#define FOC2A   7
833#define FOC2B   6
834#define WGM22   3
835#define CS22    2
836#define CS21    1
837#define CS20    0
838
839#define TCNT2   _SFR_MEM8(0xB2)
840
841#define OCR2A   _SFR_MEM8(0xB3)
842
843#define OCR2B   _SFR_MEM8(0xB4)
844
845/* Reserved [0xB5] */
846
847#define ASSR    _SFR_MEM8(0xB6)
848#define EXCLK   6
849#define AS2     5
850#define TCN2UB  4
851#define OCR2AUB 3
852#define OCR2BUB 2
853#define TCR2AUB 1
854#define TCR2BUB 0
855
856/* Reserved [0xB7] */
857
858#define TWBR    _SFR_MEM8(0xB8)
859
860#define TWSR    _SFR_MEM8(0xB9)
861#define TWS7    7
862#define TWS6    6
863#define TWS5    5
864#define TWS4    4
865#define TWS3    3
866#define TWPS1   1
867#define TWPS0   0
868
869#define TWAR    _SFR_MEM8(0xBA)
870#define TWA6    7
871#define TWA5    6
872#define TWA4    5
873#define TWA3    4
874#define TWA2    3
875#define TWA1    2
876#define TWA0    1
877#define TWGCE   0
878
879#define TWDR    _SFR_MEM8(0xBB)
880
881#define TWCR    _SFR_MEM8(0xBC)
882#define TWINT   7
883#define TWEA    6
884#define TWSTA   5
885#define TWSTO   4
886#define TWWC    3
887#define TWEN    2
888#define TWIE    0
889
890#define TWAMR   _SFR_MEM8(0xBD)
891#define TWAM6   7
892#define TWAM5   6
893#define TWAM4   5
894#define TWAM3   4
895#define TWAM2   3
896#define TWAM1   2
897#define TWAM0   1
898
899/* Reserved [0xBE..0xC7] */
900
901#define UCSR1A  _SFR_MEM8(0xC8)
902#define RXC1    7
903#define TXC1    6
904#define UDRE1   5
905#define FE1     4
906#define DOR1    3
907#define UPE1    2
908#define U2X1    1
909#define MPCM1   0
910
911#define UCSR1B  _SFR_MEM8(0XC9)
912#define RXCIE1  7
913#define TXCIE1  6
914#define UDRIE1  5
915#define RXEN1   4
916#define TXEN1   3
917#define UCSZ12  2
918#define RXB81   1
919#define TXB81   0
920
921#define UCSR1C  _SFR_MEM8(0xCA)
922#define UMSEL11 7
923#define UMSEL10 6
924#define UPM11   5
925#define UPM10   4
926#define USBS1   3
927#define UCSZ11  2
928#define UCSZ10  1
929#define UCPOL1  0
930
931/* Reserved [0xCB] */
932
933/* Combine UBRR1L and UBRR1H */
934#define UBRR1   _SFR_MEM16(0xCC)
935
936#define UBRR1L  _SFR_MEM8(0xCC)
937#define UBRR1H  _SFR_MEM8(0xCD)
938
939#define UDR1    _SFR_MEM8(0XCE)
940
941/* Reserved [0xCF..0xD6] */
942
943#define UHWCON  _SFR_MEM8(0XD7)
944#define UIMOD   7
945#define UIDE    6
946#define UVCONE  4
947#define UVREGE  0
948
949#define USBCON  _SFR_MEM8(0XD8)
950#define USBE    7
951#define HOST    6
952#define FRZCLK  5
953#define OTGPADE 4
954#define IDTE    1
955#define VBUSTE  0
956
957#define USBSTA  _SFR_MEM8(0XD9)
958#define SPEED   3
959#define ID      1
960#define VBUS    0
961
962#define USBINT  _SFR_MEM8(0XDA)
963#define IDTI    1
964#define VBUSTI  0
965
966/* Combine UDPADDL and UDPADDH */
967#define UDPADD  _SFR_MEM16(0xDB)
968
969#define UDPADDL _SFR_MEM8(0xDB)
970#define UDPADDH _SFR_MEM8(0xDC)
971#define DPACC   7
972
973#if defined(__AT90USBxx7__)
974
975#define OTGCON  _SFR_MEM8(0XDD)
976#define HNPREQ  5
977#define SRPREQ  4
978#define SRPSEL  3
979#define VBUSHWC 2
980#define VBUSREQ 1
981#define VBUSRQC 0
982
983#define OTGIEN  _SFR_MEM8(0XDE)
984#define STOE    5
985#define HNPERRE 4
986#define ROLEEXE 3
987#define BCERRE  2
988#define VBERRE  1
989#define SRPE    0
990
991#define OTGINT  _SFR_MEM8(0XDF)
992#define STOI    5
993#define HNPERRI 4
994#define ROLEEXI 3
995#define BCERRI  2
996#define VBERRI  1
997#define SRPI    0
998
999#endif /* __AT90USBxx7__ */
1000
1001#define UDCON   _SFR_MEM8(0XE0)
1002#define LSM     2
1003#define RMWKUP  1
1004#define DETACH  0
1005
1006#define UDINT   _SFR_MEM8(0XE1)
1007#define UPRSMI  6
1008#define EORSMI  5
1009#define WAKEUPI 4
1010#define EORSTI  3
1011#define SOFI    2
1012/* #define MSOFI   1 */ /* Reserved */
1013#define SUSPI   0
1014
1015#define UDIEN   _SFR_MEM8(0XE2)
1016#define UPRSME  6
1017#define EORSME  5
1018#define WAKEUPE 4
1019#define EORSTE  3
1020#define SOFE    2
1021/* #define MSOFE   1 */ /* Reserved */
1022#define SUSPE   0
1023
1024#define UDADDR  _SFR_MEM8(0XE3)
1025#define ADDEN   7
1026
1027/* Combine UDFNUML and UDFNUMH */
1028#define UDFNUM  _SFR_MEM16(0xE4)
1029
1030#define UDFNUML _SFR_MEM8(0xE4)
1031#define UDFNUMH _SFR_MEM8(0xE5)
1032
1033#define UDMFN   _SFR_MEM8(0XE6)
1034#define FNCERR  4
1035
1036#define UDTST   _SFR_MEM8(0XE7)
1037#define OPMODE2 5
1038#define TSTPCKT 4
1039#define TSTK    3
1040#define TSTJ    2
1041
1042#define UEINTX  _SFR_MEM8(0XE8)
1043#define FIFOCON 7
1044#define NAKINI  6
1045#define RWAL    5
1046#define NAKOUTI 4
1047#define RXSTPI  3
1048#define RXOUTI  2
1049#define STALLEDI 1
1050#define TXINI   0
1051
1052#define UENUM   _SFR_MEM8(0XE9)
1053
1054#define UERST   _SFR_MEM8(0XEA)
1055#define EPRST6  6
1056#define EPRST5  5
1057#define EPRST4  4
1058#define EPRST3  3
1059#define EPRST2  2
1060#define EPRST1  1
1061#define EPRST0  0
1062
1063#define UECONX  _SFR_MEM8(0XEB)
1064#define STALLRQ 5
1065#define STALLRQC 4
1066#define RSTDT   3
1067#define EPEN    0
1068
1069#define UECFG0X _SFR_MEM8(0XEC)
1070#define EPTYPE1 7
1071#define EPTYPE0 6
1072/* #define ISOSW   3 */ /* Reserved */
1073/* #define AUTOSW  2 */ /* Reserved */
1074/* #define NYETSDIS 1 */ /* Reserved */
1075#define EPDIR   0
1076
1077#define UECFG1X  _SFR_MEM8(0XED)
1078#define EPSIZE2 6
1079#define EPSIZE1 5
1080#define EPSIZE0 4
1081#define EPBK1   3
1082#define EPBK0   2
1083#define ALLOC   1
1084
1085#define UESTA0X _SFR_MEM8(0XEE)
1086#define CFGOK   7
1087#define OVERFI  6
1088#define UNDERFI 5
1089#define ZLPSEEN 4
1090#define DTSEQ1  3
1091#define DTSEQ0  2
1092#define NBUSYBK1 1
1093#define NBUSYBK0 0
1094
1095#define UESTA1X _SFR_MEM8(0XEF)
1096#define CTRLDIR 2
1097#define CURRBK1 1
1098#define CURRBK0 0
1099
1100#define UEIENX  _SFR_MEM8(0XF0)
1101#define FLERRE  7
1102#define NAKINE  6
1103#define NAKOUTE 4
1104#define RXSTPE  3
1105#define RXOUTE  2
1106#define STALLEDE 1
1107#define TXINE   0
1108
1109#define UEDATX  _SFR_MEM8(0XF1)
1110
1111/* Combine UEBCLX and UEBCHX */
1112#define UEBCX   _SFR_MEM16(0xF2)
1113
1114#define UEBCLX  _SFR_MEM8(0xF2)
1115#define UEBCHX  _SFR_MEM8(0xF3)
1116
1117#define UEINT   _SFR_MEM8(0XF4)
1118#define EPINT6  6
1119#define EPINT5  5
1120#define EPINT4  4
1121#define EPINT3  3
1122#define EPINT2  2
1123#define EPINT1  1
1124#define EPINT0  0
1125
1126#if defined(__AT90USBxx7__)
1127
1128#define UPERRX  _SFR_MEM8(0XF5)
1129#define COUNTER1 6
1130#define COUNTER0 5
1131#define CRC16    4
1132#define TIMEOUT  3
1133#define PID      2
1134#define DATAPID  1
1135#define DATATGL  0
1136
1137/* Combine UPBCLX and UPBCHX */
1138#define UPBCX   _SFR_MEM16(0xF6)
1139
1140#define UPBCLX  _SFR_MEM8(0xF6)
1141#define UPBCHX  _SFR_MEM8(0xF7)
1142
1143#define UPINT   _SFR_MEM8(0XF8)
1144#define PINT6   6
1145#define PINT5   5
1146#define PINT4   4
1147#define PINT3   3
1148#define PINT2   2
1149#define PINT1   1
1150#define PINT0   0
1151
1152#define OTGTCON _SFR_MEM8(0XF9)
1153#define PAGE1   6
1154#define PAGE0   5
1155#define VALUE1  1
1156#define VALUE0  0
1157
1158#endif /* __AT90USBxx7__ */
1159
1160/* Reserved [0xFA..0xFF] */
1161
1162/* Interrupt vectors */
1163
1164/* External Interrupt Request 0 */
1165#define INT0_vect                       _VECTOR(1)
1166
1167/* External Interrupt Request 1 */
1168#define INT1_vect                       _VECTOR(2)
1169
1170/* External Interrupt Request 2 */
1171#define INT2_vect                       _VECTOR(3)
1172
1173/* External Interrupt Request 3 */
1174#define INT3_vect                       _VECTOR(4)
1175
1176/* External Interrupt Request 4 */
1177#define INT4_vect                       _VECTOR(5)
1178
1179/* External Interrupt Request 5 */
1180#define INT5_vect                       _VECTOR(6)
1181
1182/* External Interrupt Request 6 */
1183#define INT6_vect                       _VECTOR(7)
1184
1185/* External Interrupt Request 7 */
1186#define INT7_vect                       _VECTOR(8)
1187
1188/* Pin Change Interrupt Request 0 */
1189#define PCINT0_vect                     _VECTOR(9)
1190
1191/* USB General Interrupt Request */
1192#define USB_GEN_vect                    _VECTOR(10)
1193
1194/* USB Endpoint/Pipe Interrupt Communication Request */
1195#define USB_COM_vect                    _VECTOR(11)
1196
1197/* Watchdog Time-out Interrupt */
1198#define WDT_vect                        _VECTOR(12)
1199
1200/* Timer/Counter2 Compare Match A */
1201#define TIMER2_COMPA_vect               _VECTOR(13)
1202
1203/* Timer/Counter2 Compare Match B */
1204#define TIMER2_COMPB_vect               _VECTOR(14)
1205
1206/* Timer/Counter2 Overflow */
1207#define TIMER2_OVF_vect                 _VECTOR(15)
1208
1209/* Timer/Counter1 Capture Event */
1210#define TIMER1_CAPT_vect                _VECTOR(16)
1211
1212/* Timer/Counter1 Compare Match A */
1213#define TIMER1_COMPA_vect               _VECTOR(17)
1214
1215/* Timer/Counter1 Compare Match B */
1216#define TIMER1_COMPB_vect               _VECTOR(18)
1217
1218/* Timer/Counter1 Compare Match C */
1219#define TIMER1_COMPC_vect               _VECTOR(19)
1220
1221/* Timer/Counter1 Overflow */
1222#define TIMER1_OVF_vect                 _VECTOR(20)
1223
1224/* Timer/Counter0 Compare Match A */
1225#define TIMER0_COMPA_vect               _VECTOR(21)
1226
1227/* Timer/Counter0 Compare Match B */
1228#define TIMER0_COMPB_vect               _VECTOR(22)
1229
1230/* Timer/Counter0 Overflow */
1231#define TIMER0_OVF_vect                 _VECTOR(23)
1232
1233/* SPI Serial Transfer Complete */
1234#define SPI_STC_vect                    _VECTOR(24)
1235
1236/* USART1, Rx Complete */
1237#define USART1_RX_vect                  _VECTOR(25)
1238
1239/* USART1 Data register Empty */
1240#define USART1_UDRE_vect                _VECTOR(26)
1241
1242/* USART1, Tx Complete */
1243#define USART1_TX_vect                  _VECTOR(27)
1244
1245/* Analog Comparator */
1246#define ANALOG_COMP_vect                _VECTOR(28)
1247
1248/* ADC Conversion Complete */
1249#define ADC_vect                        _VECTOR(29)
1250
1251/* EEPROM Ready */
1252#define EE_READY_vect                   _VECTOR(30)
1253
1254/* Timer/Counter3 Capture Event */
1255#define TIMER3_CAPT_vect                _VECTOR(31)
1256
1257/* Timer/Counter3 Compare Match A */
1258#define TIMER3_COMPA_vect               _VECTOR(32)
1259
1260/* Timer/Counter3 Compare Match B */
1261#define TIMER3_COMPB_vect               _VECTOR(33)
1262
1263/* Timer/Counter3 Compare Match C */
1264#define TIMER3_COMPC_vect               _VECTOR(34)
1265
1266/* Timer/Counter3 Overflow */
1267#define TIMER3_OVF_vect                 _VECTOR(35)
1268
1269/* 2-wire Serial Interface */
1270#define TWI_vect                        _VECTOR(36)
1271
1272/* Store Program Memory Read */
1273#define SPM_READY_vect                  _VECTOR(37)
1274
1275#define _VECTORS_SIZE 152
1276
1277#if defined(__AT90USBxx6__)
1278# undef __AT90USBxx6__
1279#endif /* __AT90USBxx6__ */
1280
1281#if defined(__AT90USBxx7__)
1282# undef __AT90USBxx7__
1283#endif /* __AT90USBxx7__ */
1284
1285#endif  /* _AVR_IOUSBXX6_7_H_ */
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