1 | /* Copyright (c) 2007 Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ |
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34 | |
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35 | #ifndef _AVR_IOUSBXX2_H_ |
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36 | #define _AVR_IOUSBXX2_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "iousbxx2.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* Registers and associated bit numbers */ |
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51 | |
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52 | /* Reserved [0x00..0x02] */ |
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53 | |
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54 | #define PINB _SFR_IO8(0X03) |
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55 | #define PINB7 7 |
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56 | #define PINB6 6 |
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57 | #define PINB5 5 |
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58 | #define PINB4 4 |
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59 | #define PINB3 3 |
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60 | #define PINB2 2 |
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61 | #define PINB1 1 |
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62 | #define PINB0 0 |
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63 | |
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64 | #define DDRB _SFR_IO8(0x04) |
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65 | #define DDB7 7 |
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66 | #define DDB6 6 |
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67 | #define DDB5 5 |
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68 | #define DDB4 4 |
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69 | #define DDB3 3 |
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70 | #define DDB2 2 |
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71 | #define DDB1 1 |
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72 | #define DDB0 0 |
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73 | |
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74 | #define PORTB _SFR_IO8(0x05) |
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75 | #define PB7 7 |
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76 | #define PB6 6 |
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77 | #define PB5 5 |
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78 | #define PB4 4 |
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79 | #define PB3 3 |
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80 | #define PB2 2 |
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81 | #define PB1 1 |
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82 | #define PB0 0 |
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83 | |
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84 | #define PINC _SFR_IO8(0x06) |
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85 | #define PINC7 7 |
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86 | #define PINC6 6 |
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87 | #define PINC5 5 |
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88 | #define PINC4 4 |
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89 | #define PINC2 2 |
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90 | #define PINC1 1 |
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91 | #define PINC0 0 |
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92 | |
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93 | #define DDRC _SFR_IO8(0x07) |
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94 | #define DDC7 7 |
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95 | #define DDC6 6 |
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96 | #define DDC5 5 |
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97 | #define DDC4 4 |
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98 | #define DDC2 2 |
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99 | #define DDC1 1 |
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100 | #define DDC0 0 |
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101 | |
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102 | #define PORTC _SFR_IO8(0x08) |
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103 | #define PC7 7 |
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104 | #define PC6 6 |
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105 | #define PC5 5 |
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106 | #define PC4 4 |
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107 | #define PC2 2 |
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108 | #define PC1 1 |
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109 | #define PC0 0 |
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110 | |
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111 | #define PIND _SFR_IO8(0x09) |
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112 | #define PIND7 7 |
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113 | #define PIND6 6 |
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114 | #define PIND5 5 |
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115 | #define PIND4 4 |
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116 | #define PIND3 3 |
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117 | #define PIND2 2 |
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118 | #define PIND1 1 |
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119 | #define PIND0 0 |
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120 | |
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121 | #define DDRD _SFR_IO8(0x0A) |
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122 | #define DDD7 7 |
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123 | #define DDD6 6 |
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124 | #define DDD5 5 |
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125 | #define DDD4 4 |
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126 | #define DDD3 3 |
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127 | #define DDD2 2 |
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128 | #define DDD1 1 |
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129 | #define DDD0 0 |
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130 | |
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131 | #define PORTD _SFR_IO8(0x0B) |
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132 | #define PD7 7 |
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133 | #define PD6 6 |
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134 | #define PD5 5 |
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135 | #define PD4 4 |
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136 | #define PD3 3 |
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137 | #define PD2 2 |
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138 | #define PD1 1 |
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139 | #define PD0 0 |
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140 | |
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141 | /* Reserved [0xC..0x14] */ |
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142 | |
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143 | #define TIFR0 _SFR_IO8(0x15) |
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144 | #define OCF0B 2 |
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145 | #define OCF0A 1 |
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146 | #define TOV0 0 |
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147 | |
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148 | #define TIFR1 _SFR_IO8(0x16) |
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149 | #define ICF1 5 |
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150 | #define OCF1C 3 |
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151 | #define OCF1B 2 |
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152 | #define OCF1A 1 |
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153 | #define TOV1 0 |
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154 | |
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155 | /* Reserved [0x17..0x1A] */ |
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156 | |
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157 | #define PCIFR _SFR_IO8(0x1B) |
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158 | #define PCIF1 1 |
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159 | #define PCIF0 0 |
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160 | |
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161 | #define EIFR _SFR_IO8(0x1C) |
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162 | #define INTF7 7 |
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163 | #define INTF6 6 |
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164 | #define INTF5 5 |
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165 | #define INTF4 4 |
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166 | #define INTF3 3 |
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167 | #define INTF2 2 |
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168 | #define INTF1 1 |
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169 | #define INTF0 0 |
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170 | |
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171 | #define EIMSK _SFR_IO8(0x1D) |
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172 | #define INT7 7 |
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173 | #define INT6 6 |
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174 | #define INT5 5 |
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175 | #define INT4 4 |
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176 | #define INT3 3 |
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177 | #define INT2 2 |
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178 | #define INT1 1 |
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179 | #define INT0 0 |
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180 | |
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181 | #define GPIOR0 _SFR_IO8(0x1E) |
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182 | |
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183 | #define EECR _SFR_IO8(0x1F) |
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184 | #define EEPM1 5 |
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185 | #define EEPM0 4 |
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186 | #define EERIE 3 |
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187 | #define EEMPE 2 |
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188 | #define EEPE 1 |
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189 | #define EERE 0 |
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190 | |
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191 | #define EEDR _SFR_IO8(0x20) |
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192 | |
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193 | #define EEAR _SFR_IO16(0x21) |
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194 | #define EEARL _SFR_IO8(0x21) |
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195 | #define EEARH _SFR_IO8(0x22) |
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196 | |
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197 | /* 6-char sequence denoting where to find the EEPROM registers in memory space. |
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198 | Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM |
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199 | subroutines. |
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200 | First two letters: EECR address. |
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201 | Second two letters: EEDR address. |
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202 | Last two letters: EEAR address. */ |
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203 | #define __EEPROM_REG_LOCATIONS__ 1F2021 |
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204 | |
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205 | #define GTCCR _SFR_IO8(0x23) |
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206 | #define TSM 7 |
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207 | #define PSRASY 1 |
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208 | #define PSRSYNC 0 |
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209 | |
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210 | #define TCCR0A _SFR_IO8(0x24) |
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211 | #define COM0A1 7 |
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212 | #define COM0A0 6 |
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213 | #define COM0B1 5 |
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214 | #define COM0B0 4 |
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215 | #define WGM01 1 |
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216 | #define WGM00 0 |
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217 | |
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218 | #define TCCR0B _SFR_IO8(0x25) |
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219 | #define FOC0A 7 |
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220 | #define FOC0B 6 |
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221 | #define WGM02 3 |
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222 | #define CS02 2 |
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223 | #define CS01 1 |
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224 | #define CS00 0 |
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225 | |
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226 | #define TCNT0 _SFR_IO8(0X26) |
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227 | |
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228 | #define OCR0A _SFR_IO8(0x27) |
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229 | |
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230 | #define OCR0B _SFR_IO8(0X28) |
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231 | |
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232 | #define PLLCSR _SFR_IO8(0x29) |
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233 | #define PLLP2 4 |
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234 | #define PLLP1 3 |
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235 | #define PLLP0 2 |
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236 | #define PLLE 1 |
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237 | #define PLOCK 0 |
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238 | |
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239 | #define GPIOR1 _SFR_IO8(0x2A) |
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240 | |
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241 | #define GPIOR2 _SFR_IO8(0x2B) |
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242 | |
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243 | #define SPCR _SFR_IO8(0x2C) |
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244 | #define SPIE 7 |
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245 | #define SPE 6 |
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246 | #define DORD 5 |
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247 | #define MSTR 4 |
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248 | #define CPOL 3 |
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249 | #define CPHA 2 |
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250 | #define SPR1 1 |
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251 | #define SPR0 0 |
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252 | |
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253 | #define SPSR _SFR_IO8(0x2D) |
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254 | #define SPIF 7 |
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255 | #define WCOL 6 |
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256 | #define SPI2X 0 |
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257 | |
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258 | #define SPDR _SFR_IO8(0x2E) |
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259 | |
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260 | /* Reserved [0x2F] */ |
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261 | |
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262 | #define ACSR _SFR_IO8(0x30) |
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263 | #define ACD 7 |
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264 | #define ACBG 6 |
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265 | #define ACO 5 |
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266 | #define ACI 4 |
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267 | #define ACIE 3 |
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268 | #define ACIC 2 |
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269 | #define ACIS1 1 |
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270 | #define ACIS0 0 |
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271 | |
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272 | #define DWDR _SFR_IO8(0x31) |
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273 | #define IDRD 7 |
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274 | |
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275 | /* Reserved [0x32] */ |
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276 | |
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277 | #define SMCR _SFR_IO8(0x33) |
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278 | #define SM2 3 |
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279 | #define SM1 2 |
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280 | #define SM0 1 |
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281 | #define SE 0 |
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282 | |
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283 | #define MCUSR _SFR_IO8(0x34) |
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284 | #define USBRF 5 |
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285 | #define WDRF 3 |
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286 | #define BORF 2 |
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287 | #define EXTRF 1 |
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288 | #define PORF 0 |
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289 | |
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290 | #define MCUCR _SFR_IO8(0x35) |
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291 | #define IVSEL 1 |
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292 | #define IVCE 0 |
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293 | |
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294 | /* Reserved [0x36] */ |
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295 | |
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296 | #define SPMCSR _SFR_IO8(0x37) |
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297 | #define SPMIE 7 |
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298 | #define RWWSB 6 |
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299 | #define SIGRD 5 |
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300 | #define RWWSRE 4 |
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301 | #define BLBSET 3 |
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302 | #define PGWRT 2 |
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303 | #define PGERS 1 |
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304 | #define SPMEN 0 |
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305 | |
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306 | /* Reserved [0x38..0x3C] */ |
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307 | |
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308 | /* SP [0x3D..0x3E] */ |
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309 | /* SREG [0x3F] */ |
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310 | |
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311 | #define WDTCSR _SFR_MEM8(0x60) |
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312 | #define WDIF 7 |
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313 | #define WDIE 6 |
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314 | #define WDP3 5 |
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315 | #define WDCE 4 |
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316 | #define WDE 3 |
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317 | #define WDP2 2 |
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318 | #define WDP1 1 |
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319 | #define WDP0 0 |
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320 | |
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321 | #define CLKPR _SFR_MEM8(0x61) |
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322 | #define CLKPCE 7 |
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323 | #define CLKPS3 3 |
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324 | #define CLKPS2 2 |
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325 | #define CLKPS1 1 |
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326 | #define CLKPS0 0 |
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327 | |
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328 | #define WDTCKD _SFR_MEM8(0x62) |
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329 | #define WDEWIF 3 |
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330 | #define WDEWIE 2 |
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331 | #define WCLKD1 1 |
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332 | #define WCLKD0 0 |
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333 | |
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334 | #define REGCR _SFR_MEM8(0x63) |
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335 | #define REGDIS 0 |
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336 | |
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337 | #define PRR0 _SFR_MEM8(0x64) |
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338 | #define PRTIM0 5 |
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339 | #define PRTIM1 3 |
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340 | #define PRSPI 2 |
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341 | |
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342 | #define PRR1 _SFR_MEM8(0x65) |
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343 | #define PRUSB 7 |
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344 | #define PRUSART1 0 |
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345 | |
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346 | #define OSCCAL _SFR_MEM8(0x66) |
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347 | |
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348 | /* Reserved [0x67] */ |
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349 | |
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350 | #define PCICR _SFR_MEM8(0x68) |
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351 | #define PCIE1 1 |
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352 | #define PCIE0 0 |
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353 | |
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354 | #define EICRA _SFR_MEM8(0x69) |
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355 | #define ISC31 7 |
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356 | #define ISC30 6 |
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357 | #define ISC21 5 |
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358 | #define ISC20 4 |
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359 | #define ISC11 3 |
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360 | #define ISC10 2 |
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361 | #define ISC01 1 |
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362 | #define ISC00 0 |
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363 | |
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364 | #define EICRB _SFR_MEM8(0x6A) |
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365 | #define ISC71 7 |
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366 | #define ISC70 6 |
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367 | #define ISC61 5 |
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368 | #define ISC60 4 |
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369 | #define ISC51 3 |
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370 | #define ISC50 2 |
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371 | #define ISC41 1 |
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372 | #define ISC40 0 |
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373 | |
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374 | #define PCMSK0 _SFR_MEM8(0x6B) |
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375 | #define PCINT7 7 |
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376 | #define PCINT6 6 |
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377 | #define PCINT5 5 |
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378 | #define PCINT4 4 |
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379 | #define PCINT3 3 |
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380 | #define PCINT2 2 |
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381 | #define PCINT1 1 |
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382 | #define PCINT0 0 |
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383 | |
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384 | #define PCMSK1 _SFR_MEM8(0x6C) |
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385 | #define PCINT12 4 |
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386 | #define PCINT11 3 |
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387 | #define PCINT10 2 |
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388 | #define PCINT9 1 |
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389 | #define PCINT8 0 |
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390 | |
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391 | /* Reserved [0x6D] */ |
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392 | |
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393 | #define TIMSK0 _SFR_MEM8(0x6E) |
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394 | #define OCIE0B 2 |
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395 | #define OCIE0A 1 |
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396 | #define TOIE0 0 |
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397 | |
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398 | #define TIMSK1 _SFR_MEM8(0x6F) |
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399 | #define ICIE1 5 |
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400 | #define OCIE1C 3 |
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401 | #define OCIE1B 2 |
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402 | #define OCIE1A 1 |
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403 | #define TOIE1 0 |
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404 | |
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405 | /* Reserved [0x70..0x7F] */ |
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406 | |
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407 | #define TCCR1A _SFR_MEM8(0x80) |
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408 | #define COM1A1 7 |
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409 | #define COM1A0 6 |
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410 | #define COM1B1 5 |
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411 | #define COM1B0 4 |
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412 | #define COM1C1 3 |
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413 | #define COM1C0 2 |
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414 | #define WGM11 1 |
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415 | #define WGM10 0 |
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416 | |
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417 | #define TCCR1B _SFR_MEM8(0x81) |
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418 | #define ICNC1 7 |
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419 | #define ICES1 6 |
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420 | #define WGM13 4 |
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421 | #define WGM12 3 |
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422 | #define CS12 2 |
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423 | #define CS11 1 |
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424 | #define CS10 0 |
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425 | |
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426 | #define TCCR1C _SFR_MEM8(0x82) |
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427 | #define FOC1A 7 |
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428 | #define FOC1B 6 |
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429 | #define FOC1C 5 |
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430 | |
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431 | /* Reserved [0x83] */ |
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432 | |
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433 | /* Combine TCNT1L and TCNT1H */ |
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434 | #define TCNT1 _SFR_MEM16(0x84) |
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435 | |
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436 | #define TCNT1L _SFR_MEM8(0x84) |
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437 | #define TCNT1H _SFR_MEM8(0x85) |
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438 | |
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439 | /* Combine ICR1L and ICR1H */ |
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440 | #define ICR1 _SFR_MEM16(0x86) |
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441 | |
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442 | #define ICR1L _SFR_MEM8(0x86) |
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443 | #define ICR1H _SFR_MEM8(0x87) |
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444 | |
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445 | /* Combine OCR1AL and OCR1AH */ |
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446 | #define OCR1A _SFR_MEM16(0x88) |
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447 | |
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448 | #define OCR1AL _SFR_MEM8(0x88) |
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449 | #define OCR1AH _SFR_MEM8(0x89) |
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450 | |
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451 | /* Combine OCR1BL and OCR1BH */ |
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452 | #define OCR1B _SFR_MEM16(0x8A) |
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453 | |
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454 | #define OCR1BL _SFR_MEM8(0x8A) |
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455 | #define OCR1BH _SFR_MEM8(0x8B) |
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456 | |
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457 | /* Combine OCR1CL and OCR1CH */ |
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458 | #define OCR1C _SFR_MEM16(0x8C) |
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459 | |
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460 | #define OCR1CL _SFR_MEM8(0x8C) |
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461 | #define OCR1CH _SFR_MEM8(0x8D) |
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462 | |
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463 | /* Reserved [0x8E..0xC7] */ |
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464 | |
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465 | #define UCSR1A _SFR_MEM8(0xC8) |
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466 | #define RXC1 7 |
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467 | #define TXC1 6 |
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468 | #define UDRE1 5 |
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469 | #define FE1 4 |
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470 | #define DOR1 3 |
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471 | #define UPE1 2 |
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472 | #define U2X1 1 |
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473 | #define MPCM1 0 |
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474 | |
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475 | #define UCSR1B _SFR_MEM8(0XC9) |
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476 | #define RXCIE1 7 |
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477 | #define TXCIE1 6 |
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478 | #define UDRIE1 5 |
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479 | #define RXEN1 4 |
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480 | #define TXEN1 3 |
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481 | #define UCSZ12 2 |
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482 | #define RXB81 1 |
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483 | #define TXB81 0 |
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484 | |
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485 | #define UCSR1C _SFR_MEM8(0xCA) |
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486 | #define UMSEL11 7 |
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487 | #define UMSEL10 6 |
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488 | #define UPM11 5 |
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489 | #define UPM10 4 |
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490 | #define USBS1 3 |
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491 | #define UCSZ11 2 |
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492 | #define UCSZ10 1 |
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493 | #define UCPOL1 0 |
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494 | |
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495 | #define UCSR1D _SFR_MEM8(0xCB) |
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496 | #define CTSEN 1 |
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497 | #define RTSEN 0 |
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498 | |
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499 | /* Combine UBRR1L and UBRR1H */ |
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500 | #define UBRR1 _SFR_MEM16(0xCC) |
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501 | |
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502 | #define UBRR1L _SFR_MEM8(0xCC) |
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503 | #define UBRR1H _SFR_MEM8(0xCD) |
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504 | |
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505 | #define UDR1 _SFR_MEM8(0XCE) |
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506 | |
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507 | /* Reserved [0xCF] */ |
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508 | |
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509 | #define CKSEL0 _SFR_MEM8(0XD0) |
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510 | #define RCSUT1 7 |
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511 | #define RCSUT0 6 |
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512 | #define EXSUT1 5 |
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513 | #define EXSUT0 4 |
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514 | #define RCE 3 |
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515 | #define EXTE 2 |
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516 | #define CLKS 0 |
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517 | |
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518 | #define CKSEL1 _SFR_MEM8(0XD1) |
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519 | #define RCCKSEL3 7 |
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520 | #define RCCKSEL2 6 |
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521 | #define RCCKSEL1 5 |
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522 | #define RCCKSEL0 4 |
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523 | #define EXCKSEL3 3 |
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524 | #define EXCKSEL2 2 |
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525 | #define EXCKSEL1 1 |
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526 | #define EXCKSEL0 0 |
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527 | |
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528 | #define CKSTA _SFR_MEM8(0XD2) |
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529 | #define RCON 1 |
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530 | #define EXTON 0 |
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531 | |
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532 | /* Reserved [0xD3..0xD7] */ |
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533 | |
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534 | #define USBCON _SFR_MEM8(0XD8) |
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535 | #define USBE 7 |
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536 | #define FRZCLK 5 |
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537 | |
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538 | /* Reserved [0xD9..0xDA] */ |
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539 | |
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540 | /* Combine UDPADDL and UDPADDH */ |
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541 | #define UDPADD _SFR_MEM16(0xDB) |
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542 | |
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543 | #define UDPADDL _SFR_MEM8(0xDB) |
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544 | #define UDPADDH _SFR_MEM8(0xDC) |
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545 | #define DPACC 7 |
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546 | |
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547 | /* Reserved [0xDD..0xDF] */ |
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548 | |
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549 | #define UDCON _SFR_MEM8(0XE0) |
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550 | #define RSTCPU 2 |
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551 | #define RMWKUP 1 |
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552 | #define DETACH 0 |
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553 | |
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554 | #define UDINT _SFR_MEM8(0XE1) |
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555 | #define UPRSMI 6 |
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556 | #define EORSMI 5 |
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557 | #define WAKEUPI 4 |
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558 | #define EORSTI 3 |
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559 | #define SOFI 2 |
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560 | #define SUSPI 0 |
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561 | |
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562 | #define UDIEN _SFR_MEM8(0XE2) |
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563 | #define UPRSME 6 |
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564 | #define EORSME 5 |
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565 | #define WAKEUPE 4 |
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566 | #define EORSTE 3 |
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567 | #define SOFE 2 |
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568 | #define SUSPE 0 |
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569 | |
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570 | #define UDADDR _SFR_MEM8(0XE3) |
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571 | #define ADDEN 7 |
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572 | |
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573 | /* Combine UDFNUML and UDFNUMH */ |
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574 | #define UDFNUM _SFR_MEM16(0xE4) |
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575 | |
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576 | #define UDFNUML _SFR_MEM8(0xE4) |
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577 | #define UDFNUMH _SFR_MEM8(0xE5) |
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578 | |
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579 | #define UDMFN _SFR_MEM8(0XE6) |
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580 | #define FNCERR 4 |
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581 | |
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582 | /* Reserved [0xE7] */ |
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583 | |
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584 | #define UEINTX _SFR_MEM8(0XE8) |
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585 | #define FIFOCON 7 |
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586 | #define NAKINI 6 |
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587 | #define RWAL 5 |
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588 | #define NAKOUTI 4 |
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589 | #define RXSTPI 3 |
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590 | #define RXOUTI 2 |
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591 | #define STALLEDI 1 |
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592 | #define TXINI 0 |
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593 | |
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594 | #define UENUM _SFR_MEM8(0XE9) |
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595 | #define EPNUM2 2 |
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596 | #define EPNUM1 1 |
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597 | #define EPNUM0 0 |
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598 | |
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599 | #define UERST _SFR_MEM8(0XEA) |
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600 | #define EPRST4 4 |
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601 | #define EPRST3 3 |
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602 | #define EPRST2 2 |
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603 | #define EPRST1 1 |
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604 | #define EPRST0 0 |
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605 | |
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606 | #define UECONX _SFR_MEM8(0XEB) |
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607 | #define STALLRQ 5 |
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608 | #define STALLRQC 4 |
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609 | #define RSTDT 3 |
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610 | #define EPEN 0 |
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611 | |
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612 | #define UECFG0X _SFR_MEM8(0XEC) |
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613 | #define EPTYPE1 7 |
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614 | #define EPTYPE0 6 |
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615 | #define EPDIR 0 |
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616 | |
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617 | #define UECFG1X _SFR_MEM8(0XED) |
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618 | #define EPSIZE2 6 |
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619 | #define EPSIZE1 5 |
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620 | #define EPSIZE0 4 |
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621 | #define EPBK1 3 |
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622 | #define EPBK0 2 |
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623 | #define ALLOC 1 |
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624 | |
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625 | #define UESTA0X _SFR_MEM8(0XEE) |
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626 | #define CFGOK 7 |
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627 | #define OVERFI 6 |
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628 | #define UNDERFI 5 |
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629 | #define DTSEQ1 3 |
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630 | #define DTSEQ0 2 |
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631 | #define NBUSYBK1 1 |
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632 | #define NBUSYBK0 0 |
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633 | |
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634 | #define UESTA1X _SFR_MEM8(0XEF) |
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635 | #define CTRLDIR 2 |
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636 | #define CURRBK1 1 |
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637 | #define CURRBK0 0 |
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638 | |
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639 | #define UEIENX _SFR_MEM8(0XF0) |
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640 | #define FLERRE 7 |
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641 | #define NAKINE 6 |
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642 | #define NAKOUTE 4 |
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643 | #define RXSTPE 3 |
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644 | #define RXOUTE 2 |
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645 | #define STALLEDE 1 |
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646 | #define TXINE 0 |
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647 | |
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648 | #define UEDATX _SFR_MEM8(0XF1) |
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649 | |
---|
650 | #define UEBCLX _SFR_MEM8(0xF2) |
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651 | |
---|
652 | /* Reserved [0xF3] */ |
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653 | |
---|
654 | #define UEINT _SFR_MEM8(0XF4) |
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655 | #define EPINT4 4 |
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656 | #define EPINT3 3 |
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657 | #define EPINT2 2 |
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658 | #define EPINT1 1 |
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659 | #define EPINT0 0 |
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660 | |
---|
661 | /* Reserved [0xF5..0xF9] */ |
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662 | |
---|
663 | #define PS2CON _SFR_MEM8(0XFA) |
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664 | #define PS2EN 0 |
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665 | |
---|
666 | #define UPOE _SFR_MEM8(0XFB) |
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667 | #define UPWE1 7 |
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668 | #define UPWE0 6 |
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669 | #define UPDRV1 5 |
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670 | #define UPDRV0 4 |
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671 | #define SCKI 3 |
---|
672 | #define DATAI 2 |
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673 | #define DPI 1 |
---|
674 | #define DMI 0 |
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675 | |
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676 | /* Reserved [0xFC..0xFF] */ |
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677 | |
---|
678 | /* Interrupt vectors */ |
---|
679 | |
---|
680 | /* External Interrupt Request 0 */ |
---|
681 | #define INT0_vect _VECTOR(1) |
---|
682 | |
---|
683 | /* External Interrupt Request 1 */ |
---|
684 | #define INT1_vect _VECTOR(2) |
---|
685 | |
---|
686 | /* External Interrupt Request 2 */ |
---|
687 | #define INT2_vect _VECTOR(3) |
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688 | |
---|
689 | /* External Interrupt Request 3 */ |
---|
690 | #define INT3_vect _VECTOR(4) |
---|
691 | |
---|
692 | /* External Interrupt Request 4 */ |
---|
693 | #define INT4_vect _VECTOR(5) |
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694 | |
---|
695 | /* External Interrupt Request 5 */ |
---|
696 | #define INT5_vect _VECTOR(6) |
---|
697 | |
---|
698 | /* External Interrupt Request 6 */ |
---|
699 | #define INT6_vect _VECTOR(7) |
---|
700 | |
---|
701 | /* External Interrupt Request 7 */ |
---|
702 | #define INT7_vect _VECTOR(8) |
---|
703 | |
---|
704 | /* Pin Change Interrupt Request 0 */ |
---|
705 | #define PCINT0_vect _VECTOR(9) |
---|
706 | |
---|
707 | /* Pin Change Interrupt Request 1 */ |
---|
708 | #define PCINT1_vect _VECTOR(10) |
---|
709 | |
---|
710 | /* USB General Interrupt Request */ |
---|
711 | #define USB_GEN_vect _VECTOR(11) |
---|
712 | |
---|
713 | /* USB Endpoint/Pipe Interrupt Communication Request */ |
---|
714 | #define USB_COM_vect _VECTOR(12) |
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715 | |
---|
716 | /* Watchdog Time-out Interrupt */ |
---|
717 | #define WDT_vect _VECTOR(13) |
---|
718 | |
---|
719 | /* Timer/Counter2 Capture Event */ |
---|
720 | #define TIMER1_CAPT_vect _VECTOR(14) |
---|
721 | |
---|
722 | /* Timer/Counter2 Compare Match B */ |
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723 | #define TIMER1_COMPA_vect _VECTOR(15) |
---|
724 | |
---|
725 | /* Timer/Counter2 Compare Match B */ |
---|
726 | #define TIMER1_COMPB_vect _VECTOR(16) |
---|
727 | |
---|
728 | /* Timer/Counter2 Compare Match C */ |
---|
729 | #define TIMER1_COMPC_vect _VECTOR(17) |
---|
730 | |
---|
731 | /* Timer/Counter1 Overflow */ |
---|
732 | #define TIMER1_OVF_vect _VECTOR(18) |
---|
733 | |
---|
734 | /* Timer/Counter0 Compare Match A */ |
---|
735 | #define TIMER0_COMPA_vect _VECTOR(19) |
---|
736 | |
---|
737 | /* Timer/Counter0 Compare Match B */ |
---|
738 | #define TIMER0_COMPB_vect _VECTOR(20) |
---|
739 | |
---|
740 | /* Timer/Counter0 Overflow */ |
---|
741 | #define TIMER0_OVF_vect _VECTOR(21) |
---|
742 | |
---|
743 | /* SPI Serial Transfer Complete */ |
---|
744 | #define SPI_STC_vect _VECTOR(22) |
---|
745 | |
---|
746 | /* USART1, Rx Complete */ |
---|
747 | #define USART1_RX_vect _VECTOR(23) |
---|
748 | |
---|
749 | /* USART1 Data register Empty */ |
---|
750 | #define USART1_UDRE_vect _VECTOR(24) |
---|
751 | |
---|
752 | /* USART1, Tx Complete */ |
---|
753 | #define USART1_TX_vect _VECTOR(25) |
---|
754 | |
---|
755 | /* Analog Comparator */ |
---|
756 | #define ANALOG_COMP_vect _VECTOR(26) |
---|
757 | |
---|
758 | /* EEPROM Ready */ |
---|
759 | #define EE_READY_vect _VECTOR(27) |
---|
760 | |
---|
761 | /* Store Program Memory Read */ |
---|
762 | #define SPM_READY_vect _VECTOR(28) |
---|
763 | |
---|
764 | #define _VECTORS_SIZE 116 |
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765 | |
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766 | #endif /* _AVR_IOUSBXX2_H_ */ |
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