source: rtems/cpukit/score/cpu/avr/avr/iousbxx2.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 14.9 KB
Line 
1/* Copyright (c) 2007 Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* iousbxx2.h - definitions for AT90USB82 and AT90USB162.  */
34
35#ifndef _AVR_IOUSBXX2_H_
36#define _AVR_IOUSBXX2_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iousbxx2.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* Registers and associated bit numbers */
51
52/* Reserved [0x00..0x02] */
53
54#define PINB    _SFR_IO8(0X03)
55#define PINB7   7
56#define PINB6   6
57#define PINB5   5
58#define PINB4   4
59#define PINB3   3
60#define PINB2   2
61#define PINB1   1
62#define PINB0   0
63
64#define DDRB    _SFR_IO8(0x04)
65#define DDB7    7
66#define DDB6    6
67#define DDB5    5
68#define DDB4    4
69#define DDB3    3
70#define DDB2    2
71#define DDB1    1
72#define DDB0    0
73
74#define PORTB   _SFR_IO8(0x05)
75#define PB7     7
76#define PB6     6
77#define PB5     5
78#define PB4     4
79#define PB3     3
80#define PB2     2
81#define PB1     1
82#define PB0     0
83
84#define PINC    _SFR_IO8(0x06)
85#define PINC7   7
86#define PINC6   6
87#define PINC5   5
88#define PINC4   4
89#define PINC2   2
90#define PINC1   1
91#define PINC0   0
92
93#define DDRC    _SFR_IO8(0x07)
94#define DDC7    7
95#define DDC6    6
96#define DDC5    5
97#define DDC4    4
98#define DDC2    2
99#define DDC1    1
100#define DDC0    0
101
102#define PORTC   _SFR_IO8(0x08)
103#define PC7     7
104#define PC6     6
105#define PC5     5
106#define PC4     4
107#define PC2     2
108#define PC1     1
109#define PC0     0
110
111#define PIND    _SFR_IO8(0x09)
112#define PIND7   7
113#define PIND6   6
114#define PIND5   5
115#define PIND4   4
116#define PIND3   3
117#define PIND2   2
118#define PIND1   1
119#define PIND0   0
120
121#define DDRD    _SFR_IO8(0x0A)
122#define DDD7    7
123#define DDD6    6
124#define DDD5    5
125#define DDD4    4
126#define DDD3    3
127#define DDD2    2
128#define DDD1    1
129#define DDD0    0
130
131#define PORTD   _SFR_IO8(0x0B)
132#define PD7     7
133#define PD6     6
134#define PD5     5
135#define PD4     4
136#define PD3     3
137#define PD2     2
138#define PD1     1
139#define PD0     0
140
141/* Reserved [0xC..0x14] */
142
143#define TIFR0   _SFR_IO8(0x15)
144#define OCF0B   2
145#define OCF0A   1
146#define TOV0    0
147
148#define TIFR1   _SFR_IO8(0x16)
149#define ICF1    5
150#define OCF1C   3
151#define OCF1B   2
152#define OCF1A   1
153#define TOV1    0
154
155/* Reserved [0x17..0x1A] */
156
157#define PCIFR   _SFR_IO8(0x1B)
158#define PCIF1   1
159#define PCIF0   0
160
161#define EIFR    _SFR_IO8(0x1C)
162#define INTF7   7
163#define INTF6   6
164#define INTF5   5
165#define INTF4   4
166#define INTF3   3
167#define INTF2   2
168#define INTF1   1
169#define INTF0   0
170
171#define EIMSK   _SFR_IO8(0x1D)
172#define INT7    7
173#define INT6    6
174#define INT5    5
175#define INT4    4
176#define INT3    3
177#define INT2    2
178#define INT1    1
179#define INT0    0
180
181#define GPIOR0  _SFR_IO8(0x1E)
182
183#define EECR    _SFR_IO8(0x1F)
184#define EEPM1   5
185#define EEPM0   4
186#define EERIE   3
187#define EEMPE   2
188#define EEPE    1
189#define EERE    0
190
191#define EEDR    _SFR_IO8(0x20)
192
193#define EEAR    _SFR_IO16(0x21)
194#define EEARL   _SFR_IO8(0x21)
195#define EEARH   _SFR_IO8(0x22)
196
197/* 6-char sequence denoting where to find the EEPROM registers in memory space.
198   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
199   subroutines.
200   First two letters:  EECR address.
201   Second two letters: EEDR address.
202   Last two letters:   EEAR address.  */
203#define __EEPROM_REG_LOCATIONS__ 1F2021
204
205#define GTCCR   _SFR_IO8(0x23)
206#define TSM     7
207#define PSRASY  1
208#define PSRSYNC 0
209
210#define TCCR0A  _SFR_IO8(0x24)
211#define COM0A1  7
212#define COM0A0  6
213#define COM0B1  5
214#define COM0B0  4
215#define WGM01   1
216#define WGM00   0
217
218#define TCCR0B  _SFR_IO8(0x25)
219#define FOC0A   7
220#define FOC0B   6
221#define WGM02   3
222#define CS02    2
223#define CS01    1
224#define CS00    0
225
226#define TCNT0   _SFR_IO8(0X26)
227
228#define OCR0A   _SFR_IO8(0x27)
229
230#define OCR0B   _SFR_IO8(0X28)
231
232#define PLLCSR  _SFR_IO8(0x29)
233#define PLLP2   4
234#define PLLP1   3
235#define PLLP0   2
236#define PLLE    1
237#define PLOCK   0
238
239#define GPIOR1  _SFR_IO8(0x2A)
240
241#define GPIOR2  _SFR_IO8(0x2B)
242
243#define SPCR    _SFR_IO8(0x2C)
244#define SPIE    7
245#define SPE     6
246#define DORD    5
247#define MSTR    4
248#define CPOL    3
249#define CPHA    2
250#define SPR1    1
251#define SPR0    0
252
253#define SPSR    _SFR_IO8(0x2D)
254#define SPIF    7
255#define WCOL    6
256#define SPI2X   0
257
258#define SPDR    _SFR_IO8(0x2E)
259
260/* Reserved [0x2F] */
261
262#define ACSR    _SFR_IO8(0x30)
263#define ACD     7
264#define ACBG    6
265#define ACO     5
266#define ACI     4
267#define ACIE    3
268#define ACIC    2
269#define ACIS1   1
270#define ACIS0   0
271
272#define DWDR    _SFR_IO8(0x31)
273#define IDRD    7
274
275/* Reserved [0x32] */
276
277#define SMCR    _SFR_IO8(0x33)
278#define SM2     3
279#define SM1     2
280#define SM0     1
281#define SE      0
282
283#define MCUSR   _SFR_IO8(0x34)
284#define USBRF   5
285#define WDRF    3
286#define BORF    2
287#define EXTRF   1
288#define PORF    0
289
290#define MCUCR   _SFR_IO8(0x35)
291#define IVSEL   1
292#define IVCE    0
293
294/* Reserved [0x36] */
295
296#define SPMCSR  _SFR_IO8(0x37)
297#define SPMIE   7
298#define RWWSB   6
299#define SIGRD   5
300#define RWWSRE  4
301#define BLBSET  3
302#define PGWRT   2
303#define PGERS   1
304#define SPMEN   0
305
306/* Reserved [0x38..0x3C] */
307
308/* SP [0x3D..0x3E] */
309/* SREG [0x3F] */
310
311#define WDTCSR  _SFR_MEM8(0x60)
312#define WDIF    7
313#define WDIE    6
314#define WDP3    5
315#define WDCE    4
316#define WDE     3
317#define WDP2    2
318#define WDP1    1
319#define WDP0    0
320
321#define CLKPR   _SFR_MEM8(0x61)
322#define CLKPCE  7
323#define CLKPS3  3
324#define CLKPS2  2
325#define CLKPS1  1
326#define CLKPS0  0
327
328#define WDTCKD  _SFR_MEM8(0x62)
329#define WDEWIF  3
330#define WDEWIE  2
331#define WCLKD1  1
332#define WCLKD0  0
333
334#define REGCR   _SFR_MEM8(0x63)
335#define REGDIS  0
336
337#define PRR0    _SFR_MEM8(0x64)
338#define PRTIM0  5
339#define PRTIM1  3
340#define PRSPI   2
341
342#define PRR1    _SFR_MEM8(0x65)
343#define PRUSB   7
344#define PRUSART1 0
345
346#define OSCCAL  _SFR_MEM8(0x66)
347
348/* Reserved [0x67] */
349
350#define PCICR   _SFR_MEM8(0x68)
351#define PCIE1   1
352#define PCIE0   0
353
354#define EICRA   _SFR_MEM8(0x69)
355#define ISC31   7
356#define ISC30   6
357#define ISC21   5
358#define ISC20   4
359#define ISC11   3
360#define ISC10   2
361#define ISC01   1
362#define ISC00   0
363
364#define EICRB   _SFR_MEM8(0x6A)
365#define ISC71   7
366#define ISC70   6
367#define ISC61   5
368#define ISC60   4
369#define ISC51   3
370#define ISC50   2
371#define ISC41   1
372#define ISC40   0
373
374#define PCMSK0  _SFR_MEM8(0x6B)
375#define PCINT7  7
376#define PCINT6  6
377#define PCINT5  5
378#define PCINT4  4
379#define PCINT3  3
380#define PCINT2  2
381#define PCINT1  1
382#define PCINT0  0
383
384#define PCMSK1  _SFR_MEM8(0x6C)
385#define PCINT12 4
386#define PCINT11 3
387#define PCINT10 2
388#define PCINT9  1
389#define PCINT8  0
390
391/* Reserved [0x6D] */
392
393#define TIMSK0  _SFR_MEM8(0x6E)
394#define OCIE0B  2
395#define OCIE0A  1
396#define TOIE0   0
397
398#define TIMSK1  _SFR_MEM8(0x6F)
399#define ICIE1   5
400#define OCIE1C  3
401#define OCIE1B  2
402#define OCIE1A  1
403#define TOIE1   0
404
405/* Reserved [0x70..0x7F] */
406
407#define TCCR1A  _SFR_MEM8(0x80)
408#define COM1A1  7
409#define COM1A0  6
410#define COM1B1  5
411#define COM1B0  4
412#define COM1C1  3
413#define COM1C0  2
414#define WGM11   1
415#define WGM10   0
416
417#define TCCR1B  _SFR_MEM8(0x81)
418#define ICNC1   7
419#define ICES1   6
420#define WGM13   4
421#define WGM12   3
422#define CS12    2
423#define CS11    1
424#define CS10    0
425
426#define TCCR1C  _SFR_MEM8(0x82)
427#define FOC1A   7
428#define FOC1B   6
429#define FOC1C   5
430
431/* Reserved [0x83] */
432
433/* Combine TCNT1L and TCNT1H */
434#define TCNT1   _SFR_MEM16(0x84)
435
436#define TCNT1L  _SFR_MEM8(0x84)
437#define TCNT1H  _SFR_MEM8(0x85)
438
439/* Combine ICR1L and ICR1H */
440#define ICR1    _SFR_MEM16(0x86)
441
442#define ICR1L   _SFR_MEM8(0x86)
443#define ICR1H   _SFR_MEM8(0x87)
444
445/* Combine OCR1AL and OCR1AH */
446#define OCR1A   _SFR_MEM16(0x88)
447
448#define OCR1AL  _SFR_MEM8(0x88)
449#define OCR1AH  _SFR_MEM8(0x89)
450
451/* Combine OCR1BL and OCR1BH */
452#define OCR1B   _SFR_MEM16(0x8A)
453
454#define OCR1BL  _SFR_MEM8(0x8A)
455#define OCR1BH  _SFR_MEM8(0x8B)
456
457/* Combine OCR1CL and OCR1CH */
458#define OCR1C   _SFR_MEM16(0x8C)
459
460#define OCR1CL  _SFR_MEM8(0x8C)
461#define OCR1CH  _SFR_MEM8(0x8D)
462
463/* Reserved [0x8E..0xC7] */
464
465#define UCSR1A  _SFR_MEM8(0xC8)
466#define RXC1    7
467#define TXC1    6
468#define UDRE1   5
469#define FE1     4
470#define DOR1    3
471#define UPE1    2
472#define U2X1    1
473#define MPCM1   0
474
475#define UCSR1B  _SFR_MEM8(0XC9)
476#define RXCIE1  7
477#define TXCIE1  6
478#define UDRIE1  5
479#define RXEN1   4
480#define TXEN1   3
481#define UCSZ12  2
482#define RXB81   1
483#define TXB81   0
484
485#define UCSR1C  _SFR_MEM8(0xCA)
486#define UMSEL11 7
487#define UMSEL10 6
488#define UPM11   5
489#define UPM10   4
490#define USBS1   3
491#define UCSZ11  2
492#define UCSZ10  1
493#define UCPOL1  0
494
495#define UCSR1D  _SFR_MEM8(0xCB)
496#define CTSEN   1
497#define RTSEN   0
498
499/* Combine UBRR1L and UBRR1H */
500#define UBRR1   _SFR_MEM16(0xCC)
501
502#define UBRR1L  _SFR_MEM8(0xCC)
503#define UBRR1H  _SFR_MEM8(0xCD)
504
505#define UDR1    _SFR_MEM8(0XCE)
506
507/* Reserved [0xCF] */
508
509#define CKSEL0  _SFR_MEM8(0XD0)
510#define RCSUT1  7
511#define RCSUT0  6
512#define EXSUT1  5
513#define EXSUT0  4
514#define RCE     3
515#define EXTE    2
516#define CLKS    0
517
518#define CKSEL1  _SFR_MEM8(0XD1)
519#define RCCKSEL3 7
520#define RCCKSEL2 6
521#define RCCKSEL1 5
522#define RCCKSEL0 4
523#define EXCKSEL3 3
524#define EXCKSEL2 2
525#define EXCKSEL1 1
526#define EXCKSEL0 0
527
528#define CKSTA   _SFR_MEM8(0XD2)
529#define RCON    1
530#define EXTON   0
531
532/* Reserved [0xD3..0xD7] */
533
534#define USBCON  _SFR_MEM8(0XD8)
535#define USBE    7
536#define FRZCLK  5
537
538/* Reserved [0xD9..0xDA] */
539
540/* Combine UDPADDL and UDPADDH */
541#define UDPADD  _SFR_MEM16(0xDB)
542
543#define UDPADDL _SFR_MEM8(0xDB)
544#define UDPADDH _SFR_MEM8(0xDC)
545#define DPACC   7
546
547/* Reserved [0xDD..0xDF] */
548
549#define UDCON   _SFR_MEM8(0XE0)
550#define RSTCPU  2
551#define RMWKUP  1
552#define DETACH  0
553
554#define UDINT   _SFR_MEM8(0XE1)
555#define UPRSMI  6
556#define EORSMI  5
557#define WAKEUPI 4
558#define EORSTI  3
559#define SOFI    2
560#define SUSPI   0
561
562#define UDIEN   _SFR_MEM8(0XE2)
563#define UPRSME  6
564#define EORSME  5
565#define WAKEUPE 4
566#define EORSTE  3
567#define SOFE    2
568#define SUSPE   0
569
570#define UDADDR  _SFR_MEM8(0XE3)
571#define ADDEN   7
572
573/* Combine UDFNUML and UDFNUMH */
574#define UDFNUM  _SFR_MEM16(0xE4)
575
576#define UDFNUML _SFR_MEM8(0xE4)
577#define UDFNUMH _SFR_MEM8(0xE5)
578
579#define UDMFN   _SFR_MEM8(0XE6)
580#define FNCERR  4
581
582/* Reserved [0xE7] */
583
584#define UEINTX  _SFR_MEM8(0XE8)
585#define FIFOCON 7
586#define NAKINI  6
587#define RWAL    5
588#define NAKOUTI 4
589#define RXSTPI  3
590#define RXOUTI  2
591#define STALLEDI 1
592#define TXINI   0
593
594#define UENUM   _SFR_MEM8(0XE9)
595#define EPNUM2  2
596#define EPNUM1  1
597#define EPNUM0  0
598
599#define UERST   _SFR_MEM8(0XEA)
600#define EPRST4  4
601#define EPRST3  3
602#define EPRST2  2
603#define EPRST1  1
604#define EPRST0  0
605
606#define UECONX  _SFR_MEM8(0XEB)
607#define STALLRQ 5
608#define STALLRQC 4
609#define RSTDT   3
610#define EPEN    0
611
612#define UECFG0X _SFR_MEM8(0XEC)
613#define EPTYPE1 7
614#define EPTYPE0 6
615#define EPDIR   0
616
617#define UECFG1X  _SFR_MEM8(0XED)
618#define EPSIZE2 6
619#define EPSIZE1 5
620#define EPSIZE0 4
621#define EPBK1   3
622#define EPBK0   2
623#define ALLOC   1
624
625#define UESTA0X _SFR_MEM8(0XEE)
626#define CFGOK   7
627#define OVERFI  6
628#define UNDERFI 5
629#define DTSEQ1  3
630#define DTSEQ0  2
631#define NBUSYBK1 1
632#define NBUSYBK0 0
633
634#define UESTA1X _SFR_MEM8(0XEF)
635#define CTRLDIR 2
636#define CURRBK1 1
637#define CURRBK0 0
638
639#define UEIENX  _SFR_MEM8(0XF0)
640#define FLERRE  7
641#define NAKINE  6
642#define NAKOUTE 4
643#define RXSTPE  3
644#define RXOUTE  2
645#define STALLEDE 1
646#define TXINE   0
647
648#define UEDATX  _SFR_MEM8(0XF1)
649
650#define UEBCLX  _SFR_MEM8(0xF2)
651
652/* Reserved [0xF3] */
653
654#define UEINT   _SFR_MEM8(0XF4)
655#define EPINT4  4
656#define EPINT3  3
657#define EPINT2  2
658#define EPINT1  1
659#define EPINT0  0
660
661/* Reserved [0xF5..0xF9] */
662
663#define PS2CON  _SFR_MEM8(0XFA)
664#define PS2EN   0
665
666#define UPOE    _SFR_MEM8(0XFB)
667#define UPWE1   7
668#define UPWE0   6
669#define UPDRV1  5
670#define UPDRV0  4
671#define SCKI    3
672#define DATAI   2
673#define DPI     1
674#define DMI     0
675
676/* Reserved [0xFC..0xFF] */
677
678/* Interrupt vectors */
679
680/* External Interrupt Request 0 */
681#define INT0_vect                       _VECTOR(1)
682
683/* External Interrupt Request 1 */
684#define INT1_vect                       _VECTOR(2)
685
686/* External Interrupt Request 2 */
687#define INT2_vect                       _VECTOR(3)
688
689/* External Interrupt Request 3 */
690#define INT3_vect                       _VECTOR(4)
691
692/* External Interrupt Request 4 */
693#define INT4_vect                       _VECTOR(5)
694
695/* External Interrupt Request 5 */
696#define INT5_vect                       _VECTOR(6)
697
698/* External Interrupt Request 6 */
699#define INT6_vect                       _VECTOR(7)
700
701/* External Interrupt Request 7 */
702#define INT7_vect                       _VECTOR(8)
703
704/* Pin Change Interrupt Request 0 */
705#define PCINT0_vect                     _VECTOR(9)
706
707/* Pin Change Interrupt Request 1 */
708#define PCINT1_vect                     _VECTOR(10)
709
710/* USB General Interrupt Request */
711#define USB_GEN_vect                    _VECTOR(11)
712
713/* USB Endpoint/Pipe Interrupt Communication Request */
714#define USB_COM_vect                    _VECTOR(12)
715
716/* Watchdog Time-out Interrupt */
717#define WDT_vect                        _VECTOR(13)
718
719/* Timer/Counter2 Capture Event */
720#define TIMER1_CAPT_vect                _VECTOR(14)
721
722/* Timer/Counter2 Compare Match B */
723#define TIMER1_COMPA_vect               _VECTOR(15)
724
725/* Timer/Counter2 Compare Match B */
726#define TIMER1_COMPB_vect               _VECTOR(16)
727
728/* Timer/Counter2 Compare Match C */
729#define TIMER1_COMPC_vect               _VECTOR(17)
730
731/* Timer/Counter1 Overflow */
732#define TIMER1_OVF_vect                 _VECTOR(18)
733
734/* Timer/Counter0 Compare Match A */
735#define TIMER0_COMPA_vect               _VECTOR(19)
736
737/* Timer/Counter0 Compare Match B */
738#define TIMER0_COMPB_vect               _VECTOR(20)
739
740/* Timer/Counter0 Overflow */
741#define TIMER0_OVF_vect                 _VECTOR(21)
742
743/* SPI Serial Transfer Complete */
744#define SPI_STC_vect                    _VECTOR(22)
745
746/* USART1, Rx Complete */
747#define USART1_RX_vect                  _VECTOR(23)
748
749/* USART1 Data register Empty */
750#define USART1_UDRE_vect                _VECTOR(24)
751
752/* USART1, Tx Complete */
753#define USART1_TX_vect                  _VECTOR(25)
754
755/* Analog Comparator */
756#define ANALOG_COMP_vect                _VECTOR(26)
757
758/* EEPROM Ready */
759#define EE_READY_vect                   _VECTOR(27)
760
761/* Store Program Memory Read */
762#define SPM_READY_vect                  _VECTOR(28)
763
764#define _VECTORS_SIZE 116
765
766#endif  /* _AVR_IOUSBXX2_H_ */
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