1 | /* Copyright (c) 2006, 2007 Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | |
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32 | /* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ |
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33 | |
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34 | /* This file should only be included from <avr/io.h>, never directly. */ |
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35 | |
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36 | #ifndef _AVR_IO_H_ |
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37 | # error "Include <avr/io.h> instead of this file." |
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38 | #endif |
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39 | |
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40 | #ifndef _AVR_IOXXX_H_ |
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41 | # define _AVR_IOXXX_H_ "iotnx61.h" |
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42 | #else |
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43 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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44 | #endif |
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45 | |
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46 | #ifndef _AVR_IOTNx61_H_ |
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47 | #define _AVR_IOTNx61_H_ 1 |
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48 | |
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49 | /* Registers and associated bit numbers */ |
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50 | |
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51 | #define TCCR1E _SFR_IO8(0x00) |
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52 | #define OC1OE0 0 |
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53 | #define OC1OE1 1 |
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54 | #define OC1OE2 2 |
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55 | #define OC1OE3 3 |
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56 | #define OC1OE4 4 |
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57 | #define OC1OE5 5 |
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58 | |
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59 | #define DIDR0 _SFR_IO8(0x01) |
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60 | #define ADC0D 0 |
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61 | #define ADC1D 1 |
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62 | #define ADC2D 2 |
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63 | #define AREFD 3 |
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64 | #define ADC3D 4 |
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65 | #define ADC4D 5 |
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66 | #define ADC5D 6 |
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67 | #define ADC6D 7 |
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68 | |
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69 | #define DIDR1 _SFR_IO8(0x02) |
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70 | #define ADC7D 4 |
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71 | #define ADC8D 5 |
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72 | #define ADC9D 6 |
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73 | #define ADC10D 7 |
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74 | |
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75 | #define ADCSRB _SFR_IO8(0x03) |
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76 | #define ADTS0 0 |
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77 | #define ADTS1 1 |
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78 | #define ADTS2 2 |
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79 | #define MUX5 3 |
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80 | #define REFS2 4 |
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81 | #define IRP 5 |
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82 | #define GSEL 6 |
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83 | #define BIN 7 |
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84 | |
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85 | #define ADCW _SFR_IO16(0x04) |
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86 | #ifndef __ASSEMBLER__ |
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87 | #define ADC _SFR_IO16(0x04) |
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88 | #endif |
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89 | |
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90 | #define ADCL _SFR_IO8(0x04) |
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91 | #define ADCH _SFR_IO8(0x05) |
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92 | |
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93 | #define ADCSRA _SFR_IO8(0x06) |
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94 | #define ADPS0 0 |
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95 | #define ADPS1 1 |
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96 | #define ADPS2 2 |
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97 | #define ADIE 3 |
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98 | #define ADIF 4 |
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99 | #define ADATE 5 |
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100 | #define ADSC 6 |
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101 | #define ADEN 7 |
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102 | |
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103 | #define ADMUX _SFR_IO8(0x07) |
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104 | #define MUX0 0 |
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105 | #define MUX1 1 |
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106 | #define MUX2 2 |
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107 | #define MUX3 3 |
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108 | #define MUX4 4 |
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109 | #define ADLAR 5 |
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110 | #define REFS0 6 |
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111 | #define REFS1 7 |
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112 | |
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113 | #define ACSRA _SFR_IO8(0x08) |
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114 | #define ACIS0 0 |
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115 | #define ACIS1 1 |
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116 | #define ACME 2 |
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117 | #define ACIE 3 |
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118 | #define ACI 4 |
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119 | #define ACO 5 |
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120 | #define ACBG 6 |
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121 | #define ACD 7 |
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122 | |
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123 | #define ACSRB _SFR_IO8(0x09) |
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124 | #define ACM0 0 |
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125 | #define ACM1 1 |
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126 | #define ACM2 2 |
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127 | #define HLEV 6 |
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128 | #define HSEL 7 |
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129 | |
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130 | #define GPIOR0 _SFR_IO8(0x0A) |
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131 | |
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132 | #define GPIOR1 _SFR_IO8(0x0B) |
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133 | |
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134 | #define GPIOR2 _SFR_IO8(0x0C) |
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135 | |
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136 | #define USICR _SFR_IO8(0x0D) |
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137 | #define USITC 0 |
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138 | #define USICLK 1 |
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139 | #define USICS0 2 |
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140 | #define USICS1 3 |
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141 | #define USIWM0 4 |
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142 | #define USIWM1 5 |
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143 | #define USIOIE 6 |
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144 | #define USISIE 7 |
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145 | |
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146 | #define USISR _SFR_IO8(0x0E) |
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147 | #define USICNT0 0 |
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148 | #define USICNT1 1 |
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149 | #define USICNT2 2 |
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150 | #define USICNT3 3 |
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151 | #define USIDC 4 |
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152 | #define USIPF 5 |
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153 | #define USIOIF 6 |
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154 | #define USISIF 7 |
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155 | |
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156 | #define USIDR _SFR_IO8(0x0F) |
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157 | |
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158 | #define USIBR _SFR_IO8(0x10) |
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159 | |
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160 | #define USIPP _SFR_IO8(0x11) |
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161 | #define USIPOS 0 |
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162 | |
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163 | #define OCR0B _SFR_IO8(0x12) |
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164 | |
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165 | #define OCR0A _SFR_IO8(0x13) |
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166 | |
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167 | #define TCNT0H _SFR_IO8(0x14) |
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168 | |
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169 | #define TCCR0A _SFR_IO8(0x15) |
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170 | #define WGM00 0 |
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171 | #define ACIC0 3 |
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172 | #define ICES0 4 |
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173 | #define ICNC0 5 |
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174 | #define ICEN0 6 |
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175 | #define TCW0 7 |
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176 | |
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177 | #define PINB _SFR_IO8(0x16) |
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178 | #define PINB0 0 |
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179 | #define PINB1 1 |
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180 | #define PINB2 2 |
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181 | #define PINB3 3 |
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182 | #define PINB4 4 |
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183 | #define PINB5 5 |
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184 | #define PINB6 6 |
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185 | #define PINB7 7 |
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186 | |
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187 | #define DDRB _SFR_IO8(0x17) |
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188 | #define DDB0 0 |
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189 | #define DDB1 1 |
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190 | #define DDB2 2 |
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191 | #define DDB3 3 |
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192 | #define DDB4 4 |
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193 | #define DDB5 5 |
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194 | #define DDB6 6 |
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195 | #define DDB7 7 |
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196 | |
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197 | #define PORTB _SFR_IO8(0x18) |
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198 | #define PB0 0 |
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199 | #define PB1 1 |
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200 | #define PB2 2 |
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201 | #define PB3 3 |
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202 | #define PB4 4 |
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203 | #define PB5 5 |
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204 | #define PB6 6 |
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205 | #define PB7 7 |
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206 | |
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207 | #define PINA _SFR_IO8(0x19) |
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208 | #define PINA0 0 |
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209 | #define PINA1 1 |
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210 | #define PINA2 2 |
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211 | #define PINA3 3 |
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212 | #define PINA4 4 |
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213 | #define PINA5 5 |
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214 | #define PINA6 6 |
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215 | #define PINA7 7 |
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216 | |
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217 | #define DDRA _SFR_IO8(0x1A) |
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218 | #define DDA0 0 |
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219 | #define DDA1 1 |
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220 | #define DDA2 2 |
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221 | #define DDA3 3 |
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222 | #define DDA4 4 |
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223 | #define DDA5 5 |
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224 | #define DDA6 6 |
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225 | #define DDA7 7 |
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226 | |
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227 | #define PORTA _SFR_IO8(0x1B) |
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228 | #define PA0 0 |
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229 | #define PA1 1 |
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230 | #define PA2 2 |
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231 | #define PA3 3 |
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232 | #define PA4 4 |
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233 | #define PA5 5 |
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234 | #define PA6 6 |
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235 | #define PA7 7 |
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236 | |
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237 | /* EEPROM Control Register */ |
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238 | #define EECR _SFR_IO8(0x1C) |
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239 | #define EERE 0 |
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240 | #define EEPE 1 |
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241 | #define EEMPE 2 |
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242 | #define EERIE 3 |
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243 | #define EEPM0 4 |
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244 | #define EEPM1 5 |
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245 | |
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246 | /* EEPROM Data Register */ |
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247 | #define EEDR _SFR_IO8(0x1D) |
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248 | |
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249 | /* EEPROM Address Register */ |
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250 | #define EEAR _SFR_IO16(0x1E) |
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251 | #define EEARL _SFR_IO8(0x1E) |
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252 | #define EEARH _SFR_IO8(0x1F) |
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253 | |
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254 | #define DWDR _SFR_IO8(0x20) |
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255 | |
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256 | #define WDTCR _SFR_IO8(0x21) |
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257 | #define WDP0 0 |
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258 | #define WDP1 1 |
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259 | #define WDP2 2 |
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260 | #define WDE 3 |
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261 | #define WDCE 4 |
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262 | #define WDP3 5 |
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263 | #define WDIE 6 |
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264 | #define WDIF 7 |
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265 | |
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266 | #define PCMSK1 _SFR_IO8(0x22) |
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267 | #define PCINT8 0 |
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268 | #define PCINT9 1 |
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269 | #define PCINT10 2 |
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270 | #define PCINT11 3 |
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271 | #define PCINT12 4 |
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272 | #define PCINT13 5 |
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273 | #define PCINT14 6 |
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274 | #define PCINT15 7 |
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275 | |
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276 | #define PCMSK0 _SFR_IO8(0x23) |
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277 | #define PCINT0 0 |
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278 | #define PCINT1 1 |
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279 | #define PCINT2 2 |
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280 | #define PCINT3 3 |
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281 | #define PCINT4 4 |
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282 | #define PCINT5 5 |
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283 | #define PCINT6 6 |
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284 | #define PCINT7 7 |
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285 | |
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286 | #define DT1 _SFR_IO8(0x24) |
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287 | #define DT1L0 0 |
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288 | #define DT1L1 1 |
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289 | #define DT1L2 2 |
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290 | #define DT1L3 3 |
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291 | #define DT1H0 4 |
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292 | #define DT1H1 5 |
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293 | #define DT1H2 6 |
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294 | #define DT1H3 7 |
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295 | |
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296 | #define TC1H _SFR_IO8(0x25) |
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297 | #define TC18 0 |
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298 | #define TC19 1 |
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299 | |
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300 | #define TCCR1D _SFR_IO8(0x26) |
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301 | #define WGM10 0 |
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302 | #define WGM11 1 |
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303 | #define FPF1 2 |
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304 | #define FPAC1 3 |
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305 | #define FPES1 4 |
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306 | #define FPNC1 5 |
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307 | #define FPEN1 6 |
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308 | #define FPIE1 7 |
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309 | |
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310 | #define TCCR1C _SFR_IO8(0x27) |
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311 | #define PWM1D 0 |
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312 | #define FOC1D 1 |
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313 | #define COM1D0 2 |
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314 | #define COM1D1 3 |
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315 | #define COM1B0S 4 |
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316 | #define COM1B1S 5 |
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317 | #define COM1A0S 6 |
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318 | #define COM1A1S 7 |
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319 | |
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320 | #define CLKPR _SFR_IO8(0x28) |
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321 | #define CLKPS0 0 |
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322 | #define CLKPS1 1 |
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323 | #define CLKPS2 2 |
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324 | #define CLKPS3 3 |
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325 | #define CLKPCE 7 |
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326 | |
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327 | #define PLLCSR _SFR_IO8(0x29) |
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328 | #define PLOCK 0 |
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329 | #define PLLE 1 |
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330 | #define PCKE 2 |
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331 | #define LSM 7 |
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332 | |
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333 | #define OCR1D _SFR_IO8(0x2A) |
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334 | |
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335 | #define OCR1C _SFR_IO8(0x2B) |
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336 | |
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337 | #define OCR1B _SFR_IO8(0x2C) |
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338 | |
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339 | #define OCR1A _SFR_IO8(0x2D) |
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340 | |
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341 | #define TCNT1 _SFR_IO8(0x2E) |
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342 | |
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343 | #define TCCR1B _SFR_IO8(0x2F) |
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344 | #define CS10 0 |
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345 | #define CS11 1 |
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346 | #define CS12 2 |
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347 | #define CS13 3 |
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348 | #define DTPS10 4 |
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349 | #define DTPS11 5 |
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350 | #define PSR1 6 |
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351 | #define PWM1X 7 |
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352 | |
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353 | #define TCCR1A _SFR_IO8(0x30) |
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354 | #define PWM1B 0 |
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355 | #define PWM1A 1 |
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356 | #define FOC1B 2 |
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357 | #define FOC1A 3 |
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358 | #define COM1B0 4 |
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359 | #define COM1B1 5 |
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360 | #define COM1A0 6 |
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361 | #define COM1A1 7 |
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362 | |
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363 | #define OSCCAL _SFR_IO8(0x31) |
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364 | |
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365 | #define TCNT0L _SFR_IO8(0x32) |
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366 | |
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367 | #define TCCR0B _SFR_IO8(0x33) |
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368 | #define CS00 0 |
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369 | #define CS01 1 |
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370 | #define CS02 2 |
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371 | #define PSR0 3 |
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372 | #define TSM 4 |
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373 | |
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374 | #define MCUSR _SFR_IO8(0x34) |
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375 | #define PORF 0 |
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376 | #define EXTRF 1 |
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377 | #define BORF 2 |
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378 | #define WDRF 3 |
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379 | |
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380 | #define MCUCR _SFR_IO8(0x35) |
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381 | #define ISC00 0 |
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382 | #define ISC01 1 |
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383 | #define SM0 3 |
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384 | #define SM1 4 |
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385 | #define SE 5 |
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386 | #define PUD 6 |
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387 | |
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388 | #define PRR _SFR_IO8(0x36) |
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389 | #define PRADC 0 |
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390 | #define PRUSI 1 |
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391 | #define PRTIM0 2 |
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392 | #define PRTIM1 3 |
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393 | |
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394 | #define SPMCSR _SFR_IO8(0x37) |
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395 | #define SPMEN 0 |
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396 | #define PGERS 1 |
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397 | #define PGWRT 2 |
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398 | #define RFLB 3 |
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399 | #define CTPB 4 |
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400 | |
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401 | #define TIFR _SFR_IO8(0x38) |
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402 | #define ICF0 0 |
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403 | #define TOV0 1 |
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404 | #define TOV1 2 |
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405 | #define OCF0B 3 |
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406 | #define OCF0A 4 |
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407 | #define OCF1B 5 |
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408 | #define OCF1A 6 |
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409 | #define OCF1D 7 |
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410 | |
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411 | #define TIMSK _SFR_IO8(0x39) |
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412 | #define TICIE0 0 |
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413 | #define TOIE0 1 |
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414 | #define TOIE1 2 |
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415 | #define OCIE0B 3 |
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416 | #define OCIE0A 4 |
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417 | #define OCIE1B 5 |
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418 | #define OCIE1A 6 |
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419 | #define OCIE1D 7 |
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420 | |
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421 | #define GIFR _SFR_IO8(0x3A) |
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422 | #define PCIF 5 |
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423 | #define INTF0 6 |
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424 | #define INTF1 7 |
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425 | |
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426 | #define GIMSK _SFR_IO8(0x3B) |
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427 | #define PCIE0 4 |
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428 | #define PCIE1 5 |
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429 | #define INT0 6 |
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430 | #define INT1 7 |
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431 | |
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432 | /* Reserved [0x3C] */ |
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433 | |
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434 | /* 0x3D..0x3E SP [defined in <avr/io.h>] */ |
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435 | /* 0x3F SREG [defined in <avr/io.h>] */ |
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436 | |
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437 | |
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438 | /* Interrupt vectors */ |
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439 | /* Interrupt vector 0 is the reset vector. */ |
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440 | /* External Interrupt 0 */ |
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441 | #define INT0_vect _VECTOR(1) |
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442 | #define SIG_INTERRUPT0 _VECTOR(1) |
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443 | |
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444 | /* Pin Change Interrupt */ |
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445 | #define PCINT_vect _VECTOR(2) |
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446 | #define SIG_PIN_CHANGE _VECTOR(2) |
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447 | |
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448 | /* Timer/Counter1 Compare Match 1A */ |
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449 | #define TIMER1_COMPA_vect _VECTOR(3) |
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450 | #define SIG_OUTPUT_COMPARE1A _VECTOR(3) |
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451 | |
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452 | /* Timer/Counter1 Compare Match 1B */ |
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453 | #define TIMER1_COMPB_vect _VECTOR(4) |
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454 | #define SIG_OUTPUT_COMPARE1B _VECTOR(4) |
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455 | |
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456 | /* Timer/Counter1 Overflow */ |
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457 | #define TIMER1_OVF_vect _VECTOR(5) |
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458 | #define SIG_OVERFLOW1 _VECTOR(5) |
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459 | |
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460 | /* Timer/Counter0 Overflow */ |
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461 | #define TIMER0_OVF_vect _VECTOR(6) |
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462 | #define SIG_OVERFLOW0 _VECTOR(6) |
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463 | |
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464 | /* USI Start */ |
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465 | #define USI_START_vect _VECTOR(7) |
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466 | #define SIG_USI_START _VECTOR(7) |
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467 | |
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468 | /* USI Overflow */ |
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469 | #define USI_OVF_vect _VECTOR(8) |
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470 | #define SIG_USI_OVERFLOW _VECTOR(8) |
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471 | |
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472 | /* EEPROM Ready */ |
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473 | #define EE_RDY_vect _VECTOR(9) |
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474 | #define SIG_EEPROM_READY _VECTOR(9) |
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475 | |
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476 | /* Analog Comparator */ |
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477 | #define ANA_COMP_vect _VECTOR(10) |
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478 | #define SIG_ANA_COMP _VECTOR(10) |
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479 | #define SIG_COMPARATOR _VECTOR(10) |
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480 | |
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481 | /* ADC Conversion Complete */ |
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482 | #define ADC_vect _VECTOR(11) |
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483 | #define SIG_ADC _VECTOR(11) |
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484 | |
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485 | /* Watchdog Time-Out */ |
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486 | #define WDT_vect _VECTOR(12) |
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487 | #define SIG_WDT _VECTOR(12) |
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488 | |
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489 | /* External Interrupt 1 */ |
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490 | #define INT1_vect _VECTOR(13) |
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491 | #define SIG_INTERRUPT1 _VECTOR(13) |
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492 | |
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493 | /* Timer/Counter0 Compare Match A */ |
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494 | #define TIMER0_COMPA_vect _VECTOR(14) |
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495 | #define SIG_OUTPUT_COMPARE0A _VECTOR(14) |
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496 | |
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497 | /* Timer/Counter0 Compare Match B */ |
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498 | #define TIMER0_COMPB_vect _VECTOR(15) |
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499 | #define SIG_OUTPUT_COMPARE0B _VECTOR(15) |
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500 | |
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501 | /* ADC Conversion Complete */ |
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502 | #define TIMER0_CAPT_vect _VECTOR(16) |
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503 | #define SIG_INPUT_CAPTURE0 _VECTOR(16) |
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504 | |
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505 | /* Timer/Counter1 Compare Match D */ |
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506 | #define TIMER1_COMPD_vect _VECTOR(17) |
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507 | #define SIG_OUTPUT_COMPARE0D _VECTOR(17) |
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508 | |
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509 | /* Timer/Counter1 Fault Protection */ |
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510 | #define FAULT_PROTECTION_vect _VECTOR(18) |
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511 | |
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512 | #define _VECTORS_SIZE 38 |
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513 | |
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514 | #endif /* _AVR_IOTNx61_H_ */ |
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