source: rtems/cpukit/score/cpu/avr/avr/iotnx61.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 10.6 KB
Line 
1/* Copyright (c) 2006, 2007 Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */
34
35/* This file should only be included from <avr/io.h>, never directly. */
36
37#ifndef _AVR_IO_H_
38#  error "Include <avr/io.h> instead of this file."
39#endif
40
41#ifndef _AVR_IOXXX_H_
42#  define _AVR_IOXXX_H_ "iotnx61.h"
43#else
44#  error "Attempt to include more than one <avr/ioXXX.h> file."
45#endif
46
47#ifndef _AVR_IOTNx61_H_
48#define _AVR_IOTNx61_H_ 1
49
50/* Registers and associated bit numbers */
51
52#define TCCR1E  _SFR_IO8(0x00)
53#define OC1OE0  0
54#define OC1OE1  1
55#define OC1OE2  2
56#define OC1OE3  3
57#define OC1OE4  4
58#define OC1OE5  5
59
60#define DIDR0   _SFR_IO8(0x01)
61#define ADC0D   0
62#define ADC1D   1
63#define ADC2D   2
64#define AREFD   3
65#define ADC3D   4
66#define ADC4D   5
67#define ADC5D   6
68#define ADC6D   7
69
70#define DIDR1   _SFR_IO8(0x02)
71#define ADC7D   4
72#define ADC8D   5
73#define ADC9D   6
74#define ADC10D  7
75
76#define ADCSRB  _SFR_IO8(0x03)
77#define ADTS0   0
78#define ADTS1   1
79#define ADTS2   2
80#define MUX5    3
81#define REFS2   4
82#define IRP     5
83#define GSEL    6
84#define BIN     7
85
86#define ADCW    _SFR_IO16(0x04)
87#ifndef __ASSEMBLER__
88#define ADC     _SFR_IO16(0x04)
89#endif
90
91#define ADCL    _SFR_IO8(0x04)
92#define ADCH    _SFR_IO8(0x05)
93
94#define ADCSRA  _SFR_IO8(0x06)
95#define ADPS0   0
96#define ADPS1   1
97#define ADPS2   2
98#define ADIE    3
99#define ADIF    4
100#define ADATE   5
101#define ADSC    6
102#define ADEN    7
103
104#define ADMUX   _SFR_IO8(0x07)
105#define MUX0    0
106#define MUX1    1
107#define MUX2    2
108#define MUX3    3
109#define MUX4    4
110#define ADLAR   5
111#define REFS0   6
112#define REFS1   7
113
114#define ACSRA   _SFR_IO8(0x08)
115#define ACIS0   0
116#define ACIS1   1
117#define ACME    2
118#define ACIE    3
119#define ACI     4
120#define ACO     5
121#define ACBG    6
122#define ACD     7
123
124#define ACSRB   _SFR_IO8(0x09)
125#define ACM0    0
126#define ACM1    1
127#define ACM2    2
128#define HLEV    6
129#define HSEL    7
130
131#define GPIOR0  _SFR_IO8(0x0A)
132
133#define GPIOR1  _SFR_IO8(0x0B)
134
135#define GPIOR2  _SFR_IO8(0x0C)
136
137#define USICR   _SFR_IO8(0x0D)
138#define USITC   0
139#define USICLK  1
140#define USICS0  2
141#define USICS1  3
142#define USIWM0  4
143#define USIWM1  5
144#define USIOIE  6
145#define USISIE  7
146
147#define USISR   _SFR_IO8(0x0E)
148#define USICNT0 0
149#define USICNT1 1
150#define USICNT2 2
151#define USICNT3 3
152#define USIDC   4
153#define USIPF   5
154#define USIOIF  6
155#define USISIF  7
156
157#define USIDR   _SFR_IO8(0x0F)
158
159#define USIBR   _SFR_IO8(0x10)
160
161#define USIPP   _SFR_IO8(0x11)
162#define USIPOS  0
163
164#define OCR0B   _SFR_IO8(0x12)
165
166#define OCR0A   _SFR_IO8(0x13)
167
168#define TCNT0H  _SFR_IO8(0x14)
169
170#define TCCR0A  _SFR_IO8(0x15)
171#define WGM00   0
172#define ACIC0   3
173#define ICES0   4
174#define ICNC0   5
175#define ICEN0   6
176#define TCW0    7
177
178#define PINB    _SFR_IO8(0x16)
179#define PINB0   0
180#define PINB1   1
181#define PINB2   2
182#define PINB3   3
183#define PINB4   4
184#define PINB5   5
185#define PINB6   6
186#define PINB7   7
187
188#define DDRB    _SFR_IO8(0x17)
189#define DDB0    0
190#define DDB1    1
191#define DDB2    2
192#define DDB3    3
193#define DDB4    4
194#define DDB5    5
195#define DDB6    6
196#define DDB7    7
197
198#define PORTB   _SFR_IO8(0x18)
199#define PB0     0
200#define PB1     1
201#define PB2     2
202#define PB3     3
203#define PB4     4
204#define PB5     5
205#define PB6     6
206#define PB7     7
207
208#define PINA    _SFR_IO8(0x19)
209#define PINA0   0
210#define PINA1   1
211#define PINA2   2
212#define PINA3   3
213#define PINA4   4
214#define PINA5   5
215#define PINA6   6
216#define PINA7   7
217
218#define DDRA    _SFR_IO8(0x1A)
219#define DDA0    0
220#define DDA1    1
221#define DDA2    2
222#define DDA3    3
223#define DDA4    4
224#define DDA5    5
225#define DDA6    6
226#define DDA7    7
227
228#define PORTA   _SFR_IO8(0x1B)
229#define PA0     0
230#define PA1     1
231#define PA2     2
232#define PA3     3
233#define PA4     4
234#define PA5     5
235#define PA6     6
236#define PA7     7
237
238/* EEPROM Control Register */
239#define EECR    _SFR_IO8(0x1C)
240#define EERE    0
241#define EEPE    1
242#define EEMPE   2
243#define EERIE   3
244#define EEPM0   4
245#define EEPM1   5
246
247/* EEPROM Data Register */
248#define EEDR    _SFR_IO8(0x1D)
249
250/* EEPROM Address Register */
251#define EEAR    _SFR_IO16(0x1E)
252#define EEARL   _SFR_IO8(0x1E)
253#define EEARH   _SFR_IO8(0x1F)
254
255#define DWDR    _SFR_IO8(0x20)
256
257#define WDTCR   _SFR_IO8(0x21)
258#define WDP0    0
259#define WDP1    1
260#define WDP2    2
261#define WDE     3
262#define WDCE    4
263#define WDP3    5
264#define WDIE    6
265#define WDIF    7
266
267#define PCMSK1  _SFR_IO8(0x22)
268#define PCINT8  0
269#define PCINT9  1
270#define PCINT10 2
271#define PCINT11 3
272#define PCINT12 4
273#define PCINT13 5
274#define PCINT14 6
275#define PCINT15 7
276
277#define PCMSK0  _SFR_IO8(0x23)
278#define PCINT0  0
279#define PCINT1  1
280#define PCINT2  2
281#define PCINT3  3
282#define PCINT4  4
283#define PCINT5  5
284#define PCINT6  6
285#define PCINT7  7
286
287#define DT1     _SFR_IO8(0x24)
288#define DT1L0   0
289#define DT1L1   1
290#define DT1L2   2
291#define DT1L3   3
292#define DT1H0   4
293#define DT1H1   5
294#define DT1H2   6
295#define DT1H3   7
296
297#define TC1H    _SFR_IO8(0x25)
298#define TC18    0
299#define TC19    1
300
301#define TCCR1D  _SFR_IO8(0x26)
302#define WGM10   0
303#define WGM11   1
304#define FPF1    2
305#define FPAC1   3
306#define FPES1   4
307#define FPNC1   5
308#define FPEN1   6
309#define FPIE1   7
310
311#define TCCR1C  _SFR_IO8(0x27)
312#define PWM1D   0
313#define FOC1D   1
314#define COM1D0  2
315#define COM1D1  3
316#define COM1B0S 4
317#define COM1B1S 5
318#define COM1A0S 6
319#define COM1A1S 7
320
321#define CLKPR   _SFR_IO8(0x28)
322#define CLKPS0  0
323#define CLKPS1  1
324#define CLKPS2  2
325#define CLKPS3  3
326#define CLKPCE  7
327
328#define PLLCSR  _SFR_IO8(0x29)
329#define PLOCK   0
330#define PLLE    1
331#define PCKE    2
332#define LSM     7
333
334#define OCR1D   _SFR_IO8(0x2A)
335
336#define OCR1C   _SFR_IO8(0x2B)
337
338#define OCR1B   _SFR_IO8(0x2C)
339
340#define OCR1A   _SFR_IO8(0x2D)
341
342#define TCNT1   _SFR_IO8(0x2E)
343
344#define TCCR1B  _SFR_IO8(0x2F)
345#define CS10    0
346#define CS11    1
347#define CS12    2
348#define CS13    3
349#define DTPS10  4
350#define DTPS11  5
351#define PSR1    6
352#define PWM1X   7
353
354#define TCCR1A  _SFR_IO8(0x30)
355#define PWM1B   0
356#define PWM1A   1
357#define FOC1B   2
358#define FOC1A   3
359#define COM1B0  4
360#define COM1B1  5
361#define COM1A0  6
362#define COM1A1  7
363
364#define OSCCAL  _SFR_IO8(0x31)
365
366#define TCNT0L  _SFR_IO8(0x32)
367
368#define TCCR0B  _SFR_IO8(0x33)
369#define CS00    0
370#define CS01    1
371#define CS02    2
372#define PSR0    3
373#define TSM     4
374
375#define MCUSR   _SFR_IO8(0x34)
376#define PORF    0
377#define EXTRF   1
378#define BORF    2
379#define WDRF    3
380
381#define MCUCR   _SFR_IO8(0x35)
382#define ISC00   0
383#define ISC01   1
384#define SM0     3
385#define SM1     4
386#define SE      5
387#define PUD     6
388
389#define PRR     _SFR_IO8(0x36)
390#define PRADC   0
391#define PRUSI   1
392#define PRTIM0  2
393#define PRTIM1  3
394
395#define SPMCSR  _SFR_IO8(0x37)
396#define SPMEN   0
397#define PGERS   1
398#define PGWRT 2
399#define RFLB 3
400#define CTPB 4
401
402#define TIFR    _SFR_IO8(0x38)
403#define ICF0    0
404#define TOV0    1
405#define TOV1    2
406#define OCF0B   3
407#define OCF0A   4
408#define OCF1B   5
409#define OCF1A   6
410#define OCF1D   7
411
412#define TIMSK   _SFR_IO8(0x39)
413#define TICIE0  0
414#define TOIE0   1
415#define TOIE1   2
416#define OCIE0B  3
417#define OCIE0A  4
418#define OCIE1B  5
419#define OCIE1A  6
420#define OCIE1D  7
421
422#define GIFR    _SFR_IO8(0x3A)
423#define PCIF    5
424#define INTF0   6
425#define INTF1   7
426
427#define GIMSK   _SFR_IO8(0x3B)
428#define PCIE0   4
429#define PCIE1   5
430#define INT0    6
431#define INT1    7
432
433/* Reserved [0x3C] */
434
435/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
436/* 0x3F SREG      [defined in <avr/io.h>] */
437
438
439/* Interrupt vectors */
440/* Interrupt vector 0 is the reset vector. */
441/* External Interrupt 0 */
442#define INT0_vect                       _VECTOR(1)
443#define SIG_INTERRUPT0                  _VECTOR(1)
444
445/* Pin Change Interrupt */
446#define PCINT_vect                      _VECTOR(2)
447#define SIG_PIN_CHANGE                  _VECTOR(2)
448
449/* Timer/Counter1 Compare Match 1A */
450#define TIMER1_COMPA_vect               _VECTOR(3)
451#define SIG_OUTPUT_COMPARE1A            _VECTOR(3)
452
453/* Timer/Counter1 Compare Match 1B */
454#define TIMER1_COMPB_vect               _VECTOR(4)
455#define SIG_OUTPUT_COMPARE1B            _VECTOR(4)
456
457/* Timer/Counter1 Overflow */
458#define TIMER1_OVF_vect                 _VECTOR(5)
459#define SIG_OVERFLOW1                   _VECTOR(5)
460
461/* Timer/Counter0 Overflow */
462#define TIMER0_OVF_vect                 _VECTOR(6)
463#define SIG_OVERFLOW0                   _VECTOR(6)
464
465/* USI Start */
466#define USI_START_vect                  _VECTOR(7)
467#define SIG_USI_START                   _VECTOR(7)
468
469/* USI Overflow */
470#define USI_OVF_vect                    _VECTOR(8)
471#define SIG_USI_OVERFLOW                _VECTOR(8)
472
473/* EEPROM Ready */
474#define EE_RDY_vect                     _VECTOR(9)
475#define SIG_EEPROM_READY                _VECTOR(9)
476
477/* Analog Comparator */
478#define ANA_COMP_vect                   _VECTOR(10)
479#define SIG_ANA_COMP                    _VECTOR(10)
480#define SIG_COMPARATOR                  _VECTOR(10)
481
482/* ADC Conversion Complete */
483#define ADC_vect                        _VECTOR(11)
484#define SIG_ADC                         _VECTOR(11)
485
486/* Watchdog Time-Out */
487#define WDT_vect                        _VECTOR(12)
488#define SIG_WDT                         _VECTOR(12)
489
490/* External Interrupt 1 */
491#define INT1_vect                       _VECTOR(13)
492#define SIG_INTERRUPT1                  _VECTOR(13)
493
494/* Timer/Counter0 Compare Match A */
495#define TIMER0_COMPA_vect               _VECTOR(14)
496#define SIG_OUTPUT_COMPARE0A            _VECTOR(14)
497
498/* Timer/Counter0 Compare Match B */
499#define TIMER0_COMPB_vect               _VECTOR(15)
500#define SIG_OUTPUT_COMPARE0B            _VECTOR(15)
501
502/* ADC Conversion Complete */
503#define TIMER0_CAPT_vect                _VECTOR(16)
504#define SIG_INPUT_CAPTURE0              _VECTOR(16)
505
506/* Timer/Counter1 Compare Match D */
507#define TIMER1_COMPD_vect               _VECTOR(17)
508#define SIG_OUTPUT_COMPARE0D            _VECTOR(17)
509
510/* Timer/Counter1 Fault Protection */
511#define FAULT_PROTECTION_vect           _VECTOR(18)
512
513#define _VECTORS_SIZE 38
514
515#endif  /* _AVR_IOTNx61_H_ */
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