source: rtems/cpukit/score/cpu/avr/avr/iotnx5.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 8.9 KB
Line 
1/* Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */
34
35#ifndef _AVR_IOTNX5_H_
36#define _AVR_IOTNX5_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iotnx5.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52/* Reserved [0x00..0x02] */
53
54#define ADCSRB  _SFR_IO8 (0x03)
55#define BIN     7
56#define ACME    6
57#define IPR     5
58#define ADTS2   2
59#define ADTS1   1
60#define ADTS0   0
61
62#ifndef __ASSEMBLER__
63#define ADC     _SFR_IO16(0x04)
64#endif
65#define ADCW    _SFR_IO16(0x04)
66#define ADCL    _SFR_IO8(0x04)
67#define ADCH    _SFR_IO8(0x05)
68
69#define ADCSRA  _SFR_IO8 (0x06)
70#define ADEN    7
71#define ADSC    6
72#define ADATE   5
73#define ADIF    4
74#define ADIE    3
75#define ADPS2   2
76#define ADPS1   1
77#define ADPS0   0
78
79#define ADMUX   _SFR_IO8(0x07)
80#define REFS1   7
81#define REFS0   6
82#define ADLAR   5
83#define REFS2   4
84#define MUX3    3
85#define MUX2    2
86#define MUX1    1
87#define MUX0    0
88
89#define ACSR    _SFR_IO8(0x08)
90#define ACD     7
91#define ACBG    6
92#define ACO     5
93#define ACI     4
94#define ACIE    3
95#define ACIS1   1
96#define ACIS0   0
97
98/* Reserved [0x09..0x0C] */
99
100#define USICR   _SFR_IO8(0x0D)
101#define USISIE  7
102#define USIOIE  6
103#define USIWM1  5
104#define USIWM0  4
105#define USICS1  3
106#define USICS0  2
107#define USICLK  1
108#define USITC   0
109
110#define USISR   _SFR_IO8(0x0E)
111#define USISIF  7
112#define USIOIF  6
113#define USIPF   5
114#define USIDC   4
115#define USICNT3 3
116#define USICNT2 2
117#define USICNT1 1
118#define USICNT0 0
119
120#define USIDR   _SFR_IO8(0x0F)
121#define USIBR   _SFR_IO8(0x10)
122
123#define GPIOR0  _SFR_IO8(0x11)
124#define GPIOR1  _SFR_IO8(0x12)
125#define GPIOR2  _SFR_IO8(0x13)
126
127#define DIDR0    _SFR_IO8(0x14)
128#define ADC0D   5
129#define ADC2D   4
130#define ADC3D   3
131#define ADC1D   2
132#define AIN1D   1
133#define AIN0D   0
134
135#define PCMSK   _SFR_IO8(0x15)
136#define PCINT5  5
137#define PCINT4  4
138#define PCINT3  3
139#define PCINT2  2
140#define PCINT1  1
141#define PCINT0  0
142
143#define PINB    _SFR_IO8(0x16)
144#define PINB5   5
145#define PINB4   4
146#define PINB3   3
147#define PINB2   2
148#define PINB1   1
149#define PINB0   0
150
151#define DDRB    _SFR_IO8(0x17)
152#define DDB5    5
153#define DDB4    4
154#define DDB3    3
155#define DDB2    2
156#define DDB1    1
157#define DDB0    0
158
159#define PORTB   _SFR_IO8(0x18)
160#define PB5     5
161#define PB4     4
162#define PB3     3
163#define PB2     2
164#define PB1     1
165#define PB0     0
166
167/* Reserved [0x19..0x1B] */
168
169/* EEPROM Control Register EECR */
170#define EECR    _SFR_IO8(0x1C)
171#define EEPM1   5
172#define EEPM0   4
173#define EERIE   3
174#define EEMPE   2
175#define EEPE    1
176#define EERE    0
177
178/* EEPROM Data Register */
179#define EEDR    _SFR_IO8(0x1D)
180
181/* EEPROM Address Register */
182#define EEAR    _SFR_IO16(0x1E)
183#define EEARL   _SFR_IO8(0x1E)
184#define EEARH   _SFR_IO8(0x1F)
185
186#define PRR     _SFR_IO8(0x20)
187#define PRTIM1  3
188#define PRTIM0  2
189#define PRUSI   1
190#define PRADC   0
191
192#define WDTCR   _SFR_IO8(0x21)
193#define WDIF    7
194#define WDIE    6
195#define WDP3    5
196#define WDCE    4
197#define WDE     3
198#define WDP2    2
199#define WDP1    1
200#define WDP0    0
201
202#define DWDR    _SFR_IO8(0x22)
203
204#define DTPS1   _SFR_IO8(0x23)
205#define DTPS11   1
206#define DTPS10   0
207
208#define DT1B    _SFR_IO8(0x24)
209#define DT1BH3  7
210#define DT1BH2  6
211#define DT1BH1  5
212#define DT1BH0  4
213#define DT1BL3  3
214#define DT1BL2  2
215#define DT1BL1  1
216#define DT1BL0  0
217
218#define DT1A    _SFR_IO8(0x25)
219#define DT1AH3  7
220#define DT1AH2  6
221#define DT1AH1  5
222#define DT1AH0  4
223#define DT1AL3  3
224#define DT1AL2  2
225#define DT1AL1  1
226#define DT1AL0  0
227
228#define CLKPR   _SFR_IO8(0x26)
229#define CLKPCE  7
230#define CLKPS3  3
231#define CLKPS2  2
232#define CLKPS1  1
233#define CLKPS0  0
234
235#define PLLCSR  _SFR_IO8(0x27)
236#define LSM     7
237#define PCKE    2
238#define PLLE    1
239#define PLOCK   0
240
241#define OCR0B   _SFR_IO8(0x28)
242
243#define OCR0A   _SFR_IO8(0x29)
244
245#define TCCR0A  _SFR_IO8(0x2A)
246#define COM0A1  7
247#define COM0A0  6
248#define COM0B1  5
249#define COM0B0  4
250#define WGM01   1
251#define WGM00   0
252
253#define OCR1B   _SFR_IO8(0x2B)
254
255#define GTCCR   _SFR_IO8(0x2C)
256#define TSM     7
257#define PWM1B   6
258#define COM1B1  5
259#define COM1B0  4
260#define FOC1B   3
261#define FOC1A   2
262#define PSR1    1
263#define PSR0    0
264
265#define OCR1C   _SFR_IO8(0x2D)
266
267#define OCR1A   _SFR_IO8(0x2E)
268
269#define TCNT1   _SFR_IO8(0x2F)
270
271#define TCCR1   _SFR_IO8(0x30)
272#define CTC1    7
273#define PWM1A   6
274#define COM1A1  5
275#define COM1A0  4
276#define CS13    3
277#define CS12    2
278#define CS11    1
279#define CS10    0
280
281#define OSCCAL  _SFR_IO8(0x31)
282
283#define TCNT0   _SFR_IO8(0x32)
284
285#define TCCR0B  _SFR_IO8(0x33)
286#define FOC0A   7
287#define FOC0B   6
288#define WGM02   3
289#define CS02    2
290#define CS01    1
291#define CS00    0
292
293#define MCUSR   _SFR_IO8(0x34)
294#define WDRF    3
295#define BORF    2
296#define EXTRF   1
297#define PORF    0
298
299#define MCUCR   _SFR_IO8(0x35)
300#define BODS    7
301#define PUD     6
302#define SE      5
303#define SM1     4
304#define SM0     3
305#define BODSE   2
306#define ISC01   1
307#define ISC00   0
308
309/* Reserved [0x36] */
310
311#define SPMCSR  _SFR_IO8(0x37)
312#define RSIG    5
313#define CTPB    4
314#define RFLB    3
315#define PGWRT   2
316#define PGERS   1
317#define SPMEN   0
318
319#define TIFR    _SFR_IO8(0x38)
320#define OCF1A   6
321#define OCF1B   5
322#define OCF0A   4
323#define OCF0B   3
324#define TOV1    2
325#define TOV0    1
326
327#define TIMSK   _SFR_IO8(0x39)
328#define OCIE1A  6
329#define OCIE1B  5
330#define OCIE0A  4
331#define OCIE0B  3
332#define TOIE1   2
333#define TOIE0   1
334
335#define GIFR    _SFR_IO8(0x3A)
336#define INTF0   6
337#define PCIF    5
338
339#define GIMSK   _SFR_IO8(0x3B)
340#define INT0    6
341#define PCIE    5
342
343/* Reserved [0x3C] */
344
345/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
346/* 0x3F SREG      [defined in <avr/io.h>] */
347
348///---
349
350/* Interrupt vectors */
351/* Interrupt vector 0 is the reset vector. */
352/* External Interrupt 0 */
353#define INT0_vect                       _VECTOR(1)
354#define SIG_INTERRUPT0                  _VECTOR(1)
355
356/* Pin change Interrupt Request 0 */
357#define PCINT0_vect                     _VECTOR(2)
358#define SIG_PIN_CHANGE                  _VECTOR(2)
359
360/* Timer/Counter1 Compare Match 1A */
361#define TIM1_COMPA_vect                 _VECTOR(3)
362#define TIMER1_COMPA_vect               _VECTOR(3)
363#define SIG_OUTPUT_COMPARE1A            _VECTOR(3)
364
365/* Timer/Counter1 Overflow */
366#define TIM1_OVF_vect                   _VECTOR(4)
367#define TIMER1_OVF_vect                 _VECTOR(4)
368#define SIG_OVERFLOW1                   _VECTOR(4)
369
370/* Timer/Counter0 Overflow */
371#define TIM0_OVF_vect                   _VECTOR(5)
372#define TIMER0_OVF_vect                 _VECTOR(5)
373#define SIG_OVERFLOW0                   _VECTOR(5)
374
375/* EEPROM Ready */
376#define EE_RDY_vect                     _VECTOR(6)
377#define SIG_EEPROM_READY                _VECTOR(6)
378
379/* Analog comparator */
380#define ANA_COMP_vect                   _VECTOR(7)
381#define SIG_COMPARATOR                  _VECTOR(7)
382
383/* ADC Conversion ready */
384#define ADC_vect                        _VECTOR(8)
385#define SIG_ADC                         _VECTOR(8)
386
387/* Timer/Counter1 Compare Match B */
388#define TIM1_COMPB_vect                 _VECTOR(9)
389#define TIMER1_COMPB_vect               _VECTOR(9)
390#define SIG_OUTPUT_COMPARE1B            _VECTOR(9)
391
392/* Timer/Counter0 Compare Match A */
393#define TIM0_COMPA_vect                 _VECTOR(10)
394#define TIMER0_COMPA_vect               _VECTOR(10)
395#define SIG_OUTPUT_COMPARE0A            _VECTOR(10)
396
397/* Timer/Counter0 Compare Match B */
398#define TIM0_COMPB_vect                 _VECTOR(11)
399#define TIMER0_COMPB_vect               _VECTOR(11)
400#define SIG_OUTPUT_COMPARE0B            _VECTOR(11)
401
402/* Watchdog Time-out */
403#define WDT_vect                        _VECTOR(12)
404#define SIG_WATCHDOG_TIMEOUT            _VECTOR(12)
405
406/* USI START */
407#define USI_START_vect                  _VECTOR(13)
408#define SIG_USI_START                   _VECTOR(13)
409
410/* USI Overflow */
411#define USI_OVF_vect                    _VECTOR(14)
412#define SIG_USI_OVERFLOW                _VECTOR(14)
413
414#define _VECTORS_SIZE 30
415
416#endif /* _AVR_IOTNX5_H_ */
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