1 | /* Copyright (c) 2005, 2007, 2009 Anatoly Sokolov |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ |
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34 | |
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35 | #ifndef _AVR_IOTNX5_H_ |
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36 | #define _AVR_IOTNX5_H_ 1 |
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37 | |
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38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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39 | |
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40 | #ifndef _AVR_IO_H_ |
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41 | # error "Include <avr/io.h> instead of this file." |
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42 | #endif |
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43 | |
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44 | #ifndef _AVR_IOXXX_H_ |
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45 | # define _AVR_IOXXX_H_ "iotnx5.h" |
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46 | #else |
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47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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48 | #endif |
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49 | |
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50 | /* I/O registers */ |
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51 | |
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52 | /* Reserved [0x00..0x02] */ |
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53 | |
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54 | #define ADCSRB _SFR_IO8 (0x03) |
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55 | #define BIN 7 |
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56 | #define ACME 6 |
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57 | #define IPR 5 |
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58 | #define ADTS2 2 |
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59 | #define ADTS1 1 |
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60 | #define ADTS0 0 |
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61 | |
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62 | #ifndef __ASSEMBLER__ |
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63 | #define ADC _SFR_IO16(0x04) |
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64 | #endif |
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65 | #define ADCW _SFR_IO16(0x04) |
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66 | #define ADCL _SFR_IO8(0x04) |
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67 | #define ADCH _SFR_IO8(0x05) |
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68 | |
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69 | #define ADCSRA _SFR_IO8 (0x06) |
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70 | #define ADEN 7 |
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71 | #define ADSC 6 |
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72 | #define ADATE 5 |
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73 | #define ADIF 4 |
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74 | #define ADIE 3 |
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75 | #define ADPS2 2 |
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76 | #define ADPS1 1 |
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77 | #define ADPS0 0 |
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78 | |
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79 | #define ADMUX _SFR_IO8(0x07) |
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80 | #define REFS1 7 |
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81 | #define REFS0 6 |
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82 | #define ADLAR 5 |
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83 | #define REFS2 4 |
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84 | #define MUX3 3 |
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85 | #define MUX2 2 |
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86 | #define MUX1 1 |
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87 | #define MUX0 0 |
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88 | |
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89 | #define ACSR _SFR_IO8(0x08) |
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90 | #define ACD 7 |
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91 | #define ACBG 6 |
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92 | #define ACO 5 |
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93 | #define ACI 4 |
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94 | #define ACIE 3 |
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95 | #define ACIS1 1 |
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96 | #define ACIS0 0 |
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97 | |
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98 | /* Reserved [0x09..0x0C] */ |
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99 | |
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100 | #define USICR _SFR_IO8(0x0D) |
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101 | #define USISIE 7 |
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102 | #define USIOIE 6 |
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103 | #define USIWM1 5 |
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104 | #define USIWM0 4 |
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105 | #define USICS1 3 |
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106 | #define USICS0 2 |
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107 | #define USICLK 1 |
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108 | #define USITC 0 |
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109 | |
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110 | #define USISR _SFR_IO8(0x0E) |
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111 | #define USISIF 7 |
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112 | #define USIOIF 6 |
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113 | #define USIPF 5 |
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114 | #define USIDC 4 |
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115 | #define USICNT3 3 |
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116 | #define USICNT2 2 |
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117 | #define USICNT1 1 |
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118 | #define USICNT0 0 |
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119 | |
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120 | #define USIDR _SFR_IO8(0x0F) |
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121 | #define USIBR _SFR_IO8(0x10) |
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122 | |
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123 | #define GPIOR0 _SFR_IO8(0x11) |
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124 | #define GPIOR1 _SFR_IO8(0x12) |
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125 | #define GPIOR2 _SFR_IO8(0x13) |
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126 | |
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127 | #define DIDR0 _SFR_IO8(0x14) |
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128 | #define ADC0D 5 |
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129 | #define ADC2D 4 |
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130 | #define ADC3D 3 |
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131 | #define ADC1D 2 |
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132 | #define AIN1D 1 |
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133 | #define AIN0D 0 |
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134 | |
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135 | #define PCMSK _SFR_IO8(0x15) |
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136 | #define PCINT5 5 |
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137 | #define PCINT4 4 |
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138 | #define PCINT3 3 |
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139 | #define PCINT2 2 |
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140 | #define PCINT1 1 |
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141 | #define PCINT0 0 |
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142 | |
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143 | #define PINB _SFR_IO8(0x16) |
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144 | #define PINB5 5 |
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145 | #define PINB4 4 |
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146 | #define PINB3 3 |
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147 | #define PINB2 2 |
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148 | #define PINB1 1 |
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149 | #define PINB0 0 |
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150 | |
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151 | #define DDRB _SFR_IO8(0x17) |
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152 | #define DDB5 5 |
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153 | #define DDB4 4 |
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154 | #define DDB3 3 |
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155 | #define DDB2 2 |
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156 | #define DDB1 1 |
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157 | #define DDB0 0 |
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158 | |
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159 | #define PORTB _SFR_IO8(0x18) |
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160 | #define PB5 5 |
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161 | #define PB4 4 |
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162 | #define PB3 3 |
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163 | #define PB2 2 |
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164 | #define PB1 1 |
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165 | #define PB0 0 |
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166 | |
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167 | /* Reserved [0x19..0x1B] */ |
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168 | |
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169 | /* EEPROM Control Register EECR */ |
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170 | #define EECR _SFR_IO8(0x1C) |
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171 | #define EEPM1 5 |
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172 | #define EEPM0 4 |
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173 | #define EERIE 3 |
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174 | #define EEMPE 2 |
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175 | #define EEPE 1 |
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176 | #define EERE 0 |
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177 | |
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178 | /* EEPROM Data Register */ |
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179 | #define EEDR _SFR_IO8(0x1D) |
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180 | |
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181 | /* EEPROM Address Register */ |
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182 | #define EEAR _SFR_IO16(0x1E) |
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183 | #define EEARL _SFR_IO8(0x1E) |
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184 | #define EEARH _SFR_IO8(0x1F) |
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185 | |
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186 | #define PRR _SFR_IO8(0x20) |
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187 | #define PRTIM1 3 |
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188 | #define PRTIM0 2 |
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189 | #define PRUSI 1 |
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190 | #define PRADC 0 |
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191 | |
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192 | #define WDTCR _SFR_IO8(0x21) |
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193 | #define WDIF 7 |
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194 | #define WDIE 6 |
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195 | #define WDP3 5 |
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196 | #define WDCE 4 |
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197 | #define WDE 3 |
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198 | #define WDP2 2 |
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199 | #define WDP1 1 |
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200 | #define WDP0 0 |
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201 | |
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202 | #define DWDR _SFR_IO8(0x22) |
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203 | |
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204 | #define DTPS1 _SFR_IO8(0x23) |
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205 | #define DTPS11 1 |
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206 | #define DTPS10 0 |
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207 | |
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208 | #define DT1B _SFR_IO8(0x24) |
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209 | #define DT1BH3 7 |
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210 | #define DT1BH2 6 |
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211 | #define DT1BH1 5 |
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212 | #define DT1BH0 4 |
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213 | #define DT1BL3 3 |
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214 | #define DT1BL2 2 |
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215 | #define DT1BL1 1 |
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216 | #define DT1BL0 0 |
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217 | |
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218 | #define DT1A _SFR_IO8(0x25) |
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219 | #define DT1AH3 7 |
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220 | #define DT1AH2 6 |
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221 | #define DT1AH1 5 |
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222 | #define DT1AH0 4 |
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223 | #define DT1AL3 3 |
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224 | #define DT1AL2 2 |
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225 | #define DT1AL1 1 |
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226 | #define DT1AL0 0 |
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227 | |
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228 | #define CLKPR _SFR_IO8(0x26) |
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229 | #define CLKPCE 7 |
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230 | #define CLKPS3 3 |
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231 | #define CLKPS2 2 |
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232 | #define CLKPS1 1 |
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233 | #define CLKPS0 0 |
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234 | |
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235 | #define PLLCSR _SFR_IO8(0x27) |
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236 | #define LSM 7 |
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237 | #define PCKE 2 |
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238 | #define PLLE 1 |
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239 | #define PLOCK 0 |
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240 | |
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241 | #define OCR0B _SFR_IO8(0x28) |
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242 | |
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243 | #define OCR0A _SFR_IO8(0x29) |
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244 | |
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245 | #define TCCR0A _SFR_IO8(0x2A) |
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246 | #define COM0A1 7 |
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247 | #define COM0A0 6 |
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248 | #define COM0B1 5 |
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249 | #define COM0B0 4 |
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250 | #define WGM01 1 |
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251 | #define WGM00 0 |
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252 | |
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253 | #define OCR1B _SFR_IO8(0x2B) |
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254 | |
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255 | #define GTCCR _SFR_IO8(0x2C) |
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256 | #define TSM 7 |
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257 | #define PWM1B 6 |
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258 | #define COM1B1 5 |
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259 | #define COM1B0 4 |
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260 | #define FOC1B 3 |
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261 | #define FOC1A 2 |
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262 | #define PSR1 1 |
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263 | #define PSR0 0 |
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264 | |
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265 | #define OCR1C _SFR_IO8(0x2D) |
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266 | |
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267 | #define OCR1A _SFR_IO8(0x2E) |
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268 | |
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269 | #define TCNT1 _SFR_IO8(0x2F) |
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270 | |
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271 | #define TCCR1 _SFR_IO8(0x30) |
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272 | #define CTC1 7 |
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273 | #define PWM1A 6 |
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274 | #define COM1A1 5 |
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275 | #define COM1A0 4 |
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276 | #define CS13 3 |
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277 | #define CS12 2 |
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278 | #define CS11 1 |
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279 | #define CS10 0 |
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280 | |
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281 | #define OSCCAL _SFR_IO8(0x31) |
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282 | |
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283 | #define TCNT0 _SFR_IO8(0x32) |
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284 | |
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285 | #define TCCR0B _SFR_IO8(0x33) |
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286 | #define FOC0A 7 |
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287 | #define FOC0B 6 |
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288 | #define WGM02 3 |
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289 | #define CS02 2 |
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290 | #define CS01 1 |
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291 | #define CS00 0 |
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292 | |
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293 | #define MCUSR _SFR_IO8(0x34) |
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294 | #define WDRF 3 |
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295 | #define BORF 2 |
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296 | #define EXTRF 1 |
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297 | #define PORF 0 |
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298 | |
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299 | #define MCUCR _SFR_IO8(0x35) |
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300 | #define BODS 7 |
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301 | #define PUD 6 |
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302 | #define SE 5 |
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303 | #define SM1 4 |
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304 | #define SM0 3 |
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305 | #define BODSE 2 |
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306 | #define ISC01 1 |
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307 | #define ISC00 0 |
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308 | |
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309 | /* Reserved [0x36] */ |
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310 | |
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311 | #define SPMCSR _SFR_IO8(0x37) |
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312 | #define RSIG 5 |
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313 | #define CTPB 4 |
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314 | #define RFLB 3 |
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315 | #define PGWRT 2 |
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316 | #define PGERS 1 |
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317 | #define SPMEN 0 |
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318 | |
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319 | #define TIFR _SFR_IO8(0x38) |
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320 | #define OCF1A 6 |
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321 | #define OCF1B 5 |
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322 | #define OCF0A 4 |
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323 | #define OCF0B 3 |
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324 | #define TOV1 2 |
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325 | #define TOV0 1 |
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326 | |
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327 | #define TIMSK _SFR_IO8(0x39) |
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328 | #define OCIE1A 6 |
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329 | #define OCIE1B 5 |
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330 | #define OCIE0A 4 |
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331 | #define OCIE0B 3 |
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332 | #define TOIE1 2 |
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333 | #define TOIE0 1 |
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334 | |
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335 | #define GIFR _SFR_IO8(0x3A) |
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336 | #define INTF0 6 |
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337 | #define PCIF 5 |
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338 | |
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339 | #define GIMSK _SFR_IO8(0x3B) |
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340 | #define INT0 6 |
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341 | #define PCIE 5 |
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342 | |
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343 | /* Reserved [0x3C] */ |
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344 | |
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345 | /* 0x3D..0x3E SP [defined in <avr/io.h>] */ |
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346 | /* 0x3F SREG [defined in <avr/io.h>] */ |
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347 | |
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348 | ///--- |
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349 | |
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350 | /* Interrupt vectors */ |
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351 | /* Interrupt vector 0 is the reset vector. */ |
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352 | /* External Interrupt 0 */ |
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353 | #define INT0_vect _VECTOR(1) |
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354 | #define SIG_INTERRUPT0 _VECTOR(1) |
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355 | |
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356 | /* Pin change Interrupt Request 0 */ |
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357 | #define PCINT0_vect _VECTOR(2) |
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358 | #define SIG_PIN_CHANGE _VECTOR(2) |
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359 | |
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360 | /* Timer/Counter1 Compare Match 1A */ |
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361 | #define TIM1_COMPA_vect _VECTOR(3) |
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362 | #define TIMER1_COMPA_vect _VECTOR(3) |
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363 | #define SIG_OUTPUT_COMPARE1A _VECTOR(3) |
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364 | |
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365 | /* Timer/Counter1 Overflow */ |
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366 | #define TIM1_OVF_vect _VECTOR(4) |
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367 | #define TIMER1_OVF_vect _VECTOR(4) |
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368 | #define SIG_OVERFLOW1 _VECTOR(4) |
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369 | |
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370 | /* Timer/Counter0 Overflow */ |
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371 | #define TIM0_OVF_vect _VECTOR(5) |
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372 | #define TIMER0_OVF_vect _VECTOR(5) |
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373 | #define SIG_OVERFLOW0 _VECTOR(5) |
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374 | |
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375 | /* EEPROM Ready */ |
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376 | #define EE_RDY_vect _VECTOR(6) |
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377 | #define SIG_EEPROM_READY _VECTOR(6) |
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378 | |
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379 | /* Analog comparator */ |
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380 | #define ANA_COMP_vect _VECTOR(7) |
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381 | #define SIG_COMPARATOR _VECTOR(7) |
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382 | |
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383 | /* ADC Conversion ready */ |
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384 | #define ADC_vect _VECTOR(8) |
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385 | #define SIG_ADC _VECTOR(8) |
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386 | |
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387 | /* Timer/Counter1 Compare Match B */ |
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388 | #define TIM1_COMPB_vect _VECTOR(9) |
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389 | #define TIMER1_COMPB_vect _VECTOR(9) |
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390 | #define SIG_OUTPUT_COMPARE1B _VECTOR(9) |
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391 | |
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392 | /* Timer/Counter0 Compare Match A */ |
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393 | #define TIM0_COMPA_vect _VECTOR(10) |
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394 | #define TIMER0_COMPA_vect _VECTOR(10) |
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395 | #define SIG_OUTPUT_COMPARE0A _VECTOR(10) |
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396 | |
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397 | /* Timer/Counter0 Compare Match B */ |
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398 | #define TIM0_COMPB_vect _VECTOR(11) |
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399 | #define TIMER0_COMPB_vect _VECTOR(11) |
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400 | #define SIG_OUTPUT_COMPARE0B _VECTOR(11) |
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401 | |
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402 | /* Watchdog Time-out */ |
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403 | #define WDT_vect _VECTOR(12) |
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404 | #define SIG_WATCHDOG_TIMEOUT _VECTOR(12) |
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405 | |
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406 | /* USI START */ |
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407 | #define USI_START_vect _VECTOR(13) |
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408 | #define SIG_USI_START _VECTOR(13) |
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409 | |
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410 | /* USI Overflow */ |
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411 | #define USI_OVF_vect _VECTOR(14) |
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412 | #define SIG_USI_OVERFLOW _VECTOR(14) |
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413 | |
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414 | #define _VECTORS_SIZE 30 |
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415 | |
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416 | #endif /* _AVR_IOTNX5_H_ */ |
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