source: rtems/cpukit/score/cpu/avr/avr/iotnx4.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 9.7 KB
Line 
1/* Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */
34
35#ifndef _AVR_IOTNX4_H_
36#define _AVR_IOTNX4_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iotnx4.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50/* I/O registers */
51
52#define PRR     _SFR_IO8 (0x00)
53#define PRTIM1  3
54#define PRTIM0  2
55#define PRUSI   1
56#define PRADC   0
57
58#define DIDR0    _SFR_IO8(0x01)
59#define ADC7D   7
60#define ADC6D   6
61#define ADC5D   5
62#define ADC4D   4
63#define ADC3D   3
64#define ADC2D   2
65#define ADC1D   1
66#define ADC0D   0
67
68/* Reserved [0x02] */
69
70#define ADCSRB  _SFR_IO8 (0x03)
71#define BIN     7
72#define ACME    6
73#define ADLAR   4
74#define ADTS2   2
75#define ADTS1   1
76#define ADTS0   0
77
78#ifndef __ASSEMBLER__
79#define ADC     _SFR_IO16(0x04)
80#endif
81#define ADCW    _SFR_IO16(0x04)
82#define ADCL    _SFR_IO8(0x04)
83#define ADCH    _SFR_IO8(0x05)
84
85#define ADCSRA  _SFR_IO8 (0x06)
86#define ADEN    7
87#define ADSC    6
88#define ADATE   5
89#define ADIF    4
90#define ADIE    3
91#define ADPS2   2
92#define ADPS1   1
93#define ADPS0   0
94
95#define ADMUX   _SFR_IO8(0x07)
96#define REFS1   7
97#define REFS0   6
98#define MUX5    5
99#define MUX4    4
100#define MUX3    3
101#define MUX2    2
102#define MUX1    1
103#define MUX0    0
104
105#define ACSR    _SFR_IO8(0x08)
106#define ACD     7
107#define ACBG    6
108#define ACO     5
109#define ACI     4
110#define ACIE    3
111#define ACIC    2
112#define ACIS1   1
113#define ACIS0   0
114
115/* Reserved [0x09..0x0A] */
116
117#define TIFR1   _SFR_IO8(0x0B)
118#define ICF1    5
119#define OCF1B   2
120#define OCF1A   1
121#define TOV1    0
122
123#define TIMSK1   _SFR_IO8(0x0C)
124#define ICIE1   5
125#define OCIE1B  2
126#define OCIE1A  1
127#define TOIE1   0
128
129#define USICR   _SFR_IO8(0x0D)
130#define USISIE  7
131#define USIOIE  6
132#define USIWM1  5
133#define USIWM0  4
134#define USICS1  3
135#define USICS0  2
136#define USICLK  1
137#define USITC   0
138
139#define USISR   _SFR_IO8(0x0E)
140#define USISIF  7
141#define USIOIF  6
142#define USIPF   5
143#define USIDC   4
144#define USICNT3 3
145#define USICNT2 2
146#define USICNT1 1
147#define USICNT0 0
148
149#define USIDR   _SFR_IO8(0x0F)
150
151#define USIBR   _SFR_IO8(0x10)
152
153/* Reserved [0x11] */
154
155#define PCMSK0  _SFR_IO8(0x12)
156#define PCINT7  7
157#define PCINT6  6
158#define PCINT5  5
159#define PCINT4  4
160#define PCINT3  3
161#define PCINT2  2
162#define PCINT1  1
163#define PCINT0  0
164
165#define GPIOR0  _SFR_IO8(0x13)
166
167#define GPIOR1  _SFR_IO8(0x14)
168
169#define GPIOR2  _SFR_IO8(0x15)
170
171#define PINB    _SFR_IO8(0x16)
172#define PINB3   3
173#define PINB2   2
174#define PINB1   1
175#define PINB0   0
176
177#define DDRB    _SFR_IO8(0x17)
178#define DDB3    3
179#define DDB2    2
180#define DDB1    1
181#define DDB0    0
182
183#define PORTB   _SFR_IO8(0x18)
184#define PB3     3
185#define PB2     2
186#define PB1     1
187#define PB0     0
188
189#define PINA    _SFR_IO8(0x19)
190#define PINA7   7
191#define PINA6   6
192#define PINA5   5
193#define PINA4   4
194#define PINA3   3
195#define PINA2   2
196#define PINA1   1
197#define PINA0   0
198
199#define DDRA    _SFR_IO8(0x1A)
200#define DDA7    7
201#define DDA6    6
202#define DDA5    5
203#define DDA4    4
204#define DDA3    3
205#define DDA2    2
206#define DDA1    1
207#define DDA0    0
208
209#define PORTA   _SFR_IO8(0x1B)
210#define PA7     7
211#define PA6     6
212#define PA5     5
213#define PA4     4
214#define PA3     3
215#define PA2     2
216#define PA1     1
217#define PA0     0
218
219/* EEPROM Control Register EECR */
220#define EECR    _SFR_IO8(0x1C)
221#define EEPM1   5
222#define EEPM0   4
223#define EERIE   3
224#define EEMPE   2
225#define EEPE    1
226#define EERE    0
227
228/* EEPROM Data Register */
229#define EEDR    _SFR_IO8(0x1D)
230
231/* EEPROM Address Register */
232#define EEAR    _SFR_IO16(0x1E)
233#define EEARL   _SFR_IO8(0x1E)
234#define EEARH   _SFR_IO8(0x1F)
235
236#define PCMSK1  _SFR_IO8(0x20)
237#define PCINT11 3
238#define PCINT10 2
239#define PCINT9  1
240#define PCINT8  0
241
242#define WDTCSR _SFR_IO8(0x21)
243#define WDIF    7
244#define WDIE    6
245#define WDP3    5
246#define WDCE    4
247#define WDE     3
248#define WDP2    2
249#define WDP1    1
250#define WDP0    0
251
252#define TCCR1C  _SFR_IO8(0x22)
253#define FOC1A   7
254#define FOC1B   6
255
256#define GTCCR   _SFR_IO8(0x23)
257#define TSM     7
258#define PSR10   0
259
260#define ICR1    _SFR_IO16(0x24)
261#define ICR1L   _SFR_IO8(0x24)
262#define ICR1H   _SFR_IO8(0x25)
263
264#define CLKPR   _SFR_IO8(0x26)
265#define CLKPCE  7
266#define CLKPS3  3
267#define CLKPS2  2
268#define CLKPS1  1
269#define CLKPS0  0
270
271#define DWDR    _SFR_IO8(0x27)
272
273#define OCR1B   _SFR_IO16(0x28)
274#define OCR1BL  _SFR_IO8(0x28)
275#define OCR1BH  _SFR_IO8(0x29)
276
277#define OCR1A   _SFR_IO16(0x2A)
278#define OCR1AL  _SFR_IO8(0x2A)
279#define OCR1AH  _SFR_IO8(0x2B)
280
281/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */
282#define OCRB1   _SFR_IO16(0x28)
283#define OCRB1L  _SFR_IO8(0x28)
284#define OCRB1H  _SFR_IO8(0x29)
285
286#define OCRA1   _SFR_IO16(0x2A)
287#define OCRA1L  _SFR_IO8(0x2A)
288#define OCRA1H  _SFR_IO8(0x2B)
289
290#define TCNT1   _SFR_IO16(0x2C)
291#define TCNT1L  _SFR_IO8(0x2C)
292#define TCNT1H  _SFR_IO8(0x2D)
293
294#define TCCR1B  _SFR_IO8(0x2E)
295#define ICNC1   7
296#define ICES1   6
297#define WGM13   4
298#define WGM12   3
299#define CS12    2
300#define CS11    1
301#define CS10    0
302
303#define TCCR1A  _SFR_IO8(0x2F)
304#define COM1A1  7
305#define COM1A0  6
306#define COM1B1  5
307#define COM1B0  4
308#define WGM11   1
309#define WGM10   0
310
311#define TCCR0A  _SFR_IO8(0x30)
312#define COM0A1  7
313#define COM0A0  6
314#define COM0B1  5
315#define COM0B0  4
316#define WGM01   1
317#define WGM00   0
318
319#define OSCCAL  _SFR_IO8(0x31)
320
321#define TCNT0   _SFR_IO8(0x32)
322
323#define TCCR0B  _SFR_IO8(0x33)
324#define FOC0A   7
325#define FOC0B   6
326#define WGM02   3
327#define CS02    2
328#define CS01    1
329#define CS00    0
330
331#define MCUSR   _SFR_IO8(0x34)
332#define WDRF    3
333#define BORF    2
334#define EXTRF   1
335#define PORF    0
336
337#define MCUCR   _SFR_IO8(0x35)
338#define BODS    7
339#define PUD     6
340#define SE      5
341#define SM1     4
342#define SM0     3
343#define BODSE   2
344#define ISC01   1
345#define ISC00   0
346
347#define OCR0A   _SFR_IO8(0x36)
348
349#define SPMCSR  _SFR_IO8(0x37)
350#define RSIG    5
351#define CTPB    4
352#define RFLB    3
353#define PGWRT   2
354#define PGERS   1
355#define SPMEN   0
356
357#define TIFR0   _SFR_IO8(0x38)
358#define OCF0B   2
359#define OCF0A   1
360#define TOV0    0
361
362#define TIMSK0  _SFR_IO8(0x39)
363#define OCIE0B  2
364#define OCIE0A  1
365#define TOIE0   0
366
367#define GIFR    _SFR_IO8(0x3A)
368#define INTF0   6
369#define PCIF1   5
370#define PCIF0   4
371
372#define GIMSK   _SFR_IO8(0x3B)
373#define INT0    6
374#define PCIE1   5
375#define PCIE0   4
376
377#define OCR0B   _SFR_IO8(0x3C)
378
379/* 0x3D..0x3E SP  [defined in <avr/io.h>] */
380/* 0x3F SREG      [defined in <avr/io.h>] */
381
382///---
383
384/* Interrupt vectors */
385/* Interrupt vector 0 is the reset vector. */
386/* External Interrupt Request 0 */
387#define INT0_vect                       _VECTOR(1)
388#define EXT_INT0_vect                   _VECTOR(1)
389#define SIG_INTERRUPT0                  _VECTOR(1)
390
391/* Pin Change Interrupt Request 0 */
392#define PCINT0_vect                     _VECTOR(2)
393#define SIG_PIN_CHANGE0                 _VECTOR(2)
394
395/* Pin Change Interrupt Request 1 */
396#define PCINT1_vect                     _VECTOR(3)
397#define SIG_PIN_CHANGE1                 _VECTOR(3)
398
399/* Watchdog Time-out */
400#define WDT_vect                        _VECTOR(4)
401#define WATCHDOG_vect                   _VECTOR(4)
402#define SIG_WATCHDOG_TIMEOUT            _VECTOR(4)
403
404/* Timer/Counter1 Capture Event */
405#define TIMER1_CAPT_vect                _VECTOR(5)
406#define TIM1_CAPT_vect                  _VECTOR(5)
407#define SIG_INPUT_CAPTURE1              _VECTOR(5)
408
409/* Timer/Counter1 Compare Match A */
410#define TIM1_COMPA_vect                 _VECTOR(6)
411#define SIG_OUTPUT_COMPARE1A            _VECTOR(6)
412
413/* Timer/Counter1 Compare Match B */
414#define TIM1_COMPB_vect                 _VECTOR(7)
415#define SIG_OUTPUT_COMPARE1B            _VECTOR(7)
416
417/* Timer/Counter1 Overflow */
418#define TIM1_OVF_vect                   _VECTOR(8)
419#define SIG_OVERFLOW1                   _VECTOR(8)
420
421/* Timer/Counter0 Compare Match A */
422#define TIM0_COMPA_vect                 _VECTOR(9)
423#define SIG_OUTPUT_COMPARE0A            _VECTOR(9)
424
425/* Timer/Counter0 Compare Match B */
426#define TIM0_COMPB_vect                 _VECTOR(10)
427#define SIG_OUTPUT_COMPARE0B            _VECTOR(10)
428
429/* Timer/Counter0 Overflow */
430#define TIM0_OVF_vect                   _VECTOR(11)
431#define SIG_OVERFLOW0                   _VECTOR(11)
432
433/* Analog Comparator */
434#define ANA_COMP_vect                   _VECTOR(12)
435#define SIG_COMPARATOR                  _VECTOR(12)
436
437/* ADC Conversion Complete */
438#define ADC_vect                        _VECTOR(13)
439#define SIG_ADC                         _VECTOR(13)
440
441/* EEPROM Ready */
442#define EE_RDY_vect                     _VECTOR(14)
443#define SIG_EEPROM_READY                _VECTOR(14)
444
445/* USI START */
446#define USI_START_vect                  _VECTOR(15)
447#define USI_STR_vect                    _VECTOR(15)
448#define SIG_USI_START                   _VECTOR(15)
449
450/* USI Overflow */
451#define USI_OVF_vect                    _VECTOR(16)
452#define SIG_USI_OVERFLOW                _VECTOR(16)
453
454#define _VECTORS_SIZE 34
455
456#endif /* _AVR_IOTNX4_H_ */
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