1 | /* Copyright (c) 2009 Atmel Corporation |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | /* $Id$ */ |
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32 | |
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33 | /* avr/iotn87.h - definitions for ATtiny87 */ |
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34 | |
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35 | /* This file should only be included from <avr/io.h>, never directly. */ |
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36 | |
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37 | #ifndef _AVR_IO_H_ |
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38 | # error "Include <avr/io.h> instead of this file." |
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39 | #endif |
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40 | |
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41 | #ifndef _AVR_IOXXX_H_ |
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42 | # define _AVR_IOXXX_H_ "iotn87.h" |
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43 | #else |
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44 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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45 | #endif |
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46 | |
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47 | |
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48 | #ifndef _AVR_ATtiny87_H_ |
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49 | #define _AVR_ATtiny87_H_ 1 |
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50 | |
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51 | |
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52 | /* Registers and associated bit numbers. */ |
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53 | |
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54 | #define PINA _SFR_IO8(0x00) |
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55 | #define PINA0 0 |
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56 | #define PINA1 1 |
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57 | #define PINA2 2 |
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58 | #define PINA3 3 |
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59 | #define PINA4 4 |
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60 | #define PINA5 5 |
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61 | #define PINA6 6 |
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62 | #define PINA7 7 |
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63 | |
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64 | #define DDRA _SFR_IO8(0x01) |
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65 | #define DDA0 0 |
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66 | #define DDA1 1 |
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67 | #define DDA2 2 |
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68 | #define DDA3 3 |
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69 | #define DDA4 4 |
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70 | #define DDA5 5 |
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71 | #define DDA6 6 |
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72 | #define DDA7 7 |
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73 | |
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74 | #define PORTA _SFR_IO8(0x02) |
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75 | #define PORTA0 0 |
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76 | #define PORTA1 1 |
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77 | #define PORTA2 2 |
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78 | #define PORTA3 3 |
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79 | #define PORTA4 4 |
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80 | #define PORTA5 5 |
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81 | #define PORTA6 6 |
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82 | #define PORTA7 7 |
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83 | |
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84 | #define PINB _SFR_IO8(0x03) |
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85 | #define PINB0 0 |
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86 | #define PINB1 1 |
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87 | #define PINB2 2 |
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88 | #define PINB3 3 |
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89 | #define PINB4 4 |
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90 | #define PINB5 5 |
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91 | #define PINB6 6 |
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92 | #define PINB7 7 |
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93 | |
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94 | #define DDRB _SFR_IO8(0x04) |
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95 | #define DDB0 0 |
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96 | #define DDB1 1 |
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97 | #define DDB2 2 |
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98 | #define DDB3 3 |
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99 | #define DDB4 4 |
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100 | #define DDB5 5 |
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101 | #define DDB6 6 |
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102 | #define DDB7 7 |
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103 | |
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104 | #define PORTB _SFR_IO8(0x05) |
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105 | #define PORTB0 0 |
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106 | #define PORTB1 1 |
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107 | #define PORTB2 2 |
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108 | #define PORTB3 3 |
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109 | #define PORTB4 4 |
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110 | #define PORTB5 5 |
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111 | #define PORTB6 6 |
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112 | #define PORTB7 7 |
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113 | |
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114 | #define PORTCR _SFR_IO8(0x12) |
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115 | #define PUDA 0 |
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116 | #define PUDB 2 |
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117 | #define BBMA 4 |
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118 | #define BBMB 5 |
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119 | |
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120 | #define TIFR0 _SFR_IO8(0x15) |
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121 | #define TOV0 0 |
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122 | #define OCF0A 1 |
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123 | |
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124 | #define TIFR1 _SFR_IO8(0x16) |
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125 | #define TOV1 0 |
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126 | #define OCF1A 1 |
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127 | #define OCF1B 2 |
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128 | #define ICF1 5 |
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129 | |
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130 | #define PCIFR _SFR_IO8(0x1B) |
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131 | #define PCIF0 0 |
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132 | #define PCIF1 1 |
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133 | |
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134 | #define EIFR _SFR_IO8(0x1C) |
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135 | #define INTF0 0 |
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136 | #define INTF1 1 |
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137 | |
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138 | #define EIMSK _SFR_IO8(0x1D) |
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139 | #define INT0 0 |
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140 | #define INT1 1 |
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141 | |
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142 | #define GPIOR0 _SFR_IO8(0x1E) |
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143 | #define GPIOR00 0 |
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144 | #define GPIOR01 1 |
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145 | #define GPIOR02 2 |
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146 | #define GPIOR03 3 |
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147 | #define GPIOR04 4 |
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148 | #define GPIOR05 5 |
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149 | #define GPIOR06 6 |
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150 | #define GPIOR07 7 |
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151 | |
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152 | #define EECR _SFR_IO8(0x1F) |
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153 | #define EERE 0 |
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154 | #define EEPE 1 |
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155 | #define EEMPE 2 |
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156 | #define EERIE 3 |
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157 | #define EEPM0 4 |
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158 | #define EEPM1 5 |
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159 | |
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160 | #define EEDR _SFR_IO8(0x20) |
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161 | #define EEDR0 0 |
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162 | #define EEDR1 1 |
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163 | #define EEDR2 2 |
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164 | #define EEDR3 3 |
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165 | #define EEDR4 4 |
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166 | #define EEDR5 5 |
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167 | #define EEDR6 6 |
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168 | #define EEDR7 7 |
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169 | |
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170 | #define EEAR _SFR_IO16(0x21) |
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171 | |
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172 | #define EEARL _SFR_IO8(0x21) |
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173 | #define EEAR0 0 |
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174 | #define EEAR1 1 |
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175 | #define EEAR2 2 |
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176 | #define EEAR3 3 |
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177 | #define EEAR4 4 |
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178 | #define EEAR5 5 |
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179 | #define EEAR6 6 |
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180 | #define EEAR7 7 |
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181 | |
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182 | #define EEARH _SFR_IO8(0x22) |
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183 | #define EEAR8 0 |
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184 | |
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185 | #define GTCCR _SFR_IO8(0x23) |
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186 | #define PSR1 0 |
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187 | #define PSR0 1 |
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188 | #define TSM 7 |
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189 | |
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190 | #define TCCR0A _SFR_IO8(0x25) |
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191 | #define WGM00 0 |
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192 | #define WGM01 1 |
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193 | #define COM0A0 6 |
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194 | #define COM0A1 7 |
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195 | |
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196 | #define TCCR0B _SFR_IO8(0x26) |
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197 | #define CS00 0 |
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198 | #define CS01 1 |
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199 | #define CS02 2 |
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200 | #define FOC0A 7 |
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201 | |
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202 | #define TCNT0 _SFR_IO8(0x27) |
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203 | #define TCNT00 0 |
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204 | #define TCNT01 1 |
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205 | #define TCNT02 2 |
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206 | #define TCNT03 3 |
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207 | #define TCNT04 4 |
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208 | #define TCNT05 5 |
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209 | #define TCNT06 6 |
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210 | #define TCNT07 7 |
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211 | |
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212 | #define OCR0A _SFR_IO8(0x28) |
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213 | #define OCR00 0 |
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214 | #define OCR01 1 |
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215 | #define OCR02 2 |
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216 | #define OCR03 3 |
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217 | #define OCR04 4 |
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218 | #define OCR05 5 |
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219 | #define OCR06 6 |
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220 | #define OCR07 7 |
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221 | |
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222 | #define GPIOR1 _SFR_IO8(0x2A) |
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223 | #define GPIOR10 0 |
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224 | #define GPIOR11 1 |
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225 | #define GPIOR12 2 |
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226 | #define GPIOR13 3 |
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227 | #define GPIOR14 4 |
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228 | #define GPIOR15 5 |
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229 | #define GPIOR16 6 |
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230 | #define GPIOR17 7 |
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231 | |
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232 | #define GPIOR2 _SFR_IO8(0x2B) |
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233 | #define GPIOR20 0 |
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234 | #define GPIOR21 1 |
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235 | #define GPIOR22 2 |
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236 | #define GPIOR23 3 |
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237 | #define GPIOR24 4 |
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238 | #define GPIOR25 5 |
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239 | #define GPIOR26 6 |
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240 | #define GPIOR27 7 |
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241 | |
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242 | #define SPCR _SFR_IO8(0x2C) |
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243 | #define SPR0 0 |
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244 | #define SPR1 1 |
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245 | #define CPHA 2 |
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246 | #define CPOL 3 |
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247 | #define MSTR 4 |
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248 | #define DORD 5 |
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249 | #define SPE 6 |
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250 | #define SPIE 7 |
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251 | |
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252 | #define SPSR _SFR_IO8(0x2D) |
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253 | #define SPI2X 0 |
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254 | #define WCOL 6 |
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255 | #define SPIF 7 |
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256 | |
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257 | #define SPDR _SFR_IO8(0x2E) |
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258 | #define SPDR0 0 |
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259 | #define SPDR1 1 |
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260 | #define SPDR2 2 |
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261 | #define SPDR3 3 |
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262 | #define SPDR4 4 |
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263 | #define SPDR5 5 |
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264 | #define SPDR6 6 |
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265 | #define SPDR7 7 |
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266 | |
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267 | #define ACSR _SFR_IO8(0x30) |
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268 | #define ACIS0 0 |
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269 | #define ACIS1 1 |
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270 | #define ACIC 2 |
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271 | #define ACIE 3 |
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272 | #define ACI 4 |
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273 | #define ACO 5 |
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274 | #define ACIRS 6 |
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275 | #define ACD 7 |
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276 | |
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277 | #define DWDR _SFR_IO8(0x31) |
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278 | #define DWDR0 0 |
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279 | #define DWDR1 1 |
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280 | #define DWDR2 2 |
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281 | #define DWDR3 3 |
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282 | #define DWDR4 4 |
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283 | #define DWDR5 5 |
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284 | #define DWDR6 6 |
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285 | #define DWDR7 7 |
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286 | |
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287 | #define SMCR _SFR_IO8(0x33) |
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288 | #define SE 0 |
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289 | #define SM0 1 |
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290 | #define SM1 2 |
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291 | |
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292 | #define MCUSR _SFR_IO8(0x34) |
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293 | #define PORF 0 |
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294 | #define EXTRF 1 |
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295 | #define BORF 2 |
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296 | #define WDRF 3 |
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297 | |
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298 | #define MCUCR _SFR_IO8(0x35) |
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299 | #define PUD 4 |
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300 | #define BODS 5 |
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301 | #define BODSE 6 |
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302 | |
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303 | #define SPMCSR _SFR_IO8(0x37) |
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304 | #define SPMEN 0 |
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305 | #define PGERS 1 |
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306 | #define PGWRT 2 |
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307 | #define RFLB 3 |
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308 | #define CTPB 4 |
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309 | #define SIGRD 5 |
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310 | #define RWWSB 6 |
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311 | |
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312 | #define WDTCR _SFR_MEM8(0x60) |
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313 | #define WDP0 0 |
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314 | #define WDP1 1 |
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315 | #define WDP2 2 |
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316 | #define WDE 3 |
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317 | #define WDCE 4 |
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318 | #define WDP3 5 |
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319 | #define WDIE 6 |
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320 | #define WDIF 7 |
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321 | |
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322 | #define CLKPR _SFR_MEM8(0x61) |
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323 | #define CLKPS0 0 |
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324 | #define CLKPS1 1 |
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325 | #define CLKPS2 2 |
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326 | #define CLKPS3 3 |
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327 | #define CLKPCE 7 |
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328 | |
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329 | #define CLKCSR _SFR_MEM8(0x62) |
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330 | #define CLKC0 0 |
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331 | #define CLKC1 1 |
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332 | #define CLKC2 2 |
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333 | #define CLKC3 3 |
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334 | #define CLKRDY 4 |
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335 | #define CLKCCE 7 |
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336 | |
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337 | #define CLKSELR _SFR_MEM8(0x63) |
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338 | #define CSEL0 0 |
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339 | #define CSEL1 1 |
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340 | #define CSEL2 2 |
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341 | #define CSEL3 3 |
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342 | #define CSUT0 4 |
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343 | #define CSUT1 5 |
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344 | #define COUT 6 |
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345 | |
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346 | #define PRR _SFR_MEM8(0x64) |
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347 | #define PRADC 0 |
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348 | #define PRUSI 1 |
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349 | #define PRTIM0 2 |
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350 | #define PRTIM1 3 |
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351 | #define PRSPI 4 |
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352 | #define PRLIN 5 |
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353 | |
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354 | #define OSCCAL _SFR_MEM8(0x66) |
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355 | #define CAL0 0 |
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356 | #define CAL1 1 |
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357 | #define CAL2 2 |
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358 | #define CAL3 3 |
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359 | #define CAL4 4 |
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360 | #define CAL5 5 |
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361 | #define CAL6 6 |
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362 | #define CAL7 7 |
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363 | |
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364 | #define PCICR _SFR_MEM8(0x68) |
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365 | #define PCIE0 0 |
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366 | #define PCIE1 1 |
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367 | |
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368 | #define EICRA _SFR_MEM8(0x69) |
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369 | #define ISC00 0 |
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370 | #define ISC01 1 |
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371 | #define ISC10 2 |
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372 | #define ISC11 3 |
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373 | |
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374 | #define PCMSK0 _SFR_MEM8(0x6B) |
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375 | #define PCINT0 0 |
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376 | #define PCINT1 1 |
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377 | #define PCINT2 2 |
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378 | #define PCINT3 3 |
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379 | #define PCINT4 4 |
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380 | #define PCINT5 5 |
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381 | #define PCINT6 6 |
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382 | #define PCINT7 7 |
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383 | |
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384 | #define PCMSK1 _SFR_MEM8(0x6C) |
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385 | #define PCINT8 0 |
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386 | #define PCINT9 1 |
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387 | #define PCINT10 2 |
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388 | #define PCINT11 3 |
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389 | #define PCINT12 4 |
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390 | #define PCINT13 5 |
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391 | #define PCINT14 6 |
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392 | #define PCINT15 7 |
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393 | |
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394 | #define TIMSK0 _SFR_MEM8(0x6E) |
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395 | #define TOIE0 0 |
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396 | #define OCIE0A 1 |
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397 | |
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398 | #define TIMSK1 _SFR_MEM8(0x6F) |
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399 | #define TOIE1 0 |
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400 | #define OCIE1A 1 |
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401 | #define OCIE1B 2 |
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402 | #define ICIE1 5 |
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403 | |
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404 | #define AMISCR _SFR_MEM8(0x77) |
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405 | #define ISRCEN 0 |
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406 | #define XREFEN 1 |
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407 | #define AREFEN 2 |
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408 | |
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409 | #ifndef __ASSEMBLER__ |
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410 | #define ADC _SFR_MEM16(0x78) |
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411 | #endif |
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412 | #define ADCW _SFR_MEM16(0x78) |
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413 | |
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414 | #define ADCL _SFR_MEM8(0x78) |
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415 | #define ADCL0 0 |
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416 | #define ADCL1 1 |
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417 | #define ADCL2 2 |
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418 | #define ADCL3 3 |
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419 | #define ADCL4 4 |
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420 | #define ADCL5 5 |
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421 | #define ADCL6 6 |
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422 | #define ADCL7 7 |
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423 | |
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424 | #define ADCH _SFR_MEM8(0x79) |
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425 | #define ADCH0 0 |
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426 | #define ADCH1 1 |
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427 | #define ADCH2 2 |
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428 | #define ADCH3 3 |
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429 | #define ADCH4 4 |
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430 | #define ADCH5 5 |
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431 | #define ADCH6 6 |
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432 | #define ADCH7 7 |
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433 | |
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434 | #define ADCSRA _SFR_MEM8(0x7A) |
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435 | #define ADPS0 0 |
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436 | #define ADPS1 1 |
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437 | #define ADPS2 2 |
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438 | #define ADIE 3 |
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439 | #define ADIF 4 |
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440 | #define ADATE 5 |
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441 | #define ADSC 6 |
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442 | #define ADEN 7 |
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443 | |
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444 | #define ADCSRB _SFR_MEM8(0x7B) |
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445 | #define ADTS0 0 |
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446 | #define ADTS1 1 |
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447 | #define ADTS2 2 |
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448 | #define ACIR0 4 |
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449 | #define ACIR1 5 |
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450 | #define ACME 6 |
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451 | #define BIN 7 |
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452 | |
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453 | #define ADMUX _SFR_MEM8(0x7C) |
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454 | #define MUX0 0 |
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455 | #define MUX1 1 |
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456 | #define MUX2 2 |
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457 | #define MUX3 3 |
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458 | #define MUX4 4 |
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459 | #define ADLAR 5 |
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460 | #define REFS0 6 |
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461 | #define REFS1 7 |
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462 | |
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463 | #define DIDR0 _SFR_MEM8(0x7E) |
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464 | #define ADC0D 0 |
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465 | #define ADC1D 1 |
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466 | #define ADC2D 2 |
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467 | #define ADC3D 3 |
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468 | #define ADC4D 4 |
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469 | #define ADC5D 5 |
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470 | #define ADC6D 6 |
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471 | #define ADC7D 7 |
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472 | |
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473 | #define DIDR1 _SFR_MEM8(0x7F) |
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474 | #define ADC8D 0 |
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475 | #define ADC9D 1 |
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476 | #define ADC10D 2 |
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477 | |
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478 | #define TCCR1A _SFR_MEM8(0x80) |
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479 | #define WGM10 0 |
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480 | #define WGM11 1 |
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481 | #define COM1B0 4 |
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482 | #define COM1B1 5 |
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483 | #define COM1A0 6 |
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484 | #define COM1A1 7 |
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485 | |
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486 | #define TCCR1B _SFR_MEM8(0x81) |
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487 | #define CS10 0 |
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488 | #define CS11 1 |
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489 | #define CS12 2 |
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490 | #define WGM12 3 |
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491 | #define WGM13 4 |
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492 | #define ICES1 6 |
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493 | #define ICNC1 7 |
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494 | |
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495 | #define TCCR1C _SFR_MEM8(0x82) |
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496 | #define FOC1B 6 |
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497 | #define FOC1A 7 |
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498 | |
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499 | #define TCCR1D _SFR_MEM8(0x83) |
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500 | #define OC1AU 0 |
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501 | #define OC1AV 1 |
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502 | #define OC1AW 2 |
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503 | #define OC1AX 3 |
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504 | #define OC1BU 4 |
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505 | #define OC1BV 5 |
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506 | #define OC1BW 6 |
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507 | #define OC1BX 7 |
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508 | |
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509 | #define TCNT1 _SFR_MEM16(0x84) |
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510 | |
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511 | #define TCNT1L _SFR_MEM8(0x84) |
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512 | #define TCNT1L0 0 |
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513 | #define TCNT1L1 1 |
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514 | #define TCNT1L2 2 |
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515 | #define TCNT1L3 3 |
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516 | #define TCNT1L4 4 |
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517 | #define TCNT1L5 5 |
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518 | #define TCNT1L6 6 |
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519 | #define TCNT1L7 7 |
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520 | |
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521 | #define TCNT1H _SFR_MEM8(0x85) |
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522 | #define TCNT1H0 0 |
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523 | #define TCNT1H1 1 |
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524 | #define TCNT1H2 2 |
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525 | #define TCNT1H3 3 |
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526 | #define TCNT1H4 4 |
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527 | #define TCNT1H5 5 |
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528 | #define TCNT1H6 6 |
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529 | #define TCNT1H7 7 |
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530 | |
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531 | #define ICR1 _SFR_MEM16(0x86) |
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532 | |
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533 | #define ICR1L _SFR_MEM8(0x86) |
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534 | #define ICR1L0 0 |
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535 | #define ICR1L1 1 |
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536 | #define ICR1L2 2 |
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537 | #define ICR1L3 3 |
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538 | #define ICR1L4 4 |
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539 | #define ICR1L5 5 |
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540 | #define ICR1L6 6 |
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541 | #define ICR1L7 7 |
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542 | |
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543 | #define ICR1H _SFR_MEM8(0x87) |
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544 | #define ICR1H0 0 |
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545 | #define ICR1H1 1 |
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546 | #define ICR1H2 2 |
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547 | #define ICR1H3 3 |
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548 | #define ICR1H4 4 |
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549 | #define ICR1H5 5 |
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550 | #define ICR1H6 6 |
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551 | #define ICR1H7 7 |
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552 | |
---|
553 | #define OCR1A _SFR_MEM16(0x88) |
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554 | |
---|
555 | #define OCR1AL _SFR_MEM8(0x88) |
---|
556 | #define OCR1AL0 0 |
---|
557 | #define OCR1AL1 1 |
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558 | #define OCR1AL2 2 |
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559 | #define OCR1AL3 3 |
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560 | #define OCR1AL4 4 |
---|
561 | #define OCR1AL5 5 |
---|
562 | #define OCR1AL6 6 |
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563 | #define OCR1AL7 7 |
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564 | |
---|
565 | #define OCR1AH _SFR_MEM8(0x89) |
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566 | #define OCR1AH0 0 |
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567 | #define OCR1AH1 1 |
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568 | #define OCR1AH2 2 |
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569 | #define OCR1AH3 3 |
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570 | #define OCR1AH4 4 |
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571 | #define OCR1AH5 5 |
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572 | #define OCR1AH6 6 |
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573 | #define OCR1AH7 7 |
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574 | |
---|
575 | #define OCR1B _SFR_MEM16(0x8A) |
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576 | |
---|
577 | #define OCR1BL _SFR_MEM8(0x8A) |
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578 | #define OCR1BL0 0 |
---|
579 | #define OCR1BL1 1 |
---|
580 | #define OCR1BL2 2 |
---|
581 | #define OCR1BL3 3 |
---|
582 | #define OCR1BL4 4 |
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583 | #define OCR1BL5 5 |
---|
584 | #define OCR1BL6 6 |
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585 | #define OCR1BL7 7 |
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586 | |
---|
587 | #define OCR1BH _SFR_MEM8(0x8B) |
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588 | #define OCR1BH0 0 |
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589 | #define OCR1BH1 1 |
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590 | #define OCR1BH2 2 |
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591 | #define OCR1BH3 3 |
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592 | #define OCR1BH4 4 |
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593 | #define OCR1BH5 5 |
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594 | #define OCR1BH6 6 |
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595 | #define OCR1BH7 7 |
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596 | |
---|
597 | #define ASSR _SFR_MEM8(0xB6) |
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598 | #define TCR0BUB 0 |
---|
599 | #define TCR0AUB 1 |
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600 | #define OCR0AUB 3 |
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601 | #define TCN0UB 4 |
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602 | #define AS0 5 |
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603 | #define EXCLK 6 |
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604 | |
---|
605 | #define USICR _SFR_MEM8(0xB8) |
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606 | #define USITC 0 |
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607 | #define USICLK 1 |
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608 | #define USICS0 2 |
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609 | #define USICS1 3 |
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610 | #define USIWM0 4 |
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611 | #define USIWM1 5 |
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612 | #define USIOIE 6 |
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613 | #define USISIE 7 |
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614 | |
---|
615 | #define USISR _SFR_MEM8(0xB9) |
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616 | #define USICNT0 0 |
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617 | #define USICNT1 1 |
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618 | #define USICNT2 2 |
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619 | #define USICNT3 3 |
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620 | #define USIDC 4 |
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621 | #define USIPF 5 |
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622 | #define USIOIF 6 |
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623 | #define USISIF 7 |
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624 | |
---|
625 | #define USIDR _SFR_MEM8(0xBA) |
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626 | #define USIDR0 0 |
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627 | #define USIDR1 1 |
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628 | #define USIDR2 2 |
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629 | #define USIDR3 3 |
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630 | #define USIDR4 4 |
---|
631 | #define USIDR5 5 |
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632 | #define USIDR6 6 |
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633 | #define USIDR7 7 |
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634 | |
---|
635 | #define USIBR _SFR_MEM8(0xBB) |
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636 | #define USIBR0 0 |
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637 | #define USIBR1 1 |
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638 | #define USIBR2 2 |
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639 | #define USIBR3 3 |
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640 | #define USIBR4 4 |
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641 | #define USIBR5 5 |
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642 | #define USIBR6 6 |
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643 | #define USIBR7 7 |
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644 | |
---|
645 | #define USIPP _SFR_MEM8(0xBC) |
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646 | #define USIPOS 0 |
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647 | |
---|
648 | #define LINCR _SFR_MEM8(0xC8) |
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649 | #define LCMD0 0 |
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650 | #define LCMD1 1 |
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651 | #define LCMD2 2 |
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652 | #define LENA 3 |
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653 | #define LCONF0 4 |
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654 | #define LCONF1 5 |
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655 | #define LIN13 6 |
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656 | #define LSWRES 7 |
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657 | |
---|
658 | #define LINSIR _SFR_MEM8(0xC9) |
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659 | #define LRXOK 0 |
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660 | #define LTXOK 1 |
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661 | #define LIDOK 2 |
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662 | #define LERR 3 |
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663 | #define LBUSY 4 |
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664 | #define LIDST0 5 |
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665 | #define LIDST1 6 |
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666 | #define LIDST2 7 |
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667 | |
---|
668 | #define LINENIR _SFR_MEM8(0xCA) |
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669 | #define LENRXOK 0 |
---|
670 | #define LENTXOK 1 |
---|
671 | #define LENIDOK 2 |
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672 | #define LENERR 3 |
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673 | |
---|
674 | #define LINERR _SFR_MEM8(0xCB) |
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675 | #define LBERR 0 |
---|
676 | #define LCERR 1 |
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677 | #define LPERR 2 |
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678 | #define LSERR 3 |
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679 | #define LFERR 4 |
---|
680 | #define LOVERR 5 |
---|
681 | #define LTOERR 6 |
---|
682 | #define LABORT 7 |
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683 | |
---|
684 | #define LINBTR _SFR_MEM8(0xCC) |
---|
685 | #define LBT0 0 |
---|
686 | #define LBT1 1 |
---|
687 | #define LBT2 2 |
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688 | #define LBT3 3 |
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689 | #define LBT4 4 |
---|
690 | #define LBT5 5 |
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691 | #define LDISR 7 |
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692 | |
---|
693 | #define LINBRR _SFR_MEM16(0xCD) |
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694 | |
---|
695 | #define LINBRRL _SFR_MEM8(0xCD) |
---|
696 | #define LDIV0 0 |
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697 | #define LDIV1 1 |
---|
698 | #define LDIV2 2 |
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699 | #define LDIV3 3 |
---|
700 | #define LDIV4 4 |
---|
701 | #define LDIV5 5 |
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702 | #define LDIV6 6 |
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703 | #define LDIV7 7 |
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704 | |
---|
705 | #define LINBRRH _SFR_MEM8(0xCE) |
---|
706 | #define LDIV8 0 |
---|
707 | #define LDIV9 1 |
---|
708 | #define LDIV10 2 |
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709 | #define LDIV11 3 |
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710 | |
---|
711 | #define LINDLR _SFR_MEM8(0xCF) |
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712 | #define LRXDL0 0 |
---|
713 | #define LRXDL1 1 |
---|
714 | #define LRXDL2 2 |
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715 | #define LRXDL3 3 |
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716 | #define LTXDL0 4 |
---|
717 | #define LTXDL1 5 |
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718 | #define LTXDL2 6 |
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719 | #define LTXDL3 7 |
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720 | |
---|
721 | #define LINIDR _SFR_MEM8(0xD0) |
---|
722 | #define LID0 0 |
---|
723 | #define LID1 1 |
---|
724 | #define LID2 2 |
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725 | #define LID3 3 |
---|
726 | #define LID4 4 |
---|
727 | #define LID5 5 |
---|
728 | #define LP0 6 |
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729 | #define LP1 7 |
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730 | |
---|
731 | #define LINSEL _SFR_MEM8(0xD1) |
---|
732 | #define LINDX0 0 |
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733 | #define LINDX1 1 |
---|
734 | #define LINDX2 2 |
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735 | #define LAINC 3 |
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736 | |
---|
737 | #define LINDAT _SFR_MEM8(0xD2) |
---|
738 | #define LDATA0 0 |
---|
739 | #define LDATA1 1 |
---|
740 | #define LDATA2 2 |
---|
741 | #define LDATA3 3 |
---|
742 | #define LDATA4 4 |
---|
743 | #define LDATA5 5 |
---|
744 | #define LDATA6 6 |
---|
745 | #define LDATA7 7 |
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746 | |
---|
747 | |
---|
748 | /* Interrupt vectors */ |
---|
749 | /* Vector 0 is the reset vector */ |
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750 | #define INT0_vect_num 1 |
---|
751 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
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752 | #define USI_OVF_vect_num 19 |
---|
753 | #define USI_OVF_vect _VECTOR(19) /* USI Overflow */ |
---|
754 | #define INT1_vect_num 2 |
---|
755 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ |
---|
756 | #define PCINT0_vect_num 3 |
---|
757 | #define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ |
---|
758 | #define PCINT1_vect_num 4 |
---|
759 | #define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ |
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760 | #define WDT_vect_num 5 |
---|
761 | #define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ |
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762 | #define TIMER1_CAPT_vect_num 6 |
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763 | #define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ |
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764 | #define TIMER1_COMPA_vect_num 7 |
---|
765 | #define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ |
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766 | #define TIMER1_COMPB_vect_num 8 |
---|
767 | #define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ |
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768 | #define TIMER1_OVF_vect_num 9 |
---|
769 | #define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ |
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770 | #define TIMER0_COMPA_vect_num 10 |
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771 | #define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ |
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772 | #define TIMER0_OVF_vect_num 11 |
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773 | #define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ |
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774 | #define LIN_TC_vect_num 12 |
---|
775 | #define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ |
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776 | #define LIN_ERR_vect_num 13 |
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777 | #define LIN_ERR_vect _VECTOR(13) /* LIN Error */ |
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778 | #define SPI_STC_vect_num 14 |
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779 | #define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ |
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780 | #define ADC_vect_num 15 |
---|
781 | #define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ |
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782 | #define EE_RDY_vect_num 16 |
---|
783 | #define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ |
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784 | #define ANA_COMP_vect_num 17 |
---|
785 | #define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ |
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786 | #define USI_START_vect_num 18 |
---|
787 | #define USI_START_vect _VECTOR(18) /* USI Start */ |
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788 | |
---|
789 | #define _VECTOR_SIZE 2 /* Size of individual vector. */ |
---|
790 | #define _VECTORS_SIZE (20 * _VECTOR_SIZE) |
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791 | |
---|
792 | |
---|
793 | /* Constants */ |
---|
794 | #define SPM_PAGESIZE (128) |
---|
795 | #define RAMSTART (0x0100) |
---|
796 | #define RAMSIZE (512) |
---|
797 | #define RAMEND (RAMSTART + RAMSIZE - 1) |
---|
798 | #define XRAMSTART (NA) |
---|
799 | #define XRAMSIZE (0) |
---|
800 | #define XRAMEND (RAMEND) |
---|
801 | #define E2END (0x1FF) |
---|
802 | #define E2PAGESIZE (4) |
---|
803 | #define FLASHEND (0x1FFF) |
---|
804 | |
---|
805 | |
---|
806 | /* Fuses */ |
---|
807 | #define FUSE_MEMORY_SIZE 3 |
---|
808 | |
---|
809 | /* Low Fuse Byte */ |
---|
810 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ |
---|
811 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ |
---|
812 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ |
---|
813 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ |
---|
814 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
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815 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
---|
816 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ |
---|
817 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
---|
818 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
---|
819 | |
---|
820 | /* High Fuse Byte */ |
---|
821 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
---|
822 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
---|
823 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
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824 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ |
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825 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ |
---|
826 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ |
---|
827 | #define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ |
---|
828 | #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ |
---|
829 | #define HFUSE_DEFAULT (FUSE_SPIEN) |
---|
830 | |
---|
831 | /* Extended Fuse Byte */ |
---|
832 | #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ |
---|
833 | #define EFUSE_DEFAULT (0xFF) |
---|
834 | |
---|
835 | |
---|
836 | /* Lock Bits */ |
---|
837 | #define __LOCK_BITS_EXIST |
---|
838 | |
---|
839 | |
---|
840 | /* Signature */ |
---|
841 | #define SIGNATURE_0 0x1E |
---|
842 | #define SIGNATURE_1 0x93 |
---|
843 | #define SIGNATURE_2 0x87 |
---|
844 | |
---|
845 | |
---|
846 | #endif /* _AVR_ATtiny87_H_ */ |
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847 | |
---|