source: rtems/cpukit/score/cpu/avr/avr/iotn48.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 14.5 KB
Line 
1/* Copyright (c) 2007 Atmel Corporation
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE.
30*/
31
32/* $Id$ */
33
34/* avr/iotn48.h - definitions for ATtiny43U */
35
36/* This file should only be included from <avr/io.h>, never directly. */
37
38#ifndef _AVR_IO_H_
39#  error "Include <avr/io.h> instead of this file."
40#endif
41
42#ifndef _AVR_IOXXX_H_
43#  define _AVR_IOXXX_H_ "iotn48.h"
44#else
45#  error "Attempt to include more than one <avr/ioXXX.h> file."
46#endif
47
48
49#ifndef _AVR_IOTN48_H_
50#define _AVR_IOTN48_H_ 1
51
52/* Registers and associated bit numbers */
53
54#define PINB _SFR_IO8(0x03)
55#define PINB0 0
56#define PINB1 1
57#define PINB2 2
58#define PINB3 3
59#define PINB4 4
60#define PINB5 5
61#define PINB6 6
62#define PINB7 7
63
64#define DDRB _SFR_IO8(0x04)
65#define DDB0 0
66#define DDB1 1
67#define DDB2 2
68#define DDB3 3
69#define DDB4 4
70#define DDB5 5
71#define DDB6 6
72#define DDB7 7
73
74#define PORTB _SFR_IO8(0x05)
75#define PORTB0 0
76#define PORTB1 1
77#define PORTB2 2
78#define PORTB3 3
79#define PORTB4 4
80#define PORTB5 5
81#define PORTB6 6
82#define PORTB7 7
83
84#define PINC _SFR_IO8(0x06)
85#define PINC0 0
86#define PINC1 1
87#define PINC2 2
88#define PINC3 3
89#define PINC4 4
90#define PINC5 5
91#define PINC6 6
92#define PINC7 7
93
94#define DDRC _SFR_IO8(0x07)
95#define DDC0 0
96#define DDC1 1
97#define DDC2 2
98#define DDC3 3
99#define DDC4 4
100#define DDC5 5
101#define DDC6 6
102#define DDC7 7
103
104#define PORTC _SFR_IO8(0x08)
105#define PORTC0 0
106#define PORTC1 1
107#define PORTC2 2
108#define PORTC3 3
109#define PORTC4 4
110#define PORTC5 5
111#define PORTC6 6
112#define PORTC7 7
113
114#define PIND _SFR_IO8(0x09)
115#define PIND0 0
116#define PIND1 1
117#define PIND2 2
118#define PIND3 3
119#define PIND4 4
120#define PIND5 5
121#define PIND6 6
122#define PIND7 7
123
124#define DDRD _SFR_IO8(0x0A)
125#define DDD0 0
126#define DDD1 1
127#define DDD2 2
128#define DDD3 3
129#define DDD4 4
130#define DDD5 5
131#define DDD6 6
132#define DDD7 7
133
134#define PORTD _SFR_IO8(0x0B)
135#define PORTD0 0
136#define PORTD1 1
137#define PORTD2 2
138#define PORTD3 3
139#define PORTD4 4
140#define PORTD5 5
141#define PORTD6 6
142#define PORTD7 7
143
144#define PINA _SFR_IO8(0x0C)
145#define PINA0 0
146#define PINA1 1
147#define PINA2 2
148#define PINA3 3
149
150#define DDRA _SFR_IO8(0x0D)
151#define DDA0 0
152#define DDA1 1
153#define DDA2 2
154#define DDA3 3
155
156#define PORTA _SFR_IO8(0x0E)
157#define PORTA0 0
158#define PORTA1 1
159#define PORTA2 2
160#define PORTA3 3
161
162#define PORTCR _SFR_IO8(0x12)
163#define PUDA 0
164#define PUDB 1
165#define PUDC 2
166#define PUDD 3
167#define BBMA 4
168#define BBMB 5
169#define BBMC 6
170#define BBMD 7
171
172#define TIFR0 _SFR_IO8(0x15)
173#define TOV0 0
174#define OCF0A 1
175#define OCF0B 2
176
177#define TIFR1 _SFR_IO8(0x16)
178#define TOV1 0
179#define OCF1A 1
180#define OCF1B 2
181#define ICF1 5
182
183#define PCIFR _SFR_IO8(0x1B)
184#define PCIF0 0
185#define PCIF1 1
186#define PCIF2 2
187#define PCIF3 3
188
189#define EIFR _SFR_IO8(0x1C)
190#define INTF0 0
191#define INTF1 1
192
193#define EIMSK _SFR_IO8(0x1D)
194#define INT0 0
195#define INT1 1
196
197#define GPIOR0 _SFR_IO8(0x1E)
198#define GPIOR00 0
199#define GPIOR01 1
200#define GPIOR02 2
201#define GPIOR03 3
202#define GPIOR04 4
203#define GPIOR05 5
204#define GPIOR06 6
205#define GPIOR07 7
206
207#define EECR _SFR_IO8(0x1F)
208#define EERE 0
209#define EEPE 1
210#define EEMPE 2
211#define EERIE 3
212#define EEPM0 4
213#define EEPM1 5
214
215#define EEDR _SFR_IO8(0x20)
216#define EEDR0 0
217#define EEDR1 1
218#define EEDR2 2
219#define EEDR3 3
220#define EEDR4 4
221#define EEDR5 5
222#define EEDR6 6
223#define EEDR7 7
224
225#define EEARL _SFR_IO8(0x21)
226#define EEAR0 0
227#define EEAR1 1
228#define EEAR2 2
229#define EEAR3 3
230#define EEAR4 4
231#define EEAR5 5
232#define EEAR6 6
233#define EEAR7 7
234
235#define GTCCR _SFR_IO8(0x23)
236#define PSRSYNC 0
237#define TSM 7
238
239#define TCCR0A _SFR_IO8(0x25)
240#define CS00 0
241#define CS01 1
242#define CS02 2
243#define CTC0 3
244
245#define TCNT0 _SFR_IO8(0x26)
246#define TCNT0_0 0
247#define TCNT0_1 1
248#define TCNT0_2 2
249#define TCNT0_3 3
250#define TCNT0_4 4
251#define TCNT0_5 5
252#define TCNT0_6 6
253#define TCNT0_7 7
254
255#define OCR0A _SFR_IO8(0x27)
256#define OCR0A_0 0
257#define OCR0A_1 1
258#define OCR0A_2 2
259#define OCR0A_3 3
260#define OCR0A_4 4
261#define OCR0A_5 5
262#define OCR0A_6 6
263#define OCR0A_7 7
264
265#define OCR0B _SFR_IO8(0x28)
266#define OCR0B_0 0
267#define OCR0B_1 1
268#define OCR0B_2 2
269#define OCR0B_3 3
270#define OCR0B_4 4
271#define OCR0B_5 5
272#define OCR0B_6 6
273#define OCR0B_7 7
274
275#define GPIOR1 _SFR_IO8(0x2A)
276#define GPIOR10 0
277#define GPIOR11 1
278#define GPIOR12 2
279#define GPIOR13 3
280#define GPIOR14 4
281#define GPIOR15 5
282#define GPIOR16 6
283#define GPIOR17 7
284
285#define GPIOR2 _SFR_IO8(0x2B)
286#define GPIOR20 0
287#define GPIOR21 1
288#define GPIOR22 2
289#define GPIOR23 3
290#define GPIOR24 4
291#define GPIOR25 5
292#define GPIOR26 6
293#define GPIOR27 7
294
295#define SPCR _SFR_IO8(0x2C)
296#define SPR0 0
297#define SPR1 1
298#define CPHA 2
299#define CPOL 3
300#define MSTR 4
301#define DORD 5
302#define SPE 6
303#define SPIE 7
304
305#define SPSR _SFR_IO8(0x2D)
306#define SPI2X 0
307#define WCOL 6
308#define SPIF 7
309
310#define SPDR _SFR_IO8(0x2E)
311#define SPDR0 0
312#define SPDR1 1
313#define SPDR2 2
314#define SPDR3 3
315#define SPDR4 4
316#define SPDR5 5
317#define SPDR6 6
318#define SPDR7 7
319
320#define ACSR _SFR_IO8(0x30)
321#define ACIS0 0
322#define ACIS1 1
323#define ACIC 2
324#define ACIE 3
325#define ACI 4
326#define ACO 5
327#define ACBG 6
328#define ACD 7
329
330#define SMCR _SFR_IO8(0x33)
331#define SE 0
332#define SM0 1
333#define SM1 2
334
335#define MCUSR _SFR_IO8(0x34)
336#define PORF 0
337#define EXTRF 1
338#define BORF 2
339#define WDRF 3
340
341#define MCUCR _SFR_IO8(0x35)
342#define PUD 4
343#define BODSE 5
344#define BODS 6
345
346#define SPMCSR _SFR_IO8(0x37)
347#define SELFPRGEN 0
348#define PGERS 1
349#define PGWRT 2
350#define RFLB 3
351#define CTPB 4
352#define RWWSB 6
353
354#define WDTCSR _SFR_MEM8(0x60)
355#define WDP0 0
356#define WDP1 1
357#define WDP2 2
358#define WDE 3
359#define WDCE 4
360#define WDP3 5
361#define WDIE 6
362#define WDIF 7
363
364#define CLKPR _SFR_MEM8(0x61)
365#define CLKPS0 0
366#define CLKPS1 1
367#define CLKPS2 2
368#define CLKPS3 3
369#define CLKPCE 7
370
371#define PRR _SFR_MEM8(0x64)
372#define PRADC 0
373#define PRSPI 2
374#define PRTIM1 3
375#define PRTIM0 5
376#define PRTWI 7
377
378#define OSCCAL _SFR_MEM8(0x66)
379#define CAL0 0
380#define CAL1 1
381#define CAL2 2
382#define CAL3 3
383#define CAL4 4
384#define CAL5 5
385#define CAL6 6
386#define CAL7 7
387
388#define PCICR _SFR_MEM8(0x68)
389#define PCIE0 0
390#define PCIE1 1
391#define PCIE2 2
392#define PCIE3 3
393
394#define EICRA _SFR_MEM8(0x69)
395#define ISC00 0
396#define ISC01 1
397#define ISC10 2
398#define ISC11 3
399
400#define PCMSK3 _SFR_MEM8(0x6A)
401#define PCINT24 0
402#define PCINT25 1
403#define PCINT26 2
404#define PCINT27 3
405
406#define PCMSK0 _SFR_MEM8(0x6B)
407#define PCINT0 0
408#define PCINT1 1
409#define PCINT2 2
410#define PCINT3 3
411#define PCINT4 4
412#define PCINT5 5
413#define PCINT6 6
414#define PCINT7 7
415
416#define PCMSK1 _SFR_MEM8(0x6C)
417#define PCINT8 0
418#define PCINT9 1
419#define PCINT10 2
420#define PCINT11 3
421#define PCINT12 4
422#define PCINT13 5
423#define PCINT14 6
424#define PCINT15 7
425
426#define PCMSK2 _SFR_MEM8(0x6D)
427#define PCINT16 0
428#define PCINT17 1
429#define PCINT18 2
430#define PCINT19 3
431#define PCINT20 4
432#define PCINT21 5
433#define PCINT22 6
434#define PCINT23 7
435
436#define TIMSK0 _SFR_MEM8(0x6E)
437#define TOIE0 0
438#define OCIE0A 1
439#define OCIE0B 2
440
441#define TIMSK1 _SFR_MEM8(0x6F)
442#define TOIE1 0
443#define OCIE1A 1
444#define OCIE1B 2
445#define ICIE1 5
446
447#ifndef __ASSEMBLER__
448#define ADC     _SFR_MEM16(0x78)
449#endif
450#define ADCW    _SFR_MEM16(0x78)
451
452#define ADCL _SFR_MEM8(0x78)
453#define ADCL0 0
454#define ADCL1 1
455#define ADCL2 2
456#define ADCL3 3
457#define ADCL4 4
458#define ADCL5 5
459#define ADCL6 6
460#define ADCL7 7
461
462#define ADCH _SFR_MEM8(0x79)
463#define ADCH0 0
464#define ADCH1 1
465#define ADCH2 2
466#define ADCH3 3
467#define ADCH4 4
468#define ADCH5 5
469#define ADCH6 6
470#define ADCH7 7
471
472#define ADCSRA _SFR_MEM8(0x7A)
473#define ADPS0 0
474#define ADPS1 1
475#define ADPS2 2
476#define ADIE 3
477#define ADIF 4
478#define ADATE 5
479#define ADSC 6
480#define ADEN 7
481
482#define ADCSRB _SFR_MEM8(0x7B)
483#define ADTS0 0
484#define ADTS1 1
485#define ADTS2 2
486#define ACME 6
487
488#define ADMUX _SFR_MEM8(0x7C)
489#define MUX0 0
490#define MUX1 1
491#define MUX2 2
492#define MUX3 3
493#define ADLAR 5
494#define REFS0 6
495
496#define DIDR0 _SFR_MEM8(0x7E)
497#define ADC0D 0
498#define ADC1D 1
499#define ADC2D 2
500#define ADC3D 3
501#define ADC4D 4
502#define ADC5D 5
503#define ADC6D 6
504#define ADC7D 7
505
506#define DIDR1 _SFR_MEM8(0x7F)
507#define AIN0D 0
508#define AIN1D 1
509
510#define TCCR1A _SFR_MEM8(0x80)
511#define WGM10 0
512#define WGM11 1
513#define COM1B0 4
514#define COM1B1 5
515#define COM1A0 6
516#define COM1A1 7
517
518#define TCCR1B _SFR_MEM8(0x81)
519#define CS10 0
520#define CS11 1
521#define CS12 2
522#define WGM12 3
523#define WGM13 4
524#define ICES1 6
525#define ICNC1 7
526
527#define TCCR1C _SFR_MEM8(0x82)
528#define FOC1B 6
529#define FOC1A 7
530
531#define TCNT1 _SFR_MEM16(0x84)
532
533#define TCNT1L _SFR_MEM8(0x84)
534#define TCNT1L0 0
535#define TCNT1L1 1
536#define TCNT1L2 2
537#define TCNT1L3 3
538#define TCNT1L4 4
539#define TCNT1L5 5
540#define TCNT1L6 6
541#define TCNT1L7 7
542
543#define TCNT1H _SFR_MEM8(0x85)
544#define TCNT1H0 0
545#define TCNT1H1 1
546#define TCNT1H2 2
547#define TCNT1H3 3
548#define TCNT1H4 4
549#define TCNT1H5 5
550#define TCNT1H6 6
551#define TCNT1H7 7
552
553#define ICR1 _SFR_MEM16(0x86)
554
555#define ICR1L _SFR_MEM8(0x86)
556#define ICR1L0 0
557#define ICR1L1 1
558#define ICR1L2 2
559#define ICR1L3 3
560#define ICR1L4 4
561#define ICR1L5 5
562#define ICR1L6 6
563#define ICR1L7 7
564
565#define ICR1H _SFR_MEM8(0x87)
566#define ICR1H0 0
567#define ICR1H1 1
568#define ICR1H2 2
569#define ICR1H3 3
570#define ICR1H4 4
571#define ICR1H5 5
572#define ICR1H6 6
573#define ICR1H7 7
574
575#define OCR1A _SFR_MEM16(0x88)
576
577#define OCR1AL _SFR_MEM8(0x88)
578#define OCR1AL0 0
579#define OCR1AL1 1
580#define OCR1AL2 2
581#define OCR1AL3 3
582#define OCR1AL4 4
583#define OCR1AL5 5
584#define OCR1AL6 6
585#define OCR1AL7 7
586
587#define OCR1AH _SFR_MEM8(0x89)
588#define OCR1AH0 0
589#define OCR1AH1 1
590#define OCR1AH2 2
591#define OCR1AH3 3
592#define OCR1AH4 4
593#define OCR1AH5 5
594#define OCR1AH6 6
595#define OCR1AH7 7
596
597#define OCR1B _SFR_MEM16(0x8A)
598
599#define OCR1BL _SFR_MEM8(0x8A)
600#define OCR1BL0 0
601#define OCR1BL1 1
602#define OCR1BL2 2
603#define OCR1BL3 3
604#define OCR1BL4 4
605#define OCR1BL5 5
606#define OCR1BL6 6
607#define OCR1BL7 7
608
609#define OCR1BH _SFR_MEM8(0x8B)
610#define OCR1BH0 0
611#define OCR1BH1 1
612#define OCR1BH2 2
613#define OCR1BH3 3
614#define OCR1BH4 4
615#define OCR1BH5 5
616#define OCR1BH6 6
617#define OCR1BH7 7
618
619#define TWBR _SFR_MEM8(0xB8)
620#define TWBR0 0
621#define TWBR1 1
622#define TWBR2 2
623#define TWBR3 3
624#define TWBR4 4
625#define TWBR5 5
626#define TWBR6 6
627#define TWBR7 7
628
629#define TWSR _SFR_MEM8(0xB9)
630#define TWPS0 0
631#define TWPS1 1
632#define TWS3 2
633#define TWS4 3
634#define TWS5 4
635#define TWS6 5
636#define TWS7 6
637
638#define TWAR _SFR_MEM8(0xBA)
639#define TWGCE 0
640#define TWA0 1
641#define TWA1 2
642#define TWA2 3
643#define TWA3 4
644#define TWA4 5
645#define TWA5 6
646#define TWA6 7
647
648#define TWDR _SFR_MEM8(0xBB)
649#define TWD0 0
650#define TWD1 1
651#define TWD2 2
652#define TWD3 3
653#define TWD4 4
654#define TWD5 5
655#define TWD6 6
656#define TWD7 7
657
658#define TWCR _SFR_MEM8(0xBC)
659#define TWIE 0
660#define TWEN 2
661#define TWWC 3
662#define TWSTO 4
663#define TWSTA 5
664#define TWEA 6
665#define TWINT 7
666
667#define TWAMR _SFR_MEM8(0xBD)
668#define TWAM0 1
669#define TWAM1 2
670#define TWAM2 3
671#define TWAM3 4
672#define TWAM4 5
673#define TWAM5 6
674#define TWAM6 7
675
676#define TWIHSR _SFR_MEM8(0xBE)  /* Deprecated */
677#define TWHSR _SFR_MEM8(0xBE)
678#define TWIHS 0
679
680
681/* Interrupt Vectors */
682/* Interrupt vector 0 is the reset vector. */
683
684#define INT0_vect         _VECTOR(1)
685#define INT1_vect         _VECTOR(2)
686#define PCINT0_vect       _VECTOR(3)
687#define PCINT1_vect       _VECTOR(4)
688#define PCINT2_vect       _VECTOR(5)
689#define PCINT3_vect       _VECTOR(6)
690#define WDT_vect          _VECTOR(7)
691#define TIMER1_CAPT_vect  _VECTOR(8)
692#define TIMER1_COMPA_vect _VECTOR(9)
693#define TIMER1_COMPB_vect _VECTOR(10)
694#define TIMER1_OVF_vect   _VECTOR(11)
695#define TIMER0_COMPA_vect _VECTOR(12)
696#define TIMER0_COMPB_vect _VECTOR(13)
697#define TIMER0_OVF_vect   _VECTOR(14)
698#define SPI_STC_vect      _VECTOR(15)
699#define ADC_vect          _VECTOR(16)
700#define EE_READY_vect     _VECTOR(17)
701#define ANALOG_COMP_vect  _VECTOR(18)
702#define TWI_vect          _VECTOR(19)
703
704#define _VECTORS_SIZE 40
705
706
707/* Constants */
708#define SPM_PAGESIZE 32
709#define RAMEND       0x1FF
710#define XRAMSIZE     0
711#define XRAMEND      RAMEND
712#define E2END        0x3F
713#define E2PAGESIZE   4
714#define FLASHEND     0xFFF
715
716
717/* Fuse Information */
718#define FUSE_MEMORY_SIZE 3
719
720/* Low Fuse Byte */
721#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */
722#define FUSE_CKOUT  (unsigned char)~_BV(6) /* Clock output */
723#define FUSE_SUT1   (unsigned char)~_BV(5) /* Select start-up time */
724#define FUSE_SUT0   (unsigned char)~_BV(4) /* Select start-up time */
725#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */
726#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */
727#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */
728#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */
729#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
730
731/* High Fuse Byte */
732#define FUSE_BODLEVEL0   (unsigned char)~_BV(0) /* Brown-out Detector trigger level */
733#define FUSE_BODLEVEL1   (unsigned char)~_BV(1) /* Brown-out Detector trigger level */
734#define FUSE_BODLEVEL2   (unsigned char)~_BV(2) /* Brown-out Detector trigger level */
735#define FUSE_EESAVE      (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */
736#define FUSE_WDTON       (unsigned char)~_BV(4) /* Watchdog Timer Always On */
737#define FUSE_SPIEN       (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
738#define FUSE_DWEN        (unsigned char)~_BV(6) /* debugWIRE Enable */
739#define FUSE_RSTDISBL    (unsigned char)~_BV(7) /* External reset disable */
740#define HFUSE_DEFAULT (FUSE_SPIEN)   
741
742/* Extended Fuse Byte */
743#define FUSE_SELFPRGEN   (unsigned char)~_BV(0) /* Self Programming Enable */
744#define EFUSE_DEFAULT (0xFF)
745
746
747/* Lock Bits */
748#define __LOCK_BITS_EXIST
749
750
751/* Signature */
752#define SIGNATURE_0 0x1E
753#define SIGNATURE_1 0x92
754#define SIGNATURE_2 0x09
755
756
757#endif /* _AVR_IOTN48_H_ */
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