[04a62dce] | 1 | /* Copyright (c) 2007 Atmel Corporation |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. |
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| 30 | */ |
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| 31 | |
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| 32 | /* $Id$ */ |
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| 33 | |
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| 34 | /* avr/iotn43u.h - definitions for ATtiny43U */ |
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| 35 | |
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| 36 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 37 | |
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| 38 | #ifndef _AVR_IO_H_ |
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| 39 | # error "Include <avr/io.h> instead of this file." |
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| 40 | #endif |
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| 41 | |
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| 42 | #ifndef _AVR_IOXXX_H_ |
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| 43 | # define _AVR_IOXXX_H_ "iotn43u.h" |
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| 44 | #else |
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| 45 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 46 | #endif |
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| 47 | |
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| 48 | |
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| 49 | #ifndef _AVR_IOTN43U_H_ |
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| 50 | #define _AVR_IOTN43U_H_ 1 |
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| 51 | |
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| 52 | /* Registers and associated bit numbers */ |
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| 53 | |
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| 54 | #define PRR _SFR_IO8(0x00) |
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| 55 | #define PRADC 0 |
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| 56 | #define PRUSI 1 |
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| 57 | #define PRTIM0 2 |
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| 58 | #define PRTIM1 3 |
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| 59 | |
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| 60 | #define DIDR0 _SFR_IO8(0x01) |
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| 61 | #define ADC0D 0 |
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| 62 | #define ADC1D 1 |
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| 63 | #define ADC2D 2 |
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| 64 | #define ADC3D 3 |
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| 65 | #define AIN0D 4 |
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| 66 | #define AIN1D 5 |
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| 67 | |
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| 68 | /* Reserved [0x02] */ |
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| 69 | |
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| 70 | #define ADCSRB _SFR_IO8(0x03) |
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| 71 | #define ADTS0 0 |
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| 72 | #define ADTS1 1 |
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| 73 | #define ADTS2 2 |
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| 74 | #define ADLAR 4 |
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| 75 | #define ACME 6 |
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| 76 | |
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| 77 | #define ADC _SFR_IO16(0x04) |
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| 78 | |
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| 79 | #define ADCL _SFR_IO8(0x04) |
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| 80 | #define ADCL0 0 |
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| 81 | #define ADCL1 1 |
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| 82 | #define ADCL2 2 |
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| 83 | #define ADCL3 3 |
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| 84 | #define ADCL4 4 |
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| 85 | #define ADCL5 5 |
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| 86 | #define ADCL6 6 |
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| 87 | #define ADCL7 7 |
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| 88 | |
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| 89 | #define ADCH _SFR_IO8(0x05) |
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| 90 | #define ADCH0 0 |
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| 91 | #define ADCH1 1 |
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| 92 | #define ADCH2 2 |
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| 93 | #define ADCH3 3 |
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| 94 | #define ADCH4 4 |
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| 95 | #define ADCH5 5 |
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| 96 | #define ADCH6 6 |
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| 97 | #define ADCH7 7 |
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| 98 | |
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| 99 | #define ADCSRA _SFR_IO8(0x06) |
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| 100 | #define ADPS0 0 |
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| 101 | #define ADPS1 1 |
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| 102 | #define ADPS2 2 |
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| 103 | #define ADIE 3 |
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| 104 | #define ADIF 4 |
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| 105 | #define ADATE 5 |
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| 106 | #define ADSC 6 |
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| 107 | #define ADEN 7 |
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| 108 | |
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| 109 | #define ADMUX _SFR_IO8(0x07) |
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| 110 | #define MUX0 0 |
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| 111 | #define MUX1 1 |
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| 112 | #define MUX2 2 |
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| 113 | #define REFS0 6 |
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| 114 | |
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| 115 | #define ACSR _SFR_IO8(0x08) |
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| 116 | #define ACIS0 0 |
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| 117 | #define ACIS1 1 |
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| 118 | #define ACIE 3 |
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| 119 | #define ACI 4 |
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| 120 | #define ACO 5 |
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| 121 | #define ACBG 6 |
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| 122 | #define ACD 7 |
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| 123 | |
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| 124 | /* Reserved [0x09], [0x0A] */ |
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| 125 | |
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| 126 | #define TIFR1 _SFR_IO8(0x0B) |
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| 127 | #define TOV1 0 |
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| 128 | #define OCF1A 1 |
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| 129 | #define OCF1B 2 |
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| 130 | |
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| 131 | #define TIMSK1 _SFR_IO8(0x0C) |
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| 132 | #define TOIE1 0 |
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| 133 | #define OCIE1A 1 |
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| 134 | #define OCIE1B 2 |
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| 135 | |
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| 136 | #define USICR _SFR_IO8(0x0D) |
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| 137 | #define USITC 0 |
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| 138 | #define USICLK 1 |
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| 139 | #define USICS0 2 |
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| 140 | #define USICS1 3 |
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| 141 | #define USIWM0 4 |
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| 142 | #define USIWM1 5 |
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| 143 | #define USIOIE 6 |
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| 144 | #define USISIE 7 |
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| 145 | |
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| 146 | #define USISR _SFR_IO8(0x0E) |
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| 147 | #define USICNT0 0 |
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| 148 | #define USICNT1 1 |
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| 149 | #define USICNT2 2 |
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| 150 | #define USICNT3 3 |
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| 151 | #define USIDC 4 |
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| 152 | #define USIPF 5 |
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| 153 | #define USIOIF 6 |
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| 154 | #define USISIF 7 |
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| 155 | |
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| 156 | #define USIDR _SFR_IO8(0x0F) |
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| 157 | #define USIDR0 0 |
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| 158 | #define USIDR1 1 |
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| 159 | #define USIDR2 2 |
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| 160 | #define USIDR3 3 |
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| 161 | #define USIDR4 4 |
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| 162 | #define USIDR5 5 |
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| 163 | #define USIDR6 6 |
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| 164 | #define USIDR7 7 |
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| 165 | |
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| 166 | #define USIBR _SFR_IO8(0x10) |
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| 167 | #define USIBR0 0 |
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| 168 | #define USIBR1 1 |
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| 169 | #define USIBR2 2 |
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| 170 | #define USIBR3 3 |
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| 171 | #define USIBR4 4 |
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| 172 | #define USIBR5 5 |
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| 173 | #define USIBR6 6 |
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| 174 | #define USIBR7 7 |
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| 175 | |
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| 176 | /* Reserved [0x11] */ |
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| 177 | |
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| 178 | #define PCMSK0 _SFR_IO8(0x12) |
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| 179 | #define PCINT0 0 |
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| 180 | #define PCINT1 1 |
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| 181 | #define PCINT2 2 |
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| 182 | #define PCINT3 3 |
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| 183 | #define PCINT4 4 |
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| 184 | #define PCINT5 5 |
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| 185 | #define PCINT6 6 |
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| 186 | #define PCINT7 7 |
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| 187 | |
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| 188 | #define GPIOR0 _SFR_IO8(0x13) |
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| 189 | #define GPIOR00 0 |
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| 190 | #define GPIOR01 1 |
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| 191 | #define GPIOR02 2 |
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| 192 | #define GPIOR03 3 |
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| 193 | #define GPIOR04 4 |
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| 194 | #define GPIOR05 5 |
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| 195 | #define GPIOR06 6 |
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| 196 | #define GPIOR07 7 |
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| 197 | |
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| 198 | #define GPIOR1 _SFR_IO8(0x14) |
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| 199 | #define GPIOR10 0 |
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| 200 | #define GPIOR11 1 |
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| 201 | #define GPIOR12 2 |
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| 202 | #define GPIOR13 3 |
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| 203 | #define GPIOR14 4 |
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| 204 | #define GPIOR15 5 |
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| 205 | #define GPIOR16 6 |
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| 206 | #define GPIOR17 7 |
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| 207 | |
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| 208 | #define GPIOR2 _SFR_IO8(0x15) |
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| 209 | #define GPIOR20 0 |
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| 210 | #define GPIOR21 1 |
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| 211 | #define GPIOR22 2 |
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| 212 | #define GPIOR23 3 |
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| 213 | #define GPIOR24 4 |
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| 214 | #define GPIOR25 5 |
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| 215 | #define GPIOR26 6 |
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| 216 | #define GPIOR27 7 |
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| 217 | |
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| 218 | #define PINB _SFR_IO8(0x16) |
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| 219 | #define PINB0 0 |
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| 220 | #define PINB1 1 |
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| 221 | #define PINB2 2 |
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| 222 | #define PINB3 3 |
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| 223 | #define PINB4 4 |
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| 224 | #define PINB5 5 |
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| 225 | #define PINB6 6 |
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| 226 | #define PINB7 7 |
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| 227 | |
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| 228 | #define DDRB _SFR_IO8(0x17) |
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| 229 | #define DDB0 0 |
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| 230 | #define DDB1 1 |
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| 231 | #define DDB2 2 |
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| 232 | #define DDB3 3 |
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| 233 | #define DDB4 4 |
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| 234 | #define DDB5 5 |
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| 235 | #define DDB6 6 |
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| 236 | #define DDB7 7 |
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| 237 | |
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| 238 | #define PORTB _SFR_IO8(0x18) |
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| 239 | #define PORTB0 0 |
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| 240 | #define PORTB1 1 |
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| 241 | #define PORTB2 2 |
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| 242 | #define PORTB3 3 |
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| 243 | #define PORTB4 4 |
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| 244 | #define PORTB5 5 |
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| 245 | #define PORTB6 6 |
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| 246 | #define PORTB7 7 |
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| 247 | |
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| 248 | #define PINA _SFR_IO8(0x19) |
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| 249 | #define PINA0 0 |
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| 250 | #define PINA1 1 |
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| 251 | #define PINA2 2 |
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| 252 | #define PINA3 3 |
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| 253 | #define PINA4 4 |
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| 254 | #define PINA5 5 |
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| 255 | #define PINA6 6 |
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| 256 | #define PINA7 7 |
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| 257 | |
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| 258 | #define DDRA _SFR_IO8(0x1A) |
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| 259 | #define DDA0 0 |
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| 260 | #define DDA1 1 |
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| 261 | #define DDA2 2 |
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| 262 | #define DDA3 3 |
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| 263 | #define DDA4 4 |
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| 264 | #define DDA5 5 |
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| 265 | #define DDA6 6 |
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| 266 | #define DDA7 7 |
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| 267 | |
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| 268 | #define PORTA _SFR_IO8(0x1B) |
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| 269 | #define PORTA0 0 |
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| 270 | #define PORTA1 1 |
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| 271 | #define PORTA2 2 |
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| 272 | #define PORTA3 3 |
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| 273 | #define PORTA4 4 |
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| 274 | #define PORTA5 5 |
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| 275 | #define PORTA6 6 |
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| 276 | #define PORTA7 7 |
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| 277 | |
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| 278 | /* EEPROM Control Register */ |
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| 279 | #define EECR _SFR_IO8(0x1C) |
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| 280 | #define EERE 0 |
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| 281 | #define EEPE 1 |
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| 282 | #define EEMPE 2 |
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| 283 | #define EERIE 3 |
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| 284 | #define EEPM0 4 |
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| 285 | #define EEPM1 5 |
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| 286 | |
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| 287 | /* EEPROM Data Register */ |
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| 288 | #define EEDR _SFR_IO8(0x1D) |
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| 289 | |
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| 290 | /* EEPROM Address Register */ |
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| 291 | #define EEARL _SFR_IO8(0x1E) |
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| 292 | |
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| 293 | /* Reserved [0x1F] */ |
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| 294 | |
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| 295 | #define PCMSK1 _SFR_IO8(0x20) |
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| 296 | #define PCINT8 0 |
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| 297 | #define PCINT9 1 |
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| 298 | #define PCINT10 2 |
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| 299 | #define PCINT11 3 |
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| 300 | |
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| 301 | #define WDTCSR _SFR_IO8(0x21) |
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| 302 | #define WDP0 0 |
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| 303 | #define WDP1 1 |
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| 304 | #define WDP2 2 |
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| 305 | #define WDE 3 |
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| 306 | #define WDCE 4 |
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| 307 | #define WDP3 5 |
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| 308 | #define WDIE 6 |
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| 309 | #define WDIF 7 |
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| 310 | |
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| 311 | /* Reserved [0x22] */ |
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| 312 | |
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| 313 | #define GTCCR _SFR_IO8(0x23) |
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| 314 | #define PSR10 0 |
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| 315 | #define TSM 7 |
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| 316 | |
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| 317 | /* Reserved [0x24], [0x25] */ |
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| 318 | |
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| 319 | #define CLKPR _SFR_IO8(0x26) |
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| 320 | #define CLKPS0 0 |
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| 321 | #define CLKPS1 1 |
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| 322 | #define CLKPS2 2 |
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| 323 | #define CLKPS3 3 |
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| 324 | #define CLKPCE 7 |
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| 325 | |
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| 326 | /* Reserved [0x27],[0x28],[0x29],[0x2A] */ |
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| 327 | |
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| 328 | #define OCR1B _SFR_IO8(0x2B) |
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| 329 | #define OCR1B_0 0 |
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| 330 | #define OCR1B_1 1 |
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| 331 | #define OCR1B_2 2 |
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| 332 | #define OCR1B_3 3 |
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| 333 | #define OCR1B_4 4 |
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| 334 | #define OCR1B_5 5 |
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| 335 | #define OCR1B_6 6 |
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| 336 | #define OCR1B_7 7 |
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| 337 | |
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| 338 | #define OCR1A _SFR_IO8(0x2C) |
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| 339 | #define OCR1A_0 0 |
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| 340 | #define OCR1A_1 1 |
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| 341 | #define OCRA1_2 2 |
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| 342 | #define OCRA1_3 3 |
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| 343 | #define OCRA1_4 4 |
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| 344 | #define OCRA1_5 5 |
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| 345 | #define OCRA1_6 6 |
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| 346 | #define OCRA1_7 7 |
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| 347 | |
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| 348 | #define TCNT1 _SFR_IO8(0x2D) |
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| 349 | #define TCNT1_0 0 |
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| 350 | #define TCNT1_1 1 |
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| 351 | #define TCNT1_2 2 |
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| 352 | #define TCNT1_3 3 |
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| 353 | #define TCNT1_4 4 |
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| 354 | #define TCNT1_5 5 |
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| 355 | #define TCNT1_6 6 |
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| 356 | #define TCNT1_7 7 |
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| 357 | |
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| 358 | #define TCCR1B _SFR_IO8(0x2E) |
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| 359 | #define CS10 0 |
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| 360 | #define CS11 1 |
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| 361 | #define CS12 2 |
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| 362 | #define WGM12 3 |
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| 363 | #define FOC1B 6 |
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| 364 | #define FOC1A 7 |
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| 365 | |
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| 366 | #define TCCR1A _SFR_IO8(0x2F) |
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| 367 | #define WGM10 0 |
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| 368 | #define WGM11 1 |
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| 369 | #define COM1B0 4 |
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| 370 | #define COM1B1 5 |
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| 371 | #define COM1A0 6 |
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| 372 | #define COM1A1 7 |
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| 373 | |
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| 374 | #define TCCR0A _SFR_IO8(0x30) |
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| 375 | #define WGM00 0 |
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| 376 | #define WGM01 1 |
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| 377 | #define COM0B0 4 |
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| 378 | #define COM0B1 5 |
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| 379 | #define COM0A0 6 |
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| 380 | #define COM0A1 7 |
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| 381 | |
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| 382 | #define OSCCAL _SFR_IO8(0x31) |
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| 383 | #define CAL0 0 |
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| 384 | #define CAL1 1 |
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| 385 | #define CAL2 2 |
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| 386 | #define CAL3 3 |
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| 387 | #define CAL4 4 |
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| 388 | #define CAL5 5 |
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| 389 | #define CAL6 6 |
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| 390 | #define CAL7 7 |
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| 391 | |
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| 392 | #define TCNT0 _SFR_IO8(0x32) |
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| 393 | #define TCNT0_0 0 |
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| 394 | #define TCNT0_1 1 |
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| 395 | #define TCNT0_2 2 |
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| 396 | #define TCNT0_3 3 |
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| 397 | #define TCNT0_4 4 |
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| 398 | #define TCNT0_5 5 |
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| 399 | #define TCNT0_6 6 |
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| 400 | #define TCNT0_7 7 |
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| 401 | |
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| 402 | #define TCCR0B _SFR_IO8(0x33) |
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| 403 | #define CS00 0 |
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| 404 | #define CS01 1 |
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| 405 | #define CS02 2 |
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| 406 | #define WGM02 3 |
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| 407 | #define FOC0B 6 |
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| 408 | #define FOC0A 7 |
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| 409 | |
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| 410 | #define MCUSR _SFR_IO8(0x34) |
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| 411 | #define PORF 0 |
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| 412 | #define EXTRF 1 |
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| 413 | #define BORF 2 |
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| 414 | #define WDRF 3 |
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| 415 | |
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| 416 | #define MCUCR _SFR_IO8(0x35) |
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| 417 | #define ISC00 0 |
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| 418 | #define ISC01 1 |
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| 419 | #define BODSE 2 |
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| 420 | #define SM0 3 |
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| 421 | #define SM1 4 |
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| 422 | #define SE 5 |
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| 423 | #define PUD 6 |
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| 424 | #define BODS 7 |
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| 425 | |
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| 426 | #define OCR0A _SFR_IO8(0x36) |
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| 427 | #define OCR0A_0 0 |
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| 428 | #define OCR0A_1 1 |
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| 429 | #define OCR0A_2 2 |
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| 430 | #define OCR0A_3 3 |
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| 431 | #define OCR0A_4 4 |
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| 432 | #define OCR0A_5 5 |
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| 433 | #define OCR0A_6 6 |
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| 434 | #define OCR0A_7 7 |
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| 435 | |
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| 436 | #define SPMCSR _SFR_IO8(0x37) |
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| 437 | #define SPMEN 0 |
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| 438 | #define PGERS 1 |
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| 439 | #define PGWRT 2 |
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| 440 | #define RFLB 3 |
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| 441 | #define CTPB 4 |
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| 442 | |
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| 443 | #define TIFR0 _SFR_IO8(0x38) |
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| 444 | #define TOV0 0 |
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| 445 | #define OCF0A 1 |
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| 446 | #define OCF0B 2 |
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| 447 | |
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| 448 | #define TIMSK0 _SFR_IO8(0x39) |
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| 449 | #define TOIE0 0 |
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| 450 | #define OCIE0A 1 |
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| 451 | #define OCIE0B 2 |
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| 452 | |
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| 453 | #define GIFR _SFR_IO8(0x3A) |
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| 454 | #define PCIF0 4 |
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| 455 | #define PCIF1 5 |
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| 456 | #define INTF0 6 |
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| 457 | |
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| 458 | #define GIMSK _SFR_IO8(0x3B) |
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| 459 | #define PCIE0 4 |
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| 460 | #define PCIE1 5 |
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| 461 | #define INT0 6 |
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| 462 | |
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| 463 | #define OCR0B _SFR_IO8(0x3C) |
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| 464 | #define OCR0B_0 0 |
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| 465 | #define OCR0B_1 1 |
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| 466 | #define OCR0B_2 2 |
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| 467 | #define OCR0B_3 3 |
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| 468 | #define OCR0B_4 4 |
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| 469 | #define OCR0B_5 5 |
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| 470 | #define OCR0B_6 6 |
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| 471 | #define OCR0B_7 7 |
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| 472 | |
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| 473 | |
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| 474 | |
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| 475 | /* Interrupt Vectors */ |
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| 476 | /* Interrupt vector 0 is the reset vector. */ |
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| 477 | |
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| 478 | /* External Interrupt Request 0 */ |
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| 479 | #define INT0_vect _VECTOR(1) |
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| 480 | |
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| 481 | /* Pin Change Interrupt Request 0 */ |
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| 482 | #define PCINT0_vect _VECTOR(2) |
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| 483 | |
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| 484 | /* Pin Change Interrupt Request 1 */ |
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| 485 | #define PCINT1_vect _VECTOR(3) |
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| 486 | |
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| 487 | /* Watchdog Time-out */ |
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| 488 | #define WDT_vect _VECTOR(4) |
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| 489 | |
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| 490 | /* Timer/Counter1 Compare Match A */ |
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| 491 | #define TIM1_COMPA_vect _VECTOR(5) |
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| 492 | |
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| 493 | /* Timer/Counter1 Compare Match B */ |
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| 494 | #define TIM1_COMPB_vect _VECTOR(6) |
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| 495 | |
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| 496 | /* Timer/Counter1 Overflow */ |
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| 497 | #define TIM1_OVF_vect _VECTOR(7) |
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| 498 | |
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| 499 | /* Timer/Counter0 Compare Match A */ |
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| 500 | #define TIM0_COMPA_vect _VECTOR(8) |
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| 501 | |
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| 502 | /* Timer/Counter0 Compare Match B */ |
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| 503 | #define TIM0_COMPB_vect _VECTOR(9) |
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| 504 | |
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| 505 | /* Timer/Counter0 Overflow */ |
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| 506 | #define TIM0_OVF_vect _VECTOR(10) |
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| 507 | |
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| 508 | /* Analog Comparator */ |
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| 509 | #define ANA_COMP_vect _VECTOR(11) |
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| 510 | |
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| 511 | /* ADC Conversion Complete */ |
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| 512 | #define ADC_vect _VECTOR(12) |
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| 513 | |
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| 514 | /* EEPROM Ready */ |
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| 515 | #define EE_RDY_vect _VECTOR(13) |
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| 516 | |
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| 517 | /* USI START */ |
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| 518 | #define USI_START_vect _VECTOR(14) |
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| 519 | |
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| 520 | /* USI Overflow */ |
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| 521 | #define USI_OVF_vect _VECTOR(15) |
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| 522 | |
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| 523 | #define _VECTORS_SIZE 32 |
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| 524 | |
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| 525 | |
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| 526 | /* Constants */ |
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| 527 | #define SPM_PAGESIZE 64 |
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| 528 | #define RAMEND 0x15F |
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| 529 | #define XRAMEND RAMEND |
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| 530 | #define E2END 0x3F |
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| 531 | #define E2PAGESIZE 4 |
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| 532 | #define FLASHEND 0xFFF |
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| 533 | |
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| 534 | |
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| 535 | /* Fuse Information */ |
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| 536 | #define FUSE_MEMORY_SIZE 3 |
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| 537 | |
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| 538 | /* Low Fuse Byte */ |
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| 539 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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| 540 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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| 541 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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| 542 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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| 543 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
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| 544 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
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| 545 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
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| 546 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
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| 547 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
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| 548 | |
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| 549 | /* High Fuse Byte */ |
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| 550 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) |
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| 551 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) |
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| 552 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) |
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| 553 | #define FUSE_EESAVE (unsigned char)~_BV(3) |
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| 554 | #define FUSE_WDTON (unsigned char)~_BV(4) |
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| 555 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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| 556 | #define FUSE_DWEN (unsigned char)~_BV(6) |
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| 557 | #define FUSE_RSTDISBL (unsigned char)~_BV(7) |
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| 558 | #define HFUSE_DEFAULT (FUSE_SPIEN) |
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| 559 | |
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| 560 | /* Extended Fuse Byte */ |
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| 561 | #define FUSE_SELFPRGEN (unsigned char)~_BV(0) |
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| 562 | #define EFUSE_DEFAULT (0xFF) |
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| 563 | |
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| 564 | |
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| 565 | /* Lock Bits */ |
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| 566 | #define __LOCK_BITS_EXIST |
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| 567 | |
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| 568 | |
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| 569 | /* Signature */ |
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| 570 | #define SIGNATURE_0 0x1E |
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| 571 | #define SIGNATURE_1 0x92 |
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| 572 | #define SIGNATURE_2 0x0C |
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| 573 | |
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| 574 | |
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| 575 | #endif /* _AVR_IOTN43U_H_ */ |
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