1 | /* Copyright (c) 2009 Atmel Corporation |
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2 | All rights reserved. |
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3 | |
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4 | Redistribution and use in source and binary forms, with or without |
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5 | modification, are permitted provided that the following conditions are met: |
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6 | |
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7 | * Redistributions of source code must retain the above copyright |
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8 | notice, this list of conditions and the following disclaimer. |
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9 | |
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10 | * Redistributions in binary form must reproduce the above copyright |
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11 | notice, this list of conditions and the following disclaimer in |
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12 | the documentation and/or other materials provided with the |
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13 | distribution. |
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14 | |
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15 | * Neither the name of the copyright holders nor the names of |
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16 | contributors may be used to endorse or promote products derived |
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17 | from this software without specific prior written permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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29 | POSSIBILITY OF SUCH DAMAGE. */ |
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30 | |
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31 | |
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32 | /* avr/iotn2313a.h - definitions for ATtiny2313A */ |
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33 | |
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34 | /* This file should only be included from <avr/io.h>, never directly. */ |
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35 | |
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36 | #ifndef _AVR_IO_H_ |
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37 | # error "Include <avr/io.h> instead of this file." |
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38 | #endif |
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39 | |
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40 | #ifndef _AVR_IOXXX_H_ |
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41 | # define _AVR_IOXXX_H_ "iotn2313a.h" |
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42 | #else |
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43 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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44 | #endif |
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45 | |
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46 | |
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47 | #ifndef _AVR_ATtiny2313A_H_ |
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48 | #define _AVR_ATtiny2313A_H_ 1 |
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49 | |
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50 | |
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51 | /* Registers and associated bit numbers. */ |
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52 | |
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53 | #define DIDR _SFR_IO8(0x001) |
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54 | #define AIN0D 0 |
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55 | #define AIN1D 1 |
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56 | |
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57 | #define UBRRH _SFR_IO8(0x002) |
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58 | #define UBRR8 0 |
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59 | #define UBRR9 1 |
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60 | #define UBRR10 2 |
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61 | #define UBRR11 3 |
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62 | |
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63 | #define UCSRC _SFR_IO8(0x003) |
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64 | #define UCPOL 0 |
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65 | #define UCSZ0 1 |
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66 | #define UCSZ1 2 |
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67 | #define USBS 3 |
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68 | #define UPM0 4 |
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69 | #define UPM1 5 |
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70 | #define UMSEL 6 |
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71 | |
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72 | #define PCMSK1 _SFR_IO8(0x004) |
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73 | #define PCINT8 0 |
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74 | #define PCINT9 1 |
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75 | #define PCINT10 2 |
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76 | |
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77 | #define PCMSK2 _SFR_IO8(0x005) |
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78 | #define PCINT11 0 |
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79 | #define PCINT12 1 |
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80 | #define PCINT13 2 |
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81 | #define PCINT14 3 |
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82 | #define PCINT15 4 |
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83 | #define PCINT16 5 |
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84 | #define PCINT17 6 |
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85 | |
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86 | #define PRR _SFR_IO8(0x006) |
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87 | #define PRUSART 0 |
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88 | #define PRUSI 1 |
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89 | #define PRTIM0 2 |
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90 | #define PRTIM1 3 |
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91 | |
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92 | #define BODCR _SFR_IO8(0x007) |
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93 | #define BPDSE 0 |
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94 | #define BPDS 1 |
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95 | |
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96 | #define ACSR _SFR_IO8(0x008) |
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97 | #define ACIS0 0 |
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98 | #define ACIS1 1 |
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99 | #define ACIC 2 |
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100 | #define ACIE 3 |
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101 | #define ACI 4 |
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102 | #define ACO 5 |
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103 | #define ACBG 6 |
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104 | #define ACD 7 |
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105 | |
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106 | #define UBRRL _SFR_IO8(0x009) |
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107 | #define UBRR0 0 |
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108 | #define UBRR1 1 |
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109 | #define UBRR2 2 |
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110 | #define UBRR3 3 |
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111 | #define UBRR4 4 |
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112 | #define UBRR5 5 |
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113 | #define UBRR6 6 |
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114 | #define UBRR7 7 |
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115 | |
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116 | #define UCSRB _SFR_IO8(0x00A) |
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117 | #define TXB8 0 |
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118 | #define RXB8 1 |
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119 | #define UCSZ2 2 |
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120 | #define TXEN 3 |
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121 | #define RXEN 4 |
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122 | #define UDRIE 5 |
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123 | #define TXCIE 6 |
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124 | #define RXCIE 7 |
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125 | |
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126 | #define UCSRA _SFR_IO8(0x00B) |
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127 | #define MPCM 0 |
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128 | #define U2X 1 |
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129 | #define UPE 2 |
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130 | #define DOR 3 |
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131 | #define FE 4 |
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132 | #define UDRE 5 |
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133 | #define TXC 6 |
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134 | #define RXC 7 |
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135 | |
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136 | #define UDR _SFR_IO8(0x00C) |
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137 | #define UDR0 0 |
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138 | #define UDR1 1 |
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139 | #define UDR2 2 |
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140 | #define UDR3 3 |
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141 | #define UDR4 4 |
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142 | #define UDR5 5 |
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143 | #define UDR6 6 |
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144 | #define UDR7 7 |
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145 | |
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146 | #define USICR _SFR_IO8(0x00D) |
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147 | #define USITC 0 |
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148 | #define USICLK 1 |
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149 | #define USICS0 2 |
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150 | #define USICS1 3 |
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151 | #define USIWM0 4 |
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152 | #define USIWM1 5 |
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153 | #define USIOIE 6 |
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154 | #define USISIE 7 |
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155 | |
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156 | #define USISR _SFR_IO8(0x00E) |
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157 | #define USICNT0 0 |
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158 | #define USICNT1 1 |
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159 | #define USICNT2 2 |
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160 | #define USICNT3 3 |
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161 | #define USIDC 4 |
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162 | #define USIPF 5 |
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163 | #define USIOIF 6 |
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164 | #define USISIF 7 |
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165 | |
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166 | #define USIDR _SFR_IO8(0x00F) |
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167 | #define USIDR0 0 |
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168 | #define USIDR1 1 |
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169 | #define USIDR2 2 |
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170 | #define USIDR3 3 |
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171 | #define USIDR4 4 |
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172 | #define USIDR5 5 |
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173 | #define USIDR6 6 |
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174 | #define USIDR7 7 |
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175 | |
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176 | #define PIND _SFR_IO8(0x010) |
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177 | #define PIND0 0 |
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178 | #define PIND1 1 |
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179 | #define PIND2 2 |
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180 | #define PIND3 3 |
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181 | #define PIND4 4 |
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182 | #define PIND5 5 |
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183 | #define PIND6 6 |
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184 | |
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185 | #define DDRD _SFR_IO8(0x011) |
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186 | #define DDD0 0 |
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187 | #define DDD1 1 |
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188 | #define DDD2 2 |
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189 | #define DDD3 3 |
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190 | #define DDD4 4 |
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191 | #define DDD5 5 |
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192 | #define DDD6 6 |
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193 | |
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194 | #define PORTD _SFR_IO8(0x012) |
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195 | #define PORTD0 0 |
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196 | #define PORTD1 1 |
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197 | #define PORTD2 2 |
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198 | #define PORTD3 3 |
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199 | #define PORTD4 4 |
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200 | #define PORTD5 5 |
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201 | #define PORTD6 6 |
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202 | |
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203 | #define GPIOR0 _SFR_IO8(0x013) |
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204 | #define GPIOR00 0 |
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205 | #define GPIOR01 1 |
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206 | #define GPIOR02 2 |
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207 | #define GPIOR03 3 |
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208 | #define GPIOR04 4 |
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209 | #define GPIOR05 5 |
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210 | #define GPIOR06 6 |
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211 | #define GPIOR07 7 |
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212 | |
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213 | #define GPIOR1 _SFR_IO8(0x014) |
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214 | #define GPIOR10 0 |
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215 | #define GPIOR11 1 |
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216 | #define GPIOR12 2 |
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217 | #define GPIOR13 3 |
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218 | #define GPIOR14 4 |
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219 | #define GPIOR15 5 |
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220 | #define GPIOR16 6 |
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221 | #define GPIOR17 7 |
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222 | |
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223 | #define GPIOR2 _SFR_IO8(0x015) |
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224 | #define GPIOR20 0 |
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225 | #define GPIOR21 1 |
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226 | #define GPIOR22 2 |
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227 | #define GPIOR23 3 |
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228 | #define GPIOR24 4 |
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229 | #define GPIOR25 5 |
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230 | #define GPIOR26 6 |
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231 | #define GPIOR27 7 |
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232 | |
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233 | #define PINB _SFR_IO8(0x016) |
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234 | #define PINB0 0 |
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235 | #define PINB1 1 |
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236 | #define PINB2 2 |
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237 | #define PINB3 3 |
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238 | #define PINB4 4 |
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239 | #define PINB5 5 |
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240 | #define PINB6 6 |
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241 | #define PINB7 7 |
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242 | |
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243 | #define DDRB _SFR_IO8(0x017) |
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244 | #define DDB0 0 |
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245 | #define DDB1 1 |
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246 | #define DDB2 2 |
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247 | #define DDB3 3 |
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248 | #define DDB4 4 |
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249 | #define DDB5 5 |
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250 | #define DDB6 6 |
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251 | #define DDB7 7 |
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252 | |
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253 | #define PORTB _SFR_IO8(0x018) |
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254 | #define PORTB0 0 |
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255 | #define PORTB1 1 |
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256 | #define PORTB2 2 |
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257 | #define PORTB3 3 |
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258 | #define PORTB4 4 |
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259 | #define PORTB5 5 |
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260 | #define PORTB6 6 |
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261 | #define PORTB7 7 |
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262 | |
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263 | #define PINA _SFR_IO8(0x019) |
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264 | #define PINA0 0 |
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265 | #define PINA1 1 |
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266 | #define PINA2 2 |
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267 | |
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268 | #define DDRA _SFR_IO8(0x01A) |
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269 | #define DDA0 0 |
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270 | #define DDA1 1 |
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271 | #define DDA2 2 |
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272 | |
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273 | #define PORTA _SFR_IO8(0x01B) |
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274 | #define PORTA0 0 |
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275 | #define PORTA1 1 |
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276 | #define PORTA2 2 |
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277 | |
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278 | #define EECR _SFR_IO8(0x01C) |
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279 | #define EERE 0 |
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280 | #define EEPE 1 |
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281 | #define EEMPE 2 |
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282 | #define EERIE 3 |
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283 | #define EEPM0 4 |
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284 | #define EEPM1 5 |
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285 | |
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286 | #define EEDR _SFR_IO8(0x01D) |
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287 | #define EEDR0 0 |
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288 | #define EEDR1 1 |
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289 | #define EEDR2 2 |
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290 | #define EEDR3 3 |
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291 | #define EEDR4 4 |
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292 | #define EEDR5 5 |
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293 | #define EEDR6 6 |
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294 | #define EEDR7 7 |
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295 | |
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296 | #define EEAR _SFR_IO8(0x01E) |
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297 | #define EEAR0 0 |
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298 | #define EEAR1 1 |
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299 | #define EEAR2 2 |
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300 | #define EEAR3 3 |
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301 | #define EEAR4 4 |
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302 | #define EEAR5 5 |
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303 | #define EEAR6 6 |
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304 | |
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305 | #define PCMSK _SFR_IO8(0x020) |
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306 | #define PCINT0 0 |
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307 | #define PCINT1 1 |
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308 | #define PCINT2 2 |
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309 | #define PCINT3 3 |
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310 | #define PCINT4 4 |
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311 | #define PCINT5 5 |
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312 | #define PCINT6 6 |
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313 | #define PCINT7 7 |
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314 | |
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315 | #define WDTCR _SFR_IO8(0x021) |
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316 | #define WDP0 0 |
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317 | #define WDP1 1 |
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318 | #define WDP2 2 |
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319 | #define WDE 3 |
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320 | #define WDCE 4 |
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321 | #define WDP3 5 |
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322 | #define WDIE 6 |
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323 | #define WDIF 7 |
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324 | |
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325 | #define TCCR1C _SFR_IO8(0x022) |
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326 | #define FOC1B 6 |
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327 | #define FOC1A 7 |
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328 | |
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329 | #define GTCCR _SFR_IO8(0x023) |
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330 | #define PSR10 0 |
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331 | |
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332 | #define ICR1 _SFR_IO16(0x024) |
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333 | |
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334 | #define ICR1L _SFR_IO8(0x024) |
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335 | #define ICR1L0 0 |
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336 | #define ICR1L1 1 |
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337 | #define ICR1L2 2 |
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338 | #define ICR1L3 3 |
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339 | #define ICR1L4 4 |
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340 | #define ICR1L5 5 |
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341 | #define ICR1L6 6 |
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342 | #define ICR1L7 7 |
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343 | |
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344 | #define ICR1H _SFR_IO8(0x025) |
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345 | #define ICR1H0 0 |
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346 | #define ICR1H1 1 |
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347 | #define ICR1H2 2 |
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348 | #define ICR1H3 3 |
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349 | #define ICR1H4 4 |
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350 | #define ICR1H5 5 |
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351 | #define ICR1H6 6 |
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352 | #define ICR1H7 7 |
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353 | |
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354 | #define CLKPR _SFR_IO8(0x026) |
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355 | #define CLKPS0 0 |
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356 | #define CLKPS1 1 |
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357 | #define CLKPS2 2 |
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358 | #define CLKPS3 3 |
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359 | #define CLKPCE 7 |
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360 | |
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361 | #define OCR1B _SFR_IO16(0x028) |
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362 | |
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363 | #define OCR1BL _SFR_IO8(0x028) |
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364 | #define OCR1BL0 0 |
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365 | #define OCR1BL1 1 |
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366 | #define OCR1BL2 2 |
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367 | #define OCR1BL3 3 |
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368 | #define OCR1BL4 4 |
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369 | #define OCR1BL5 5 |
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370 | #define OCR1BL6 6 |
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371 | #define OCR1BL7 7 |
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372 | |
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373 | #define OCR1BH _SFR_IO8(0x029) |
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374 | #define OCR1BH0 0 |
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375 | #define OCR1BH1 1 |
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376 | #define OCR1BH2 2 |
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377 | #define OCR1BH3 3 |
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378 | #define OCR1BH4 4 |
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379 | #define OCR1BH5 5 |
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380 | #define OCR1BH6 6 |
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381 | #define OCR1BH7 7 |
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382 | |
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383 | #define OCR1A _SFR_IO16(0x02A) |
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384 | |
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385 | #define OCR1AL _SFR_IO8(0x02A) |
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386 | #define OCR1AL0 0 |
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387 | #define OCR1AL1 1 |
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388 | #define OCR1AL2 2 |
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389 | #define OCR1AL3 3 |
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390 | #define OCR1AL4 4 |
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391 | #define OCR1AL5 5 |
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392 | #define OCR1AL6 6 |
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393 | #define OCR1AL7 7 |
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394 | |
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395 | #define OCR1AH _SFR_IO8(0x02B) |
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396 | #define OCR1AH0 0 |
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397 | #define OCR1AH1 1 |
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398 | #define OCR1AH2 2 |
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399 | #define OCR1AH3 3 |
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400 | #define OCR1AH4 4 |
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401 | #define OCR1AH5 5 |
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402 | #define OCR1AH6 6 |
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403 | #define OCR1AH7 7 |
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404 | |
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405 | #define TCNT1 _SFR_IO16(0x02C) |
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406 | |
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407 | #define TCNT1L _SFR_IO8(0x02C) |
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408 | #define TCNT1L0 0 |
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409 | #define TCNT1L1 1 |
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410 | #define TCNT1L2 2 |
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411 | #define TCNT1L3 3 |
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412 | #define TCNT1L4 4 |
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413 | #define TCNT1L5 5 |
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414 | #define TCNT1L6 6 |
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415 | #define TCNT1L7 7 |
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416 | |
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417 | #define TCNT1H _SFR_IO8(0x02D) |
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418 | #define TCNT1H0 0 |
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419 | #define TCNT1H1 1 |
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420 | #define TCNT1H2 2 |
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421 | #define TCNT1H3 3 |
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422 | #define TCNT1H4 4 |
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423 | #define TCNT1H5 5 |
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424 | #define TCNT1H6 6 |
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425 | #define TCNT1H7 7 |
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426 | |
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427 | #define TCCR1B _SFR_IO8(0x02E) |
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428 | #define CS10 0 |
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429 | #define CS11 1 |
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430 | #define CS12 2 |
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431 | #define WGM12 3 |
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432 | #define WGM13 4 |
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433 | #define ICES1 6 |
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434 | #define ICNC1 7 |
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435 | |
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436 | #define TCCR1A _SFR_IO8(0x02F) |
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437 | #define WGM10 0 |
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438 | #define WGM11 1 |
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439 | #define COM1B0 4 |
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440 | #define COM1B1 5 |
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441 | #define COM1A0 6 |
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442 | #define COM1A1 7 |
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443 | |
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444 | #define TCCR0A _SFR_IO8(0x030) |
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445 | #define WGM00 0 |
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446 | #define WGM01 1 |
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447 | #define COM0B0 4 |
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448 | #define COM0B1 5 |
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449 | #define COM0A0 6 |
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450 | #define COM0A1 7 |
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451 | |
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452 | #define OSCCAL _SFR_IO8(0x031) |
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453 | #define CAL0 0 |
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454 | #define CAL1 1 |
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455 | #define CAL2 2 |
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456 | #define CAL3 3 |
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457 | #define CAL4 4 |
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458 | #define CAL5 5 |
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459 | #define CAL6 6 |
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460 | |
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461 | #define TCNT0 _SFR_IO8(0x032) |
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462 | #define TCNT0_0 0 |
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463 | #define TCNT0_1 1 |
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464 | #define TCNT0_2 2 |
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465 | #define TCNT0_3 3 |
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466 | #define TCNT0_4 4 |
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467 | #define TCNT0_5 5 |
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468 | #define TCNT0_6 6 |
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469 | #define TCNT0_7 7 |
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470 | |
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471 | #define TCCR0B _SFR_IO8(0x033) |
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472 | #define CS00 0 |
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473 | #define CS01 1 |
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474 | #define CS02 2 |
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475 | #define WGM02 3 |
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476 | #define FOC0B 6 |
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477 | #define FOC0A 7 |
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478 | |
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479 | #define MCUSR _SFR_IO8(0x034) |
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480 | #define PORF 0 |
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481 | #define EXTRF 1 |
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482 | #define BORF 2 |
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483 | #define WDRF 3 |
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484 | |
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485 | #define MCUCR _SFR_IO8(0x035) |
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486 | #define ISC00 0 |
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487 | #define ISC01 1 |
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488 | #define ISC10 2 |
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489 | #define ISC11 3 |
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490 | #define SM0 4 |
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491 | #define SE 5 |
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492 | #define SM1 6 |
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493 | #define PUD 7 |
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494 | |
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495 | #define OCR0A _SFR_IO8(0x036) |
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496 | #define OCR0A_0 0 |
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497 | #define OCR0A_1 1 |
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498 | #define OCR0A_2 2 |
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499 | #define OCR0A_3 3 |
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500 | #define OCR0A_4 4 |
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501 | #define OCR0A_5 5 |
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502 | #define OCR0A_6 6 |
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503 | #define OCR0A_7 7 |
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504 | |
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505 | #define SPMCSR _SFR_IO8(0x037) |
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506 | #define SPMEN 0 |
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507 | #define PGERS 1 |
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508 | #define PGWRT 2 |
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509 | #define RFLB 3 |
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510 | #define CTPB 4 |
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511 | |
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512 | #define TIFR _SFR_IO8(0x038) |
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513 | #define OCF0A 0 |
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514 | #define TOV0 1 |
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515 | #define OCF0B 2 |
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516 | #define ICF1 3 |
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517 | #define OCF1B 5 |
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518 | #define OCF1A 6 |
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519 | #define TOV1 7 |
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520 | |
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521 | #define TIMSK _SFR_IO8(0x039) |
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522 | #define OCIE0A 0 |
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523 | #define TOIE0 1 |
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524 | #define OCIE0B 2 |
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525 | #define ICIE1 3 |
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526 | #define OCIE1B 5 |
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527 | #define OCIE1A 6 |
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528 | #define TOIE1 7 |
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529 | |
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530 | #define EIFR _SFR_IO8(0x03A) |
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531 | #define PCIF 5 |
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532 | #define INTF0 6 |
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533 | #define INTF1 7 |
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534 | |
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535 | #define GIMSK _SFR_IO8(0x03B) |
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536 | #define PCIE 5 |
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537 | #define INT0 6 |
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538 | #define INT1 7 |
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539 | |
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540 | #define OCR0B _SFR_IO8(0x03C) |
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541 | #define OCR0_0 0 |
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542 | #define OCR0_1 1 |
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543 | #define OCR0_2 2 |
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544 | #define OCR0_3 3 |
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545 | #define OCR0_4 4 |
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546 | #define OCR0_5 5 |
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547 | #define OCR0_6 6 |
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548 | #define OCR0_7 7 |
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549 | |
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550 | |
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551 | /* Interrupt vectors */ |
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552 | /* Vector 0 is the reset vector */ |
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553 | #define INT0_vect_num 1 |
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554 | #define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ |
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555 | #define INT1_vect_num 2 |
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556 | #define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ |
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557 | #define TIMER1_CAPT_vect_num 3 |
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558 | #define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ |
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559 | #define TIMER1_COMPA_vect_num 4 |
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560 | #define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ |
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561 | #define TIMER1_OVF_vect_num 5 |
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562 | #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ |
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563 | #define TIMER0_OVF_vect_num 6 |
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564 | #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ |
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565 | #define USART_RX_vect_num 7 |
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566 | #define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ |
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567 | #define USART_UDRE_vect_num 8 |
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568 | #define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ |
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569 | #define USART_TX_vect_num 9 |
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570 | #define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ |
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571 | #define ANA_COMP_vect_num 10 |
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572 | #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ |
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573 | #define PCINT_B_vect_num 11 |
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574 | #define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ |
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575 | #define TIMER1_COMPB_vect_num 12 |
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576 | #define TIMER1_COMPB_vect _VECTOR(12) /* */ |
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577 | #define TIMER0_COMPA_vect_num 13 |
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578 | #define TIMER0_COMPA_vect _VECTOR(13) /* */ |
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579 | #define TIMER0_COMPB_vect_num 14 |
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580 | #define TIMER0_COMPB_vect _VECTOR(14) /* */ |
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581 | #define USI_START_vect_num 15 |
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582 | #define USI_START_vect _VECTOR(15) /* USI Start Condition */ |
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583 | #define USI_OVERFLOW_vect_num 16 |
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584 | #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ |
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585 | #define WDT_OVERFLOW_vect_num 18 |
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586 | #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ |
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587 | #define PCINT_D_vect_num 20 |
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588 | #define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ |
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589 | #define EEPROM_Ready_vect_num 17 |
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590 | #define EEPROM_Ready_vect _VECTOR(17) /* */ |
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591 | #define PCINT_A_vect_num 19 |
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592 | #define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ |
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593 | |
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594 | #define _VECTOR_SIZE 2 /* Size of individual vector. */ |
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595 | #define _VECTORS_SIZE (21 * _VECTOR_SIZE) |
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596 | |
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597 | |
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598 | /* Constants */ |
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599 | #define SPM_PAGESIZE (32) |
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600 | #define RAMSTART (0x60) |
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601 | #define RAMSIZE (128) |
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602 | #define RAMEND (RAMSTART + RAMSIZE - 1) |
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603 | #define XRAMSTART (NA) |
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604 | #define XRAMSIZE (0) |
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605 | #define XRAMEND (RAMEND) |
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606 | #define E2END (0x7F) |
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607 | #define E2PAGESIZE (4) |
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608 | #define FLASHEND (0x7FF) |
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609 | |
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610 | |
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611 | /* Fuses */ |
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612 | #define FUSE_MEMORY_SIZE 3 |
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613 | |
---|
614 | /* Low Fuse Byte */ |
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615 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ |
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616 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ |
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617 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ |
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618 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ |
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619 | #define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ |
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620 | #define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ |
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621 | #define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ |
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622 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ |
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623 | #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) |
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624 | |
---|
625 | /* High Fuse Byte */ |
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626 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ |
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627 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ |
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628 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ |
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629 | #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ |
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630 | #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ |
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631 | #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ |
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632 | #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ |
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633 | #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ |
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634 | #define HFUSE_DEFAULT (FUSE_SPIEN) |
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635 | |
---|
636 | /* Extended Fuse Byte */ |
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637 | #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ |
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638 | #define EFUSE_DEFAULT (0xFF) |
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639 | |
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640 | |
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641 | /* Lock Bits */ |
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642 | #define __LOCK_BITS_EXIST |
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643 | |
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644 | |
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645 | /* Signature */ |
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646 | #define SIGNATURE_0 0x1E |
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647 | #define SIGNATURE_1 0x91 |
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648 | #define SIGNATURE_2 0x0A |
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649 | |
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650 | |
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651 | /* Device Pin Definitions */ |
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652 | #define RXD_DDR DDRD |
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653 | #define RXD_PORT PORTD |
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654 | #define RXD_PIN PIND |
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655 | #define RXD_BIT 0 |
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656 | |
---|
657 | #define TXD_DDR DDRD |
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658 | #define TXD_PORT PORTD |
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659 | #define TXD_PIN PIND |
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660 | #define TXD_BIT 1 |
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661 | |
---|
662 | #define PA1_DDR DDRXTAL |
---|
663 | #define PA1_PORT PORTXTAL |
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664 | #define PA1_PIN PINXTAL |
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665 | #define PA1_BIT XTAL2 |
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666 | |
---|
667 | #define PA0_DDR DDRXTAL |
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668 | #define PA0_PORT PORTXTAL |
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669 | #define PA0_PIN PINXTAL |
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670 | #define PA0_BIT XTAL1 |
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671 | |
---|
672 | #define INT0_DDR DDRD |
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673 | #define INT0_PORT PORTD |
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674 | #define INT0_PIN PIND |
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675 | #define INT0_BIT 2 |
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676 | |
---|
677 | #define XCK_DDR DDRD |
---|
678 | #define XCK_PORT PORTD |
---|
679 | #define XCK_PIN PIND |
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680 | #define XCK_BIT 2 |
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681 | |
---|
682 | #define CKOUT_DDR DDRD |
---|
683 | #define CKOUT_PORT PORTD |
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684 | #define CKOUT_PIN PIND |
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685 | #define CKOUT_BIT 2 |
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686 | |
---|
687 | #define INT1_DDR DDRD |
---|
688 | #define INT1_PORT PORTD |
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689 | #define INT1_PIN PIND |
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690 | #define INT1_BIT 3 |
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691 | |
---|
692 | #define T0_DDR DDRD |
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693 | #define T0_PORT PORTD |
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694 | #define T0_PIN PIND |
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695 | #define T0_BIT 4 |
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696 | |
---|
697 | #define T1_DDR DDRD |
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698 | #define T1_PORT PORTD |
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699 | #define T1_PIN PIND |
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700 | #define T1_BIT 5 |
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701 | |
---|
702 | #define OC0B_DDR DDRD |
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703 | #define OC0B_PORT PORTD |
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704 | #define OC0B_PIN PIND |
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705 | #define OC0B_BIT 5 |
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706 | |
---|
707 | #define ICP_DDR DDRD |
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708 | #define ICP_PORT PORTD |
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709 | #define ICP_PIN PIND |
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710 | #define ICP_BIT 6 |
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711 | |
---|
712 | #define AIN0_DDR DDRB |
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713 | #define AIN0_PORT PORTB |
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714 | #define AIN0_PIN PINB |
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715 | #define AIN0_BIT 0 |
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716 | |
---|
717 | #define AIN1_DDR DDRB |
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718 | #define AIN1_PORT PORTB |
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719 | #define AIN1_PIN PINB |
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720 | #define AIN1_BIT 1 |
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721 | |
---|
722 | #define OC0A_DDR DDRB |
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723 | #define OC0A_PORT PORTB |
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724 | #define OC0A_PIN PINB |
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725 | #define OC0A_BIT 2 |
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726 | |
---|
727 | #define OC1A_DDR DDRB |
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728 | #define OC1A_PORT PORTB |
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729 | #define OC1A_PIN PINB |
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730 | #define OC1A_BIT 3 |
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731 | |
---|
732 | #define OC1B_DDR DDRB |
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733 | #define OC1B_PORT PORTB |
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734 | #define OC1B_PIN PINB |
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735 | #define OC1B_BIT 4 |
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736 | |
---|
737 | #define MOSI_DDR DDRB |
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738 | #define MOSI_PORT PORTB |
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739 | #define MOSI_PIN PINB |
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740 | #define MOSI_BIT 5 |
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741 | |
---|
742 | #define DI_DDR DDRB |
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743 | #define DI_PORT PORTB |
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744 | #define DI_PIN PINB |
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745 | #define DI_BIT 5 |
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746 | |
---|
747 | #define MISO_DDR DDRB |
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748 | #define MISO_PORT PORTB |
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749 | #define MISO_PIN PINB |
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750 | #define MISO_BIT 6 |
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751 | |
---|
752 | #define DO_DDR DDRB |
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753 | #define DO_PORT PORTB |
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754 | #define DO_PIN PINB |
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755 | #define DO_BIT 6 |
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756 | |
---|
757 | #define SCK_DDR DDRB |
---|
758 | #define SCK_PORT PORTB |
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759 | #define SCK_PIN PINB |
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760 | #define SCK_BIT 7 |
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761 | |
---|
762 | #define SCL_DDR DDRB |
---|
763 | #define SCL_PORT PORTB |
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764 | #define SCL_PIN PINB |
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765 | #define SCL_BIT 7 |
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766 | |
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767 | #endif /* _AVR_ATtiny2313A_H_ */ |
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768 | |
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