1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief Definitions for ATtiny2313 |
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5 | * |
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6 | * This file should only be included from <avr/io.h>, never directly. |
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7 | */ |
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8 | |
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9 | /* Copyright (c) 2004, 2005, 2006 Bob Paddock |
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10 | All rights reserved. |
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11 | |
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12 | Redistribution and use in source and binary forms, with or without |
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13 | modification, are permitted provided that the following conditions are met: |
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14 | |
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15 | * Redistributions of source code must retain the above copyright |
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16 | notice, this list of conditions and the following disclaimer. |
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17 | |
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18 | * Redistributions in binary form must reproduce the above copyright |
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19 | notice, this list of conditions and the following disclaimer in |
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20 | the documentation and/or other materials provided with the |
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21 | distribution. |
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22 | |
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23 | * Neither the name of the copyright holders nor the names of |
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24 | contributors may be used to endorse or promote products derived |
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25 | from this software without specific prior written permission. |
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26 | |
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27 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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28 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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29 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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30 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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31 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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32 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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33 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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34 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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35 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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36 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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37 | POSSIBILITY OF SUCH DAMAGE. */ |
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38 | |
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39 | |
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40 | /* iotn2313.h derived from io2313.h by Bob Paddock. |
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41 | |
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42 | The changes between the AT90S2313 and the ATtiny2313 are extensive. |
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43 | |
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44 | Atmel has renamed several registers, and bits. See Atmel application note |
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45 | AVR091, as well as the errata at the end of the current ATtiny2313 data |
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46 | sheet. Some of the names have changed more than once during the sampling |
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47 | period of the ATtiny2313. |
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48 | |
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49 | Where there is no conflict the new and old names are both supported. |
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50 | |
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51 | In the case of a new feature in a register, only the new name is used. |
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52 | This intentionally breaks old code, so that there are no silent bugs. The |
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53 | source code must be updated to the new name in this case. |
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54 | |
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55 | The hardware interrupt vector table has changed from that of the AT90S2313. |
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56 | |
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57 | ATtiny2313 programs in page mode rather than the byte mode of the |
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58 | AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, |
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59 | when programming the Flash. |
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60 | |
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61 | ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. |
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62 | |
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63 | Changes and/or additions are noted by "ATtiny" in the comments below. */ |
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64 | |
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65 | /* avr/iotn2313.h - definitions for ATtiny2313 */ |
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66 | |
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67 | #ifndef _AVR_IOTN2313_H_ |
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68 | #define _AVR_IOTN2313_H_ 1 |
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69 | |
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70 | /* This file should only be included from <avr/io.h>, never directly. */ |
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71 | |
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72 | #ifndef _AVR_IO_H_ |
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73 | # error "Include <avr/io.h> instead of this file." |
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74 | #endif |
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75 | |
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76 | #ifndef _AVR_IOXXX_H_ |
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77 | # define _AVR_IOXXX_H_ "iotn2313.h" |
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78 | #else |
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79 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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80 | #endif |
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81 | |
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82 | /** |
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83 | * @defgroup AvrDef_iotn2313 ATtiny2313 Definitions |
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84 | * |
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85 | * @ingroup avr |
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86 | * |
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87 | */ |
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88 | /**@{**/ |
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89 | |
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90 | /* I/O registers */ |
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91 | |
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92 | /* |
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93 | * The Register Bit names are represented by their bit number (0-7). |
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94 | * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. |
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95 | */ |
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96 | |
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97 | /* 0x00 Reserved */ |
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98 | |
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99 | /* ATtiny Digital Input Disable Register DIDR */ |
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100 | #define DIDR _SFR_IO8(0x01) |
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101 | |
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102 | #define AIN1D 1 |
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103 | #define AIN0D 0 |
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104 | |
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105 | /* ATtiny USART Baud Rate Register High UBBRH[11:8] */ |
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106 | #define UBRRH _SFR_IO8(0x02) |
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107 | |
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108 | /* ATtiny USART Control and Status Register C UCSRC */ |
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109 | #define UCSRC _SFR_IO8(0x03) |
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110 | |
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111 | #define UMSEL 6 |
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112 | #define UPM1 5 |
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113 | #define UPM0 4 |
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114 | #define USBS 3 |
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115 | #define UCSZ1 2 |
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116 | #define UCSZ0 1 |
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117 | #define UCPOL 0 |
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118 | |
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119 | /* 0x04 -> 0x07 Reserved */ |
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120 | |
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121 | /* ATtiny Analog Comparator Control and Status Register ACSR */ |
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122 | #define ACSR _SFR_IO8(0x08) |
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123 | |
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124 | #define ACD 7 |
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125 | #define ACBG 6 |
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126 | #define ACO 5 |
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127 | #define ACI 4 |
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128 | #define ACIE 3 |
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129 | #define ACIC 2 |
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130 | #define ACIS1 1 |
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131 | #define ACIS0 0 |
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132 | |
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133 | /* USART Baud Rate Register Low UBBRL[7:0] */ |
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134 | #define UBRRL _SFR_IO8(0x09) |
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135 | |
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136 | /* ATtiny USART Control Register UCSRB */ |
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137 | #define UCSRB _SFR_IO8(0x0A) |
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138 | |
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139 | #define RXCIE 7 |
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140 | #define TXCIE 6 |
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141 | #define UDRIE 5 |
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142 | #define RXEN 4 |
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143 | #define TXEN 3 |
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144 | #define UCSZ2 2 |
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145 | #define RXB8 1 |
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146 | #define TXB8 0 |
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147 | |
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148 | /* ATtiny USART Status Register UCSRA */ |
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149 | #define UCSRA _SFR_IO8(0x0B) |
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150 | |
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151 | #define RXC 7 |
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152 | #define TXC 6 |
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153 | #define UDRE 5 |
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154 | #define FE 4 |
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155 | #define DOR 3 |
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156 | #define UPE 2 |
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157 | #define U2X 1 |
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158 | #define MPCM 0 |
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159 | |
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160 | /* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ |
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161 | #define UDR _SFR_IO8(0x0C) |
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162 | #define RXB _SFR_IO8(0x0C) |
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163 | #define TXB _SFR_IO8(0x0C) |
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164 | |
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165 | /* ATtiny USI Control Register USICR */ |
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166 | #define USICR _SFR_IO8(0x0D) |
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167 | |
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168 | #define USISIE 7 |
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169 | #define USIOIE 6 |
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170 | #define USIWM1 5 |
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171 | #define USIWM0 4 |
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172 | #define USICS1 3 |
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173 | #define USICS0 2 |
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174 | #define USICLK 1 |
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175 | #define USITC 0 |
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176 | |
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177 | /* ATtiny USI Status Register USISR */ |
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178 | #define USISR _SFR_IO8(0x0E) |
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179 | |
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180 | #define USISIF 7 |
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181 | #define USIOIF 6 |
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182 | #define USIPF 5 |
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183 | #define USIDC 4 |
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184 | #define USICNT3 3 |
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185 | #define USICNT2 2 |
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186 | #define USICNT1 1 |
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187 | #define USICNT0 0 |
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188 | |
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189 | /* ATtiny USI Data Register USIDR[7:0] */ |
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190 | #define USIDR _SFR_IO8(0x0F) |
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191 | |
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192 | /* Input Pins, Port D PIND[6:0] */ |
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193 | #define PIND _SFR_IO8(0x10) |
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194 | |
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195 | #define PIND6 6 |
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196 | #define PIND5 5 |
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197 | #define PIND4 4 |
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198 | #define PIND3 3 |
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199 | #define PIND2 2 |
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200 | #define PIND1 1 |
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201 | #define PIND0 0 |
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202 | |
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203 | /* Data Direction Register, Port D DDRD[6:0] */ |
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204 | #define DDRD _SFR_IO8(0x11) |
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205 | |
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206 | #define DDD6 6 |
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207 | #define DDD5 5 |
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208 | #define DDD4 4 |
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209 | #define DDD3 3 |
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210 | #define DDD2 2 |
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211 | #define DDD1 1 |
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212 | #define DDD0 0 |
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213 | |
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214 | /* Data Register, Port D PORTD[6:0] */ |
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215 | #define PORTD _SFR_IO8(0x12) |
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216 | |
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217 | #define PD6 6 |
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218 | #define PD5 5 |
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219 | #define PD4 4 |
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220 | #define PD3 3 |
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221 | #define PD2 2 |
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222 | #define PD1 1 |
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223 | #define PD0 0 |
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224 | |
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225 | /* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ |
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226 | #define GPIOR0 _SFR_IO8(0x13) |
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227 | |
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228 | /* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ |
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229 | #define GPIOR1 _SFR_IO8(0x14) |
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230 | |
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231 | /* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ |
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232 | #define GPIOR2 _SFR_IO8(0x15) |
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233 | |
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234 | /* Input Pins, Port B PORTB[7:0] */ |
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235 | #define PINB _SFR_IO8(0x16) |
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236 | |
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237 | #define PINB7 7 |
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238 | #define PINB6 6 |
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239 | #define PINB5 5 |
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240 | #define PINB4 4 |
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241 | #define PINB3 3 |
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242 | #define PINB2 2 |
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243 | #define PINB1 1 |
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244 | #define PINB0 0 |
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245 | |
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246 | /* Data Direction Register, Port B PORTB[7:0] */ |
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247 | #define DDRB _SFR_IO8(0x17) |
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248 | |
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249 | #define DDB7 7 |
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250 | #define DDB6 6 |
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251 | #define DDB5 5 |
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252 | #define DDB4 4 |
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253 | #define DDB3 3 |
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254 | #define DDB2 2 |
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255 | #define DDB1 1 |
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256 | #define DDB0 0 |
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257 | |
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258 | /* Data Register, Port B PORTB[7:0] */ |
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259 | #define PORTB _SFR_IO8(0x18) |
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260 | |
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261 | #define PB7 7 |
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262 | #define PB6 6 |
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263 | #define PB5 5 |
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264 | #define PB4 4 |
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265 | #define PB3 3 |
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266 | #define PB2 2 |
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267 | #define PB1 1 |
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268 | #define PB0 0 |
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269 | |
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270 | /* Port A Input Pins Address PINA[2:0] */ |
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271 | #define PINA _SFR_IO8(0x19) |
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272 | |
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273 | #define PINA2 2 |
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274 | #define PINA1 1 |
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275 | #define PINA0 0 |
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276 | |
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277 | /* Port A Data Direction Register DDRA[2:0] */ |
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278 | #define DDRA _SFR_IO8(0x1A) |
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279 | |
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280 | #define DDRA2 2 |
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281 | #define DDRA1 1 |
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282 | #define DDRA0 0 |
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283 | |
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284 | /* Port A Data Register PORTA[2:0] */ |
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285 | #define PORTA _SFR_IO8(0x1B) |
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286 | |
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287 | #define PA2 2 |
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288 | #define PA1 1 |
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289 | #define PA0 0 |
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290 | |
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291 | /* ATtiny EEPROM Control Register EECR */ |
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292 | #define EECR _SFR_IO8(0x1C) |
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293 | #define EEPM1 5 |
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294 | #define EEPM0 4 |
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295 | #define EERIE 3 |
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296 | #define EEMPE 2 |
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297 | #define EEPE 1 |
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298 | #define EERE 0 |
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299 | |
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300 | /* EEPROM Data Register */ |
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301 | #define EEDR _SFR_IO8(0x1D) |
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302 | |
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303 | /* The EEPROM Address Register EEAR[6:0] */ |
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304 | #define EEAR _SFR_IO8(0x1E) |
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305 | #define EEARL _SFR_IO8(0x1E) |
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306 | #define EEAR6 6 |
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307 | #define EEAR5 5 |
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308 | #define EEAR4 4 |
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309 | #define EEAR3 3 |
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310 | #define EEAR2 2 |
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311 | #define EEAR1 1 |
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312 | #define EEAR0 0 |
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313 | |
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314 | /* 0x1F Reserved */ |
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315 | |
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316 | /* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ |
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317 | #define PCMSK _SFR_IO8(0x20) |
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318 | |
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319 | #define PCINT7 7 |
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320 | #define PCINT6 6 |
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321 | #define PCINT5 5 |
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322 | #define PCINT4 4 |
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323 | #define PCINT3 3 |
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324 | #define PCINT2 2 |
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325 | #define PCINT1 1 |
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326 | #define PCINT0 0 |
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327 | |
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328 | /* ATtiny Watchdog Timer Control Register WDTCSR */ |
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329 | #define WDTCSR _SFR_IO8(0x21) |
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330 | |
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331 | #define WDIF 7 |
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332 | #define WDIE 6 |
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333 | #define WDP3 5 |
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334 | #define WDCE 4 |
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335 | #define WDE 3 |
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336 | #define WDP2 2 |
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337 | #define WDP1 1 |
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338 | #define WDP0 0 |
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339 | |
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340 | /* ATtiny Timer/Counter1 Control Register C TCCR1C */ |
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341 | #define TCCR1C _SFR_IO8(0x22) |
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342 | |
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343 | #define FOC1A 7 |
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344 | #define FOC1B 6 |
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345 | |
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346 | /* General Timer/Counter Control Register GTCCR */ |
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347 | #define GTCCR _SFR_IO8(0x23) |
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348 | |
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349 | #define PSR10 0 |
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350 | |
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351 | /* T/C 1 Input Capture Register ICR1[15:0] */ |
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352 | #define ICR1 _SFR_IO16(0x24) |
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353 | #define ICR1L _SFR_IO8(0x24) |
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354 | #define ICR1H _SFR_IO8(0x25) |
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355 | |
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356 | /* ATtiny Clock Prescale Register */ |
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357 | #define CLKPR _SFR_IO8(0x26) |
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358 | |
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359 | #define CLKPCE 7 |
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360 | #define CLKPS3 3 |
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361 | #define CLKPS2 2 |
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362 | #define CLKPS1 1 |
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363 | #define CLKPS0 0 |
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364 | |
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365 | /* 0x27 Reserved */ |
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366 | |
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367 | /* ATtiny Output Compare Register 1 B OCR1B[15:0] */ |
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368 | #define OCR1B _SFR_IO16(0x28) |
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369 | #define OCR1BL _SFR_IO8(0x28) |
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370 | #define OCR1BH _SFR_IO8(0x29) |
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371 | |
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372 | /* Output Compare Register 1 OCR1A[15:0] */ |
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373 | #define OCR1 _SFR_IO16(0x2A) |
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374 | #define OCR1L _SFR_IO8(0x2A) |
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375 | #define OCR1H _SFR_IO8(0x2B) |
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376 | #define OCR1A _SFR_IO16(0x2A) |
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377 | #define OCR1AL _SFR_IO8(0x2A) |
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378 | #define OCR1AH _SFR_IO8(0x2B) |
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379 | |
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380 | /* Timer/Counter 1 TCNT1[15:0] */ |
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381 | #define TCNT1 _SFR_IO16(0x2C) |
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382 | #define TCNT1L _SFR_IO8(0x2C) |
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383 | #define TCNT1H _SFR_IO8(0x2D) |
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384 | |
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385 | /* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ |
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386 | #define TCCR1B _SFR_IO8(0x2E) |
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387 | |
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388 | #define ICNC1 7 |
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389 | #define ICES1 6 |
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390 | #define WGM13 4 |
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391 | #define WGM12 3 /* Was CTC1 in AT90S2313 */ |
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392 | #define CS12 2 |
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393 | #define CS11 1 |
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394 | #define CS10 0 |
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395 | |
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396 | /* ATtiny Timer/Counter 1 Control Register TCCR1A */ |
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397 | #define TCCR1A _SFR_IO8(0x2F) |
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398 | |
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399 | #define COM1A1 7 |
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400 | #define COM1A0 6 |
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401 | #define COM1B1 5 |
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402 | #define COM1B0 4 |
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403 | #define WGM11 1 /* Was PWM11 in AT90S2313 */ |
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404 | #define WGM10 0 /* Was PWM10 in AT90S2313 */ |
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405 | |
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406 | /* ATtiny Timer/Counter Control Register A TCCR0A */ |
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407 | #define TCCR0A _SFR_IO8(0x30) |
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408 | |
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409 | #define COM0A1 7 |
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410 | #define COM0A0 6 |
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411 | #define COM0B1 5 |
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412 | #define COM0B0 4 |
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413 | #define WGM01 1 |
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414 | #define WGM00 0 |
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415 | |
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416 | /* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ |
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417 | #define OSCCAL _SFR_IO8(0x31) |
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418 | |
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419 | #define CAL6 6 |
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420 | #define CAL5 5 |
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421 | #define CAL4 4 |
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422 | #define CAL3 3 |
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423 | #define CAL2 2 |
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424 | #define CAL1 1 |
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425 | #define CAL0 0 |
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426 | |
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427 | /* Timer/Counter 0 TCNT0[7:0] */ |
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428 | #define TCNT0 _SFR_IO8(0x32) |
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429 | |
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430 | /* ATtiny Timer/Counter 0 Control Register TCCR0B */ |
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431 | #define TCCR0B _SFR_IO8(0x33) |
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432 | |
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433 | #define FOC0A 7 |
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434 | #define FOC0B 6 |
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435 | #define WGM02 3 |
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436 | #define CS02 2 |
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437 | #define CS01 1 |
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438 | #define CS00 0 |
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439 | |
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440 | /* ATtiny MCU Status Register MCUSR */ |
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441 | #define MCUSR _SFR_IO8(0x34) |
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442 | |
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443 | #define WDRF 3 |
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444 | #define BORF 2 |
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445 | #define EXTRF 1 |
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446 | #define PORF 0 |
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447 | |
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448 | /* ATtiny MCU general Control Register MCUCR */ |
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449 | #define MCUCR _SFR_IO8(0x35) |
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450 | |
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451 | #define PUD 7 |
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452 | #define SM1 6 |
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453 | #define SE 5 |
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454 | #define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer |
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455 | to this bit as SMD; was SM in AT90S2313. */ |
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456 | #define ISC11 3 |
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457 | #define ISC10 2 |
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458 | #define ISC01 1 |
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459 | #define ISC00 0 |
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460 | |
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461 | /* ATtiny Output Compare Register A OCR0A[7:0] */ |
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462 | #define OCR0A _SFR_IO8(0x36) |
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463 | |
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464 | /* ATtiny Store Program Memory Control and Status Register SPMCSR */ |
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465 | #define SPMCSR _SFR_IO8(0x37) |
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466 | |
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467 | #define CTPB 4 |
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468 | #define RFLB 3 |
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469 | #define PGWRT 2 |
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470 | #define PGERS 1 |
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471 | #define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ |
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472 | #define SELFPRGEN 0 /* The name is used in datasheet. */ |
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473 | #define SELFPRGE 0 /* The name is left for compatibility. */ |
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474 | |
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475 | /* ATtiny Timer/Counter Interrupt Flag register TIFR */ |
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476 | #define TIFR _SFR_IO8(0x38) |
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477 | |
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478 | #define TOV1 7 |
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479 | #define OCF1A 6 |
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480 | #define OCF1B 5 |
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481 | #define ICF1 3 |
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482 | #define OCF0B 2 |
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483 | #define TOV0 1 |
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484 | #define OCF0A 0 |
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485 | |
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486 | /* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ |
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487 | #define TIMSK _SFR_IO8(0x39) |
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488 | |
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489 | #define TOIE1 7 |
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490 | #define OCIE1A 6 |
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491 | #define OCIE1B 5 |
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492 | #define ICIE1 3 |
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493 | #define OCIE0B 2 |
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494 | #define TOIE0 1 |
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495 | #define OCIE0A 0 |
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496 | |
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497 | /* ATtiny External Interrupt Flag Register EIFR, was GIFR */ |
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498 | #define EIFR _SFR_IO8(0x3A) |
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499 | |
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500 | #define INTF1 7 |
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501 | #define INTF0 6 |
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502 | #define PCIF 5 |
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503 | |
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504 | /* ATtiny General Interrupt MaSK register GIMSK */ |
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505 | #define GIMSK _SFR_IO8(0x3B) |
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506 | |
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507 | #define INT1 7 |
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508 | #define INT0 6 |
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509 | #define PCIE 5 |
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510 | |
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511 | /* ATtiny Output Compare Register B OCR0B[7:0] */ |
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512 | #define OCR0B _SFR_IO8(0x3C) |
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513 | |
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514 | /* Interrupt vectors: */ |
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515 | |
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516 | /* External Interrupt Request 0 */ |
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517 | #define INT0_vect _VECTOR(1) |
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518 | #define SIG_INTERRUPT0 _VECTOR(1) |
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519 | #define SIG_INT0 _VECTOR(1) |
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520 | |
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521 | /* External Interrupt Request 1 */ |
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522 | #define INT1_vect _VECTOR(2) |
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523 | #define SIG_INTERRUPT1 _VECTOR(2) |
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524 | #define SIG_INT1 _VECTOR(2) |
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525 | |
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526 | /* Timer/Counter1 Capture Event */ |
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527 | #define TIMER1_CAPT_vect _VECTOR(3) |
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528 | #define SIG_INPUT_CAPTURE1 _VECTOR(3) |
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529 | #define SIG_TIMER1_CAPT _VECTOR(3) |
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530 | |
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531 | /* Timer/Counter1 Compare Match A */ |
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532 | #define TIMER1_COMPA_vect _VECTOR(4) |
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533 | #define SIG_OUTPUT_COMPARE1A _VECTOR(4) |
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534 | #define SIG_TIMER1_COMPA _VECTOR(4) |
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535 | |
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536 | /* Timer/Counter1 Overflow */ |
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537 | #define TIMER1_OVF_vect _VECTOR(5) |
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538 | #define SIG_OVERFLOW1 _VECTOR(5) |
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539 | #define SIG_TIMER1_OVF _VECTOR(5) |
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540 | |
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541 | /* Timer/Counter0 Overflow */ |
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542 | #define TIMER0_OVF_vect _VECTOR(6) |
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543 | #define SIG_OVERFLOW0 _VECTOR(6) |
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544 | #define SIG_TIMER0_OVF _VECTOR(6) |
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545 | |
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546 | /* USART, Rx Complete */ |
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547 | #define USART_RX_vect _VECTOR(7) |
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548 | #define SIG_USART0_RECV _VECTOR(7) |
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549 | #define SIG_USART0_RX _VECTOR(7) |
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550 | |
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551 | /* USART Data Register Empty */ |
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552 | #define USART_UDRE_vect _VECTOR(8) |
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553 | #define SIG_USART0_DATA _VECTOR(8) |
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554 | #define SIG_USART0_UDRE _VECTOR(8) |
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555 | |
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556 | /* USART, Tx Complete */ |
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557 | #define USART_TX_vect _VECTOR(9) |
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558 | #define SIG_USART0_TRANS _VECTOR(9) |
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559 | #define SIG_USART0_TX _VECTOR(9) |
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560 | |
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561 | /* Analog Comparator */ |
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562 | #define ANA_COMP_vect _VECTOR(10) |
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563 | #define SIG_COMPARATOR _VECTOR(10) |
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564 | #define SIG_ANALOG_COMP _VECTOR(10) |
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565 | #define PCINT_vect _VECTOR(11) |
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566 | #define SIG_PIN_CHANGE _VECTOR(11) |
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567 | #define SIG_PCINT _VECTOR(11) |
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568 | #define TIMER1_COMPB_vect _VECTOR(12) |
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569 | #define SIG_OUTPUT_COMPARE1B _VECTOR(12) |
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570 | #define SIG_TIMER1_COMPB _VECTOR(12) |
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571 | #define TIMER0_COMPA_vect _VECTOR(13) |
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572 | #define SIG_OUTPUT_COMPARE0A _VECTOR(13) |
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573 | #define SIG_TIMER0_COMPA _VECTOR(13) |
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574 | #define TIMER0_COMPB_vect _VECTOR(14) |
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575 | #define SIG_OUTPUT_COMPARE0B _VECTOR(14) |
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576 | #define SIG_TIMER0_COMPB _VECTOR(14) |
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577 | |
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578 | /* USI Start Condition */ |
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579 | #define USI_START_vect _VECTOR(15) |
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580 | #define SIG_USI_START _VECTOR(15) |
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581 | #define SIG_USI_START _VECTOR(15) |
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582 | |
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583 | /* USI Overflow */ |
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584 | #define USI_OVERFLOW_vect _VECTOR(16) |
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585 | #define SIG_USI_OVERFLOW _VECTOR(16) |
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586 | #define SIG_USI_OVERFLOW _VECTOR(16) |
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587 | #define EEPROM_READY_vect _VECTOR(17) |
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588 | #define SIG_EEPROM_READY _VECTOR(17) |
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589 | #define SIG_EE_READY _VECTOR(17) |
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590 | |
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591 | /* Watchdog Timer Overflow */ |
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592 | #define WDT_OVERFLOW_vect _VECTOR(18) |
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593 | #define SIG_WATCHDOG_TIMEOUT _VECTOR(18) |
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594 | #define SIG_WDT_OVERFLOW _VECTOR(18) |
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595 | |
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596 | /* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ |
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597 | #define _VECTORS_SIZE 38 |
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598 | |
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599 | /* Constants */ |
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600 | #define SPM_PAGESIZE 32 |
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601 | #define RAMEND 0xDF |
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602 | #define XRAMEND RAMEND |
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603 | #define E2END 0x7F |
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604 | #define E2PAGESIZE 4 |
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605 | #define FLASHEND 0x07FF |
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606 | |
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607 | |
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608 | /* Fuses */ |
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609 | #define FUSE_MEMORY_SIZE 3 |
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610 | |
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611 | /* Low Fuse Byte */ |
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612 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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613 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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614 | #define FUSE_CKSEL2 (unsigned char)~_BV(2) |
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615 | #define FUSE_CKSEL3 (unsigned char)~_BV(3) |
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616 | #define FUSE_SUT0 (unsigned char)~_BV(4) |
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617 | #define FUSE_SUT1 (unsigned char)~_BV(5) |
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618 | #define FUSE_CKOUT (unsigned char)~_BV(6) |
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619 | #define FUSE_CKDIV8 (unsigned char)~_BV(7) |
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620 | #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) |
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621 | |
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622 | /* High Fuse Byte */ |
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623 | #define FUSE_RSTDISBL (unsigned char)~_BV(0) |
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624 | #define FUSE_BODLEVEL0 (unsigned char)~_BV(1) |
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625 | #define FUSE_BODLEVEL1 (unsigned char)~_BV(2) |
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626 | #define FUSE_BODLEVEL2 (unsigned char)~_BV(3) |
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627 | #define FUSE_WDTON (unsigned char)~_BV(4) |
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628 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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629 | #define FUSE_EESAVE (unsigned char)~_BV(6) |
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630 | #define FUSE_DWEN (unsigned char)~_BV(7) |
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631 | #define HFUSE_DEFAULT (FUSE_SPIEN) |
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632 | |
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633 | /* Extended Fuse Byte */ |
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634 | #define FUSE_SELFPRGEN (unsigned char)~_BV(0) |
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635 | #define EFUSE_DEFAULT (0xFF) |
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636 | |
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637 | |
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638 | /* Lock Bits */ |
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639 | #define __LOCK_BITS_EXIST |
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640 | |
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641 | |
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642 | /* Signature */ |
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643 | #define SIGNATURE_0 0x1E |
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644 | #define SIGNATURE_1 0x91 |
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645 | #define SIGNATURE_2 0x0A |
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646 | |
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647 | /** @} */ |
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648 | |
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649 | #endif /* _AVR_IOTN2313_H_ */ |
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