source: rtems/cpukit/score/cpu/avr/avr/iotn2313.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 15.5 KB
Line 
1/* Copyright (c) 2004, 2005, 2006 Bob Paddock
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* iotn2313.h derived from io2313.h by Bob Paddock.
34
35   The changes between the AT90S2313 and the ATtiny2313 are extensive.
36
37   Atmel has renamed several registers, and bits.  See Atmel application note
38   AVR091, as well as the errata at the end of the current ATtiny2313 data
39   sheet.  Some of the names have changed more than once during the sampling
40   period of the ATtiny2313.
41
42   Where there is no conflict the new and old names are both supported.
43
44   In the case of a new feature in a register, only the new name is used.
45   This intentionally breaks old code, so that there are no silent bugs.  The
46   source code must be updated to the new name in this case.
47
48   The hardware interrupt vector table has changed from that of the AT90S2313.
49
50   ATtiny2313 programs in page mode rather than the byte mode of the
51   AT90S2313.  Beware of programming the ATtiny2313 as a AT90S2313 device,
52   when programming the Flash.
53
54   ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A.
55
56   Changes and/or additions are noted by "ATtiny" in the comments below. */
57
58/* avr/iotn2313.h - definitions for ATtiny2313 */
59
60#ifndef _AVR_IOTN2313_H_
61#define _AVR_IOTN2313_H_ 1
62
63/* This file should only be included from <avr/io.h>, never directly. */
64
65#ifndef _AVR_IO_H_
66#  error "Include <avr/io.h> instead of this file."
67#endif
68
69#ifndef _AVR_IOXXX_H_
70#  define _AVR_IOXXX_H_ "iotn2313.h"
71#else
72#  error "Attempt to include more than one <avr/ioXXX.h> file."
73#endif
74
75/* I/O registers */
76
77/*
78 *  The Register Bit names are represented by their bit number (0-7).
79 *  Example: PORTB |= _BV(PORTB7); Set MSB of PORTB.
80 */
81
82/* 0x00 Reserved */
83
84/* ATtiny Digital Input Disable Register DIDR */
85#define DIDR    _SFR_IO8(0x01)
86
87#define AIN1D   1
88#define AIN0D   0
89
90/* ATtiny USART Baud Rate Register High UBBRH[11:8] */
91#define UBRRH   _SFR_IO8(0x02)
92
93/* ATtiny USART Control and Status Register C UCSRC */
94#define UCSRC   _SFR_IO8(0x03)
95
96#define UMSEL   6
97#define UPM1    5
98#define UPM0    4
99#define USBS    3
100#define UCSZ1   2
101#define UCSZ0   1
102#define UCPOL   0
103
104/* 0x04 -> 0x07 Reserved */
105
106/* ATtiny Analog Comparator Control and Status Register ACSR */
107#define ACSR    _SFR_IO8(0x08)
108
109#define ACD     7
110#define ACBG    6
111#define ACO     5
112#define ACI     4
113#define ACIE    3
114#define ACIC    2
115#define ACIS1   1
116#define ACIS0   0
117
118/* USART Baud Rate Register Low UBBRL[7:0] */
119#define UBRRL   _SFR_IO8(0x09)
120
121/* ATtiny USART Control Register UCSRB */
122#define UCSRB   _SFR_IO8(0x0A)
123
124#define RXCIE   7
125#define TXCIE   6
126#define UDRIE   5
127#define RXEN    4
128#define TXEN    3
129#define UCSZ2   2
130#define RXB8    1
131#define TXB8    0
132
133/* ATtiny USART Status Register UCSRA */
134#define UCSRA   _SFR_IO8(0x0B)
135
136#define RXC     7
137#define TXC     6
138#define UDRE    5
139#define FE      4
140#define DOR     3
141#define UPE     2
142#define U2X     1
143#define MPCM    0
144
145/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */
146#define UDR     _SFR_IO8(0x0C)
147#define RXB     _SFR_IO8(0x0C)
148#define TXB     _SFR_IO8(0x0C)
149
150/* ATtiny USI Control Register USICR */
151#define USICR   _SFR_IO8(0x0D)
152
153#define USISIE  7
154#define USIOIE  6
155#define USIWM1  5
156#define USIWM0  4
157#define USICS1  3
158#define USICS0  2
159#define USICLK  1
160#define USITC   0
161
162/* ATtiny USI Status Register USISR */
163#define USISR   _SFR_IO8(0x0E)
164
165#define USISIF  7
166#define USIOIF  6
167#define USIPF   5
168#define USIDC   4
169#define USICNT3 3
170#define USICNT2 2
171#define USICNT1 1
172#define USICNT0 0
173
174/* ATtiny USI Data Register USIDR[7:0] */
175#define USIDR   _SFR_IO8(0x0F)
176
177/* Input Pins, Port D PIND[6:0] */
178#define PIND    _SFR_IO8(0x10)
179
180#define PIND6   6
181#define PIND5   5
182#define PIND4   4
183#define PIND3   3
184#define PIND2   2
185#define PIND1   1
186#define PIND0   0
187
188/* Data Direction Register, Port D DDRD[6:0] */
189#define DDRD    _SFR_IO8(0x11)
190
191#define DDD6    6
192#define DDD5    5
193#define DDD4    4
194#define DDD3    3
195#define DDD2    2
196#define DDD1    1
197#define DDD0    0
198
199/* Data Register, Port D PORTD[6:0] */
200#define PORTD   _SFR_IO8(0x12)
201
202#define PD6     6
203#define PD5     5
204#define PD4     4
205#define PD3     3
206#define PD2     2
207#define PD1     1
208#define PD0     0
209
210/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */
211#define GPIOR0  _SFR_IO8(0x13)
212
213/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */
214#define GPIOR1  _SFR_IO8(0x14)
215
216/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */
217#define GPIOR2  _SFR_IO8(0x15)
218
219/* Input Pins, Port B PORTB[7:0] */
220#define PINB    _SFR_IO8(0x16)
221
222#define PINB7   7
223#define PINB6   6
224#define PINB5   5
225#define PINB4   4
226#define PINB3   3
227#define PINB2   2
228#define PINB1   1
229#define PINB0   0
230
231/* Data Direction Register, Port B PORTB[7:0] */
232#define DDRB    _SFR_IO8(0x17)
233
234#define DDB7    7
235#define DDB6    6
236#define DDB5    5
237#define DDB4    4
238#define DDB3    3
239#define DDB2    2
240#define DDB1    1
241#define DDB0    0
242
243/* Data Register, Port B PORTB[7:0] */
244#define PORTB   _SFR_IO8(0x18)
245
246#define PB7     7
247#define PB6     6
248#define PB5     5
249#define PB4     4
250#define PB3     3
251#define PB2     2
252#define PB1     1
253#define PB0     0
254
255/* Port A Input Pins Address PINA[2:0] */
256#define PINA    _SFR_IO8(0x19)
257
258#define PINA2   2
259#define PINA1   1
260#define PINA0   0
261
262/* Port A Data Direction Register DDRA[2:0] */
263#define DDRA    _SFR_IO8(0x1A)
264
265#define DDRA2   2
266#define DDRA1   1
267#define DDRA0   0
268
269/* Port A Data Register PORTA[2:0] */
270#define PORTA   _SFR_IO8(0x1B)
271
272#define PA2     2
273#define PA1     1
274#define PA0     0
275
276/* ATtiny EEPROM Control Register EECR */
277#define EECR    _SFR_IO8(0x1C)
278#define EEPM1   5
279#define EEPM0   4
280#define EERIE   3
281#define EEMPE   2
282#define EEPE    1
283#define EERE    0
284
285/* EEPROM Data Register */
286#define EEDR    _SFR_IO8(0x1D)
287
288/* The EEPROM Address Register EEAR[6:0] */
289#define EEAR    _SFR_IO8(0x1E)
290#define EEARL   _SFR_IO8(0x1E)
291#define EEAR6   6
292#define EEAR5   5
293#define EEAR4   4
294#define EEAR3   3
295#define EEAR2   2
296#define EEAR1   1
297#define EEAR0   0
298
299/* 0x1F Reserved */
300
301/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */
302#define PCMSK   _SFR_IO8(0x20)
303
304#define PCINT7  7
305#define PCINT6  6
306#define PCINT5  5
307#define PCINT4  4
308#define PCINT3  3
309#define PCINT2  2
310#define PCINT1  1
311#define PCINT0  0
312
313/* ATtiny Watchdog Timer Control Register WDTCSR */
314#define WDTCSR  _SFR_IO8(0x21)
315
316#define WDIF    7
317#define WDIE    6
318#define WDP3    5
319#define WDCE    4
320#define WDE     3
321#define WDP2    2
322#define WDP1    1
323#define WDP0    0
324
325/* ATtiny Timer/Counter1 Control Register C TCCR1C */
326#define TCCR1C  _SFR_IO8(0x22)
327
328#define FOC1A   7
329#define FOC1B   6
330
331/* General Timer/Counter Control Register GTCCR */
332#define GTCCR   _SFR_IO8(0x23)
333
334#define PSR10   0
335
336/* T/C 1 Input Capture Register ICR1[15:0] */
337#define ICR1    _SFR_IO16(0x24)
338#define ICR1L   _SFR_IO8(0x24)
339#define ICR1H   _SFR_IO8(0x25)
340
341/* ATtiny Clock Prescale Register */
342#define CLKPR   _SFR_IO8(0x26)
343
344#define CLKPCE  7
345#define CLKPS3  3
346#define CLKPS2  2
347#define CLKPS1  1
348#define CLKPS0  0
349
350/* 0x27 Reserved */
351
352/* ATtiny Output Compare Register 1 B OCR1B[15:0] */
353#define OCR1B   _SFR_IO16(0x28)
354#define OCR1BL  _SFR_IO8(0x28)
355#define OCR1BH  _SFR_IO8(0x29)
356
357/* Output Compare Register 1 OCR1A[15:0] */
358#define OCR1    _SFR_IO16(0x2A)
359#define OCR1L   _SFR_IO8(0x2A)
360#define OCR1H   _SFR_IO8(0x2B)
361#define OCR1A   _SFR_IO16(0x2A)
362#define OCR1AL  _SFR_IO8(0x2A)
363#define OCR1AH  _SFR_IO8(0x2B)
364
365/* Timer/Counter 1 TCNT1[15:0] */
366#define TCNT1   _SFR_IO16(0x2C)
367#define TCNT1L  _SFR_IO8(0x2C)
368#define TCNT1H  _SFR_IO8(0x2D)
369
370/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */
371#define TCCR1B  _SFR_IO8(0x2E)
372
373#define ICNC1   7
374#define ICES1   6
375#define WGM13   4
376#define WGM12   3 /* Was CTC1 in AT90S2313 */
377#define CS12    2
378#define CS11    1
379#define CS10    0
380
381/* ATtiny Timer/Counter 1 Control Register TCCR1A */
382#define TCCR1A  _SFR_IO8(0x2F)
383
384#define COM1A1  7
385#define COM1A0  6
386#define COM1B1  5
387#define COM1B0  4
388#define WGM11   1 /* Was PWM11 in AT90S2313 */
389#define WGM10   0 /* Was PWM10 in AT90S2313 */
390
391/* ATtiny Timer/Counter Control Register A TCCR0A */
392#define TCCR0A  _SFR_IO8(0x30)
393
394#define COM0A1  7
395#define COM0A0  6
396#define COM0B1  5
397#define COM0B0  4
398#define WGM01   1
399#define WGM00   0
400
401/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */
402#define OSCCAL  _SFR_IO8(0x31)
403
404#define CAL6    6
405#define CAL5    5
406#define CAL4    4
407#define CAL3    3
408#define CAL2    2
409#define CAL1    1
410#define CAL0    0
411
412/* Timer/Counter 0 TCNT0[7:0] */
413#define TCNT0   _SFR_IO8(0x32)
414
415/* ATtiny Timer/Counter 0 Control Register TCCR0B */
416#define TCCR0B  _SFR_IO8(0x33)
417
418#define FOC0A   7
419#define FOC0B   6
420#define WGM02   3
421#define CS02    2
422#define CS01    1
423#define CS00    0
424
425/* ATtiny MCU Status Register MCUSR */
426#define MCUSR   _SFR_IO8(0x34)
427
428#define WDRF    3
429#define BORF    2
430#define EXTRF   1
431#define PORF    0
432
433/* ATtiny MCU general Control Register MCUCR */
434#define MCUCR   _SFR_IO8(0x35)
435
436#define PUD     7
437#define SM1     6
438#define SE      5
439#define SM0     4 /* Some preliminary ATtiny2313 data sheets incorrectly refer
440                     to this bit as SMD; was SM in AT90S2313. */
441#define ISC11   3
442#define ISC10   2
443#define ISC01   1
444#define ISC00   0
445
446/* ATtiny Output Compare Register A OCR0A[7:0] */
447#define OCR0A   _SFR_IO8(0x36)
448
449/* ATtiny Store Program Memory Control and Status Register SPMCSR */
450#define SPMCSR  _SFR_IO8(0x37)
451
452#define CTPB    4
453#define RFLB    3
454#define PGWRT   2
455#define PGERS   1
456#define SPMEN   0   /* The name is used in ATtiny2313.xml file. */
457#define SELFPRGEN 0 /* The name is used in datasheet. */
458#define SELFPRGE  0 /* The name is left for compatibility. */
459
460/* ATtiny Timer/Counter Interrupt Flag register TIFR */
461#define TIFR    _SFR_IO8(0x38)
462
463#define TOV1    7
464#define OCF1A   6
465#define OCF1B   5
466#define ICF1    3
467#define OCF0B   2
468#define TOV0    1
469#define OCF0A   0
470
471/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */
472#define TIMSK   _SFR_IO8(0x39)
473
474#define TOIE1   7
475#define OCIE1A  6
476#define OCIE1B  5
477#define ICIE1   3
478#define OCIE0B  2
479#define TOIE0   1
480#define OCIE0A  0
481
482/* ATtiny External Interrupt Flag Register EIFR, was GIFR */
483#define EIFR    _SFR_IO8(0x3A)
484
485#define INTF1   7
486#define INTF0   6
487#define PCIF    5
488
489/* ATtiny General Interrupt MaSK register GIMSK */
490#define GIMSK   _SFR_IO8(0x3B)
491
492#define INT1    7
493#define INT0    6
494#define PCIE    5
495
496/* ATtiny Output Compare Register B OCR0B[7:0] */
497#define OCR0B   _SFR_IO8(0x3C)
498
499/* Interrupt vectors: */
500
501/* External Interrupt Request 0 */
502#define INT0_vect                       _VECTOR(1)
503#define SIG_INTERRUPT0                  _VECTOR(1)
504#define SIG_INT0                        _VECTOR(1)
505
506/* External Interrupt Request 1 */
507#define INT1_vect                       _VECTOR(2)
508#define SIG_INTERRUPT1                  _VECTOR(2)
509#define SIG_INT1                        _VECTOR(2)
510
511/* Timer/Counter1 Capture Event */
512#define TIMER1_CAPT_vect                _VECTOR(3)
513#define SIG_INPUT_CAPTURE1              _VECTOR(3)
514#define SIG_TIMER1_CAPT                 _VECTOR(3)
515
516/* Timer/Counter1 Compare Match A */
517#define TIMER1_COMPA_vect               _VECTOR(4)
518#define SIG_OUTPUT_COMPARE1A            _VECTOR(4)
519#define SIG_TIMER1_COMPA                _VECTOR(4)
520
521/* Timer/Counter1 Overflow */
522#define TIMER1_OVF_vect                 _VECTOR(5)
523#define SIG_OVERFLOW1                   _VECTOR(5)
524#define SIG_TIMER1_OVF                  _VECTOR(5)
525
526/* Timer/Counter0 Overflow */
527#define TIMER0_OVF_vect                 _VECTOR(6)
528#define SIG_OVERFLOW0                   _VECTOR(6)
529#define SIG_TIMER0_OVF                  _VECTOR(6)
530
531/* USART, Rx Complete */
532#define USART_RX_vect                   _VECTOR(7)
533#define SIG_USART0_RECV                 _VECTOR(7)
534#define SIG_USART0_RX                   _VECTOR(7)
535
536/* USART Data Register Empty */
537#define USART_UDRE_vect                 _VECTOR(8)
538#define SIG_USART0_DATA                 _VECTOR(8)
539#define SIG_USART0_UDRE                 _VECTOR(8)
540
541/* USART, Tx Complete */
542#define USART_TX_vect                   _VECTOR(9)
543#define SIG_USART0_TRANS                _VECTOR(9)
544#define SIG_USART0_TX                   _VECTOR(9)
545
546/* Analog Comparator */
547#define ANA_COMP_vect                   _VECTOR(10)
548#define SIG_COMPARATOR                  _VECTOR(10)
549#define SIG_ANALOG_COMP                 _VECTOR(10)
550#define PCINT_vect                      _VECTOR(11)
551#define SIG_PIN_CHANGE                  _VECTOR(11)
552#define SIG_PCINT                       _VECTOR(11)
553#define TIMER1_COMPB_vect               _VECTOR(12)
554#define SIG_OUTPUT_COMPARE1B            _VECTOR(12)
555#define SIG_TIMER1_COMPB                _VECTOR(12)
556#define TIMER0_COMPA_vect               _VECTOR(13)
557#define SIG_OUTPUT_COMPARE0A            _VECTOR(13)
558#define SIG_TIMER0_COMPA                _VECTOR(13)
559#define TIMER0_COMPB_vect               _VECTOR(14)
560#define SIG_OUTPUT_COMPARE0B            _VECTOR(14)
561#define SIG_TIMER0_COMPB                _VECTOR(14)
562
563/* USI Start Condition */
564#define USI_START_vect                  _VECTOR(15)
565#define SIG_USI_START                   _VECTOR(15)
566#define SIG_USI_START                   _VECTOR(15)
567
568/* USI Overflow */
569#define USI_OVERFLOW_vect               _VECTOR(16)
570#define SIG_USI_OVERFLOW                _VECTOR(16)
571#define SIG_USI_OVERFLOW                _VECTOR(16)
572#define EEPROM_READY_vect               _VECTOR(17)
573#define SIG_EEPROM_READY                _VECTOR(17)
574#define SIG_EE_READY                    _VECTOR(17)
575
576/* Watchdog Timer Overflow */
577#define WDT_OVERFLOW_vect               _VECTOR(18)
578#define SIG_WATCHDOG_TIMEOUT            _VECTOR(18)
579#define SIG_WDT_OVERFLOW                _VECTOR(18)
580
581/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */
582#define _VECTORS_SIZE     38
583
584/* Constants */
585#define SPM_PAGESIZE 32
586#define RAMEND       0xDF
587#define XRAMEND      RAMEND
588#define E2END        0x7F
589#define E2PAGESIZE   4
590#define FLASHEND     0x07FF
591
592
593/* Fuses */
594#define FUSE_MEMORY_SIZE 3
595
596/* Low Fuse Byte */
597#define FUSE_CKSEL0      (unsigned char)~_BV(0)
598#define FUSE_CKSEL1      (unsigned char)~_BV(1)
599#define FUSE_CKSEL2      (unsigned char)~_BV(2)
600#define FUSE_CKSEL3      (unsigned char)~_BV(3)
601#define FUSE_SUT0        (unsigned char)~_BV(4)
602#define FUSE_SUT1        (unsigned char)~_BV(5)
603#define FUSE_CKOUT       (unsigned char)~_BV(6)
604#define FUSE_CKDIV8      (unsigned char)~_BV(7)
605#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
606
607/* High Fuse Byte */
608#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
609#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
610#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
611#define FUSE_BODLEVEL2   (unsigned char)~_BV(3)
612#define FUSE_WDTON       (unsigned char)~_BV(4)
613#define FUSE_SPIEN       (unsigned char)~_BV(5)
614#define FUSE_EESAVE      (unsigned char)~_BV(6)
615#define FUSE_DWEN        (unsigned char)~_BV(7)
616#define HFUSE_DEFAULT (FUSE_SPIEN)
617
618/* Extended Fuse Byte */
619#define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
620#define EFUSE_DEFAULT (0xFF)
621
622
623/* Lock Bits */
624#define __LOCK_BITS_EXIST
625
626
627/* Signature */
628#define SIGNATURE_0 0x1E
629#define SIGNATURE_1 0x91
630#define SIGNATURE_2 0x0A
631
632
633#endif  /* _AVR_IOTN2313_H_ */
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