source: rtems/cpukit/score/cpu/avr/avr/iotn15.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 6.8 KB
Line 
1/* Copyright (c) 2002,2005 Marek Michalkiewicz
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotn15.h - definitions for ATtiny15 */
34
35#ifndef _AVR_IOTN15_H_
36#define _AVR_IOTN15_H_ 1
37
38/* This file should only be included from <avr/io.h>, never directly. */
39
40#ifndef _AVR_IO_H_
41#  error "Include <avr/io.h> instead of this file."
42#endif
43
44#ifndef _AVR_IOXXX_H_
45#  define _AVR_IOXXX_H_ "iotn15.h"
46#else
47#  error "Attempt to include more than one <avr/ioXXX.h> file."
48#endif
49
50#ifndef __ASSEMBLER__
51#  warning "MCU not supported by the C compiler"
52#endif
53
54/* I/O registers */
55
56/* 0x00..0x03 reserved */
57
58#ifndef __ASSEMBLER__
59#define ADC     _SFR_IO16 (0x04)
60#endif
61#define ADCW    _SFR_IO16(0x04)
62#define ADCL    _SFR_IO8(0x04)
63#define ADCH    _SFR_IO8(0x05)
64#define ADCSR   _SFR_IO8(0x06)
65#define ADMUX   _SFR_IO8(0x07)
66
67/* Analog Comparator Control and Status Register */
68#define ACSR    _SFR_IO8(0x08)
69
70/* 0x09..0x15 reserved */
71
72/* Input Pins, Port B */
73#define PINB    _SFR_IO8(0x16)
74
75/* Data Direction Register, Port B */
76#define DDRB    _SFR_IO8(0x17)
77
78/* Data Register, Port B */
79#define PORTB   _SFR_IO8(0x18)
80
81/* 0x19..0x1B reserved */
82
83/* EEPROM Control Register */
84#define EECR    _SFR_IO8(0x1C)
85
86/* EEPROM Data Register */
87#define EEDR    _SFR_IO8(0x1D)
88
89/* EEPROM Address Register */
90#define EEAR    _SFR_IO8(0x1E)
91#define EEARL   _SFR_IO8(0x1E)
92
93/* 0x1F..0x20 reserved */
94
95/* Watchdog Timer Control Register */
96#define WDTCR   _SFR_IO8(0x21)
97
98/* 0x22..0x2B reserved */
99#define SFIOR   _SFR_IO8(0x2C)
100
101#define OCR1B   _SFR_IO8(0x2D)
102#define OCR1A   _SFR_IO8(0x2E)
103#define TCNT1   _SFR_IO8(0x2F)
104#define TCCR1   _SFR_IO8(0x30)
105
106/* Oscillator Calibration Register */
107#define OSCCAL  _SFR_IO8(0x31)
108
109/* Timer/Counter0 (8-bit) */
110#define TCNT0   _SFR_IO8(0x32)
111
112/* Timer/Counter0 Control Register */
113#define TCCR0   _SFR_IO8(0x33)
114
115/* MCU general Status Register */
116#define MCUSR   _SFR_IO8(0x34)
117
118/* MCU general Control Register */
119#define MCUCR   _SFR_IO8(0x35)
120
121/* 0x36..0x37 reserved */
122
123/* Timer/Counter Interrupt Flag Register */
124#define TIFR    _SFR_IO8(0x38)
125
126/* Timer/Counter Interrupt MaSK Register */
127#define TIMSK   _SFR_IO8(0x39)
128
129/* General Interrupt Flag Register */
130#define GIFR    _SFR_IO8(0x3A)
131
132/* General Interrupt MaSK register */
133#define GIMSK   _SFR_IO8(0x3B)
134
135/* 0x3C..0x3E reserved */
136
137/* 0x3F SREG */
138
139/* Interrupt vectors */
140
141/* External Interrupt 0 */
142#define INT0_vect                       _VECTOR(1)
143#define SIG_INTERRUPT0                  _VECTOR(1)
144
145/* External Interrupt Request 0 */
146#define IO_PINS_vect                    _VECTOR(2)
147#define SIG_PIN                         _VECTOR(2)
148#define SIG_PIN_CHANGE                  _VECTOR(2)
149
150/* Timer/Counter1 Compare Match */
151#define TIMER1_COMP_vect                _VECTOR(3)
152#define SIG_OUTPUT_COMPARE1A            _VECTOR(3)
153
154/* Timer/Counter1 Overflow */
155#define TIMER1_OVF_vect                 _VECTOR(4)
156#define SIG_OVERFLOW1                   _VECTOR(4)
157
158/* Timer/Counter0 Overflow */
159#define TIMER0_OVF_vect                 _VECTOR(5)
160#define SIG_OVERFLOW0                   _VECTOR(5)
161
162/* EEPROM Ready */
163#define EE_RDY_vect                     _VECTOR(6)
164#define SIG_EEPROM_READY                _VECTOR(6)
165
166/* Analog Comparator */
167#define ANA_COMP_vect                   _VECTOR(7)
168#define SIG_COMPARATOR                  _VECTOR(7)
169
170/* ADC Conversion Ready */
171#define ADC_vect                        _VECTOR(8)
172#define SIG_ADC                         _VECTOR(8)
173
174#define _VECTORS_SIZE 18
175
176/* Bit numbers */
177
178/* GIMSK */
179#define INT0    6
180#define PCIE    5
181
182/* GIFR */
183#define INTF0   6
184#define PCIF    5
185
186/* TIMSK */
187#define OCIE1   6
188#define TOIE1   2
189#define TOIE0   1
190
191/* TIFR */
192#define OCF1    6
193#define TOV1    2
194#define TOV0    1
195
196/* MCUCR */
197#define PUD     6
198#define SE      5
199#define SM1     4
200#define SM0     3
201#define ISC01   1
202#define ISC00   0
203
204/* MCUSR */
205#define WDRF    3
206#define BORF    2
207#define EXTRF   1
208#define PORF    0
209
210/* TCCR0 */
211#define CS02    2
212#define CS01    1
213#define CS00    0
214
215/* TCCR1 */
216#define CTC1    7
217#define PWM1    6
218#define COM1A1  5
219#define COM1A0  4
220#define CS13    3
221#define CS12    2
222#define CS11    1
223#define CS10    0
224
225/* SFIOR */
226#define FOC1A   2
227#define PSR1    1
228#define PSR0    0
229
230/* WDTCR */
231#define WDTOE   4
232#define WDE     3
233#define WDP2    2
234#define WDP1    1
235#define WDP0    0
236
237/*
238   PB5 = RESET# / ADC0
239   PB4 = ADC3
240   PB3 = ADC2
241   PB2 = SCK / ADC1 / T0 / INT0
242   PB1 = MISO / AIN1 / OCP
243   PB0 = MOSI / AIN0 / AREF
244 */
245
246/* PORTB */
247#define PB4     4
248#define PB3     3
249#define PB2     2
250#define PB1     1
251#define PB0     0
252
253/* DDRB */
254#define DDB4    4
255#define DDB3    3
256#define DDB2    2
257#define DDB1    1
258#define DDB0    0
259
260/* PINB */
261#define PINB5   5
262#define PINB4   4
263#define PINB3   3
264#define PINB2   2
265#define PINB1   1
266#define PINB0   0
267
268/* ACSR */
269#define ACD     7
270#define GREF    6
271#define ACO     5
272#define ACI     4
273#define ACIE    3
274#define ACIS1   1
275#define ACIS0   0
276
277/* ADMUX */
278#define REFS1   7
279#define REFS0   6
280#define ADLAR   5
281#define MUX2    2
282#define MUX1    1
283#define MUX0    0
284
285/* ADCSR */
286#define ADEN    7
287#define ADSC    6
288#define ADFR    5
289#define ADIF    4
290#define ADIE    3
291#define ADPS2   2
292#define ADPS1   1
293#define ADPS0   0
294
295/* EEPROM Control Register */
296#define EERIE   3
297#define EEMWE   2
298#define EEWE    1
299#define EERE    0
300
301/* Last memory addresses */
302#define RAMEND          0x1F
303#define XRAMEND         0x0
304#define E2END           0x3F
305#define E2PAGESIZE  2
306#define FLASHEND        0x3FF
307
308
309/* Fuses */
310
311#define FUSE_MEMORY_SIZE 1
312
313/* Fuse Byte */
314#define FUSE_CKSEL0      (unsigned char)~_BV(0)
315#define FUSE_CKSEL1      (unsigned char)~_BV(1)
316#define FUSE_RSTDISBL    (unsigned char)~_BV(4)
317#define FUSE_SPIEN       (unsigned char)~_BV(5)
318#define FUSE_BODEN       (unsigned char)~_BV(6)
319#define FUSE_BODLEVEL    (unsigned char)~_BV(7)
320#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN)
321
322
323/* Lock Bits */
324#define __LOCK_BITS_EXIST
325
326
327/* Signature */
328#define SIGNATURE_0 0x1E
329#define SIGNATURE_1 0x90
330#define SIGNATURE_2 0x06
331
332
333#endif /* _AVR_IOTN15_H_ */
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