[04a62dce] | 1 | /* Copyright (c) 2002,2005 Marek Michalkiewicz |
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| 2 | All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | * Redistributions of source code must retain the above copyright |
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| 8 | notice, this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | * Redistributions in binary form must reproduce the above copyright |
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| 11 | notice, this list of conditions and the following disclaimer in |
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| 12 | the documentation and/or other materials provided with the |
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| 13 | distribution. |
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| 14 | |
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| 15 | * Neither the name of the copyright holders nor the names of |
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| 16 | contributors may be used to endorse or promote products derived |
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| 17 | from this software without specific prior written permission. |
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| 18 | |
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| 19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 22 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 23 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 24 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 25 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 26 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 27 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 28 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 29 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 30 | |
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| 31 | /* $Id$ */ |
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| 32 | |
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| 33 | /* avr/iotn15.h - definitions for ATtiny15 */ |
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| 34 | |
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| 35 | #ifndef _AVR_IOTN15_H_ |
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| 36 | #define _AVR_IOTN15_H_ 1 |
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| 37 | |
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| 38 | /* This file should only be included from <avr/io.h>, never directly. */ |
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| 39 | |
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| 40 | #ifndef _AVR_IO_H_ |
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| 41 | # error "Include <avr/io.h> instead of this file." |
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| 42 | #endif |
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| 43 | |
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| 44 | #ifndef _AVR_IOXXX_H_ |
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| 45 | # define _AVR_IOXXX_H_ "iotn15.h" |
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| 46 | #else |
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| 47 | # error "Attempt to include more than one <avr/ioXXX.h> file." |
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| 48 | #endif |
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| 49 | |
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| 50 | #ifndef __ASSEMBLER__ |
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| 51 | # warning "MCU not supported by the C compiler" |
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| 52 | #endif |
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| 53 | |
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| 54 | /* I/O registers */ |
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| 55 | |
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| 56 | /* 0x00..0x03 reserved */ |
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| 57 | |
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| 58 | #ifndef __ASSEMBLER__ |
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| 59 | #define ADC _SFR_IO16 (0x04) |
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| 60 | #endif |
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| 61 | #define ADCW _SFR_IO16(0x04) |
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| 62 | #define ADCL _SFR_IO8(0x04) |
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| 63 | #define ADCH _SFR_IO8(0x05) |
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| 64 | #define ADCSR _SFR_IO8(0x06) |
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| 65 | #define ADMUX _SFR_IO8(0x07) |
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| 66 | |
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| 67 | /* Analog Comparator Control and Status Register */ |
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| 68 | #define ACSR _SFR_IO8(0x08) |
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| 69 | |
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| 70 | /* 0x09..0x15 reserved */ |
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| 71 | |
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| 72 | /* Input Pins, Port B */ |
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| 73 | #define PINB _SFR_IO8(0x16) |
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| 74 | |
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| 75 | /* Data Direction Register, Port B */ |
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| 76 | #define DDRB _SFR_IO8(0x17) |
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| 77 | |
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| 78 | /* Data Register, Port B */ |
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| 79 | #define PORTB _SFR_IO8(0x18) |
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| 80 | |
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| 81 | /* 0x19..0x1B reserved */ |
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| 82 | |
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| 83 | /* EEPROM Control Register */ |
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| 84 | #define EECR _SFR_IO8(0x1C) |
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| 85 | |
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| 86 | /* EEPROM Data Register */ |
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| 87 | #define EEDR _SFR_IO8(0x1D) |
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| 88 | |
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| 89 | /* EEPROM Address Register */ |
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| 90 | #define EEAR _SFR_IO8(0x1E) |
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| 91 | #define EEARL _SFR_IO8(0x1E) |
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| 92 | |
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| 93 | /* 0x1F..0x20 reserved */ |
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| 94 | |
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| 95 | /* Watchdog Timer Control Register */ |
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| 96 | #define WDTCR _SFR_IO8(0x21) |
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| 97 | |
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| 98 | /* 0x22..0x2B reserved */ |
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| 99 | #define SFIOR _SFR_IO8(0x2C) |
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| 100 | |
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| 101 | #define OCR1B _SFR_IO8(0x2D) |
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| 102 | #define OCR1A _SFR_IO8(0x2E) |
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| 103 | #define TCNT1 _SFR_IO8(0x2F) |
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| 104 | #define TCCR1 _SFR_IO8(0x30) |
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| 105 | |
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| 106 | /* Oscillator Calibration Register */ |
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| 107 | #define OSCCAL _SFR_IO8(0x31) |
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| 108 | |
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| 109 | /* Timer/Counter0 (8-bit) */ |
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| 110 | #define TCNT0 _SFR_IO8(0x32) |
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| 111 | |
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| 112 | /* Timer/Counter0 Control Register */ |
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| 113 | #define TCCR0 _SFR_IO8(0x33) |
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| 114 | |
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| 115 | /* MCU general Status Register */ |
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| 116 | #define MCUSR _SFR_IO8(0x34) |
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| 117 | |
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| 118 | /* MCU general Control Register */ |
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| 119 | #define MCUCR _SFR_IO8(0x35) |
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| 120 | |
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| 121 | /* 0x36..0x37 reserved */ |
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| 122 | |
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| 123 | /* Timer/Counter Interrupt Flag Register */ |
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| 124 | #define TIFR _SFR_IO8(0x38) |
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| 125 | |
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| 126 | /* Timer/Counter Interrupt MaSK Register */ |
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| 127 | #define TIMSK _SFR_IO8(0x39) |
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| 128 | |
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| 129 | /* General Interrupt Flag Register */ |
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| 130 | #define GIFR _SFR_IO8(0x3A) |
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| 131 | |
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| 132 | /* General Interrupt MaSK register */ |
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| 133 | #define GIMSK _SFR_IO8(0x3B) |
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| 134 | |
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| 135 | /* 0x3C..0x3E reserved */ |
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| 136 | |
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| 137 | /* 0x3F SREG */ |
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| 138 | |
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| 139 | /* Interrupt vectors */ |
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| 140 | |
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| 141 | /* External Interrupt 0 */ |
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| 142 | #define INT0_vect _VECTOR(1) |
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| 143 | #define SIG_INTERRUPT0 _VECTOR(1) |
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| 144 | |
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| 145 | /* External Interrupt Request 0 */ |
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| 146 | #define IO_PINS_vect _VECTOR(2) |
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| 147 | #define SIG_PIN _VECTOR(2) |
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| 148 | #define SIG_PIN_CHANGE _VECTOR(2) |
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| 149 | |
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| 150 | /* Timer/Counter1 Compare Match */ |
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| 151 | #define TIMER1_COMP_vect _VECTOR(3) |
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| 152 | #define SIG_OUTPUT_COMPARE1A _VECTOR(3) |
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| 153 | |
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| 154 | /* Timer/Counter1 Overflow */ |
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| 155 | #define TIMER1_OVF_vect _VECTOR(4) |
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| 156 | #define SIG_OVERFLOW1 _VECTOR(4) |
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| 157 | |
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| 158 | /* Timer/Counter0 Overflow */ |
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| 159 | #define TIMER0_OVF_vect _VECTOR(5) |
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| 160 | #define SIG_OVERFLOW0 _VECTOR(5) |
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| 161 | |
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| 162 | /* EEPROM Ready */ |
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| 163 | #define EE_RDY_vect _VECTOR(6) |
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| 164 | #define SIG_EEPROM_READY _VECTOR(6) |
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| 165 | |
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| 166 | /* Analog Comparator */ |
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| 167 | #define ANA_COMP_vect _VECTOR(7) |
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| 168 | #define SIG_COMPARATOR _VECTOR(7) |
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| 169 | |
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| 170 | /* ADC Conversion Ready */ |
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| 171 | #define ADC_vect _VECTOR(8) |
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| 172 | #define SIG_ADC _VECTOR(8) |
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| 173 | |
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| 174 | #define _VECTORS_SIZE 18 |
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| 175 | |
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| 176 | /* Bit numbers */ |
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| 177 | |
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| 178 | /* GIMSK */ |
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| 179 | #define INT0 6 |
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| 180 | #define PCIE 5 |
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| 181 | |
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| 182 | /* GIFR */ |
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| 183 | #define INTF0 6 |
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| 184 | #define PCIF 5 |
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| 185 | |
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| 186 | /* TIMSK */ |
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| 187 | #define OCIE1 6 |
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| 188 | #define TOIE1 2 |
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| 189 | #define TOIE0 1 |
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| 190 | |
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| 191 | /* TIFR */ |
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| 192 | #define OCF1 6 |
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| 193 | #define TOV1 2 |
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| 194 | #define TOV0 1 |
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| 195 | |
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| 196 | /* MCUCR */ |
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| 197 | #define PUD 6 |
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| 198 | #define SE 5 |
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| 199 | #define SM1 4 |
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| 200 | #define SM0 3 |
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| 201 | #define ISC01 1 |
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| 202 | #define ISC00 0 |
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| 203 | |
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| 204 | /* MCUSR */ |
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| 205 | #define WDRF 3 |
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| 206 | #define BORF 2 |
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| 207 | #define EXTRF 1 |
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| 208 | #define PORF 0 |
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| 209 | |
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| 210 | /* TCCR0 */ |
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| 211 | #define CS02 2 |
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| 212 | #define CS01 1 |
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| 213 | #define CS00 0 |
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| 214 | |
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| 215 | /* TCCR1 */ |
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| 216 | #define CTC1 7 |
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| 217 | #define PWM1 6 |
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| 218 | #define COM1A1 5 |
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| 219 | #define COM1A0 4 |
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| 220 | #define CS13 3 |
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| 221 | #define CS12 2 |
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| 222 | #define CS11 1 |
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| 223 | #define CS10 0 |
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| 224 | |
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| 225 | /* SFIOR */ |
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| 226 | #define FOC1A 2 |
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| 227 | #define PSR1 1 |
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| 228 | #define PSR0 0 |
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| 229 | |
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| 230 | /* WDTCR */ |
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| 231 | #define WDTOE 4 |
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| 232 | #define WDE 3 |
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| 233 | #define WDP2 2 |
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| 234 | #define WDP1 1 |
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| 235 | #define WDP0 0 |
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| 236 | |
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| 237 | /* |
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| 238 | PB5 = RESET# / ADC0 |
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| 239 | PB4 = ADC3 |
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| 240 | PB3 = ADC2 |
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| 241 | PB2 = SCK / ADC1 / T0 / INT0 |
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| 242 | PB1 = MISO / AIN1 / OCP |
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| 243 | PB0 = MOSI / AIN0 / AREF |
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| 244 | */ |
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| 245 | |
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| 246 | /* PORTB */ |
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| 247 | #define PB4 4 |
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| 248 | #define PB3 3 |
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| 249 | #define PB2 2 |
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| 250 | #define PB1 1 |
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| 251 | #define PB0 0 |
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| 252 | |
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| 253 | /* DDRB */ |
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| 254 | #define DDB4 4 |
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| 255 | #define DDB3 3 |
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| 256 | #define DDB2 2 |
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| 257 | #define DDB1 1 |
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| 258 | #define DDB0 0 |
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| 259 | |
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| 260 | /* PINB */ |
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| 261 | #define PINB5 5 |
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| 262 | #define PINB4 4 |
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| 263 | #define PINB3 3 |
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| 264 | #define PINB2 2 |
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| 265 | #define PINB1 1 |
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| 266 | #define PINB0 0 |
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| 267 | |
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| 268 | /* ACSR */ |
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| 269 | #define ACD 7 |
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| 270 | #define GREF 6 |
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| 271 | #define ACO 5 |
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| 272 | #define ACI 4 |
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| 273 | #define ACIE 3 |
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| 274 | #define ACIS1 1 |
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| 275 | #define ACIS0 0 |
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| 276 | |
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| 277 | /* ADMUX */ |
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| 278 | #define REFS1 7 |
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| 279 | #define REFS0 6 |
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| 280 | #define ADLAR 5 |
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| 281 | #define MUX2 2 |
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| 282 | #define MUX1 1 |
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| 283 | #define MUX0 0 |
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| 284 | |
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| 285 | /* ADCSR */ |
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| 286 | #define ADEN 7 |
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| 287 | #define ADSC 6 |
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| 288 | #define ADFR 5 |
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| 289 | #define ADIF 4 |
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| 290 | #define ADIE 3 |
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| 291 | #define ADPS2 2 |
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| 292 | #define ADPS1 1 |
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| 293 | #define ADPS0 0 |
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| 294 | |
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| 295 | /* EEPROM Control Register */ |
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| 296 | #define EERIE 3 |
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| 297 | #define EEMWE 2 |
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| 298 | #define EEWE 1 |
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| 299 | #define EERE 0 |
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| 300 | |
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| 301 | /* Last memory addresses */ |
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| 302 | #define RAMEND 0x1F |
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| 303 | #define XRAMEND 0x0 |
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| 304 | #define E2END 0x3F |
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| 305 | #define E2PAGESIZE 2 |
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| 306 | #define FLASHEND 0x3FF |
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| 307 | |
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| 308 | |
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| 309 | /* Fuses */ |
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| 310 | |
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| 311 | #define FUSE_MEMORY_SIZE 1 |
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| 312 | |
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| 313 | /* Fuse Byte */ |
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| 314 | #define FUSE_CKSEL0 (unsigned char)~_BV(0) |
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| 315 | #define FUSE_CKSEL1 (unsigned char)~_BV(1) |
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| 316 | #define FUSE_RSTDISBL (unsigned char)~_BV(4) |
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| 317 | #define FUSE_SPIEN (unsigned char)~_BV(5) |
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| 318 | #define FUSE_BODEN (unsigned char)~_BV(6) |
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| 319 | #define FUSE_BODLEVEL (unsigned char)~_BV(7) |
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| 320 | #define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) |
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| 321 | |
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| 322 | |
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| 323 | /* Lock Bits */ |
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| 324 | #define __LOCK_BITS_EXIST |
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| 325 | |
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| 326 | |
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| 327 | /* Signature */ |
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| 328 | #define SIGNATURE_0 0x1E |
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| 329 | #define SIGNATURE_1 0x90 |
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| 330 | #define SIGNATURE_2 0x06 |
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| 331 | |
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| 332 | |
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| 333 | #endif /* _AVR_IOTN15_H_ */ |
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