source: rtems/cpukit/score/cpu/avr/avr/iotn13.h @ 04a62dce

4.104.11
Last change on this file since 04a62dce was 04a62dce, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 6, 2009 at 2:52:07 PM

2009-08-05 Josh Switnicki <josh.switnicki@…>

  • Makefile.am: added AVR specific Header files to score/cpu/avr/avr. These are from avr-libc 1.6 and assumed to exist by AVR applications.
  • preinstall.am: Regenerated.
  • Property mode set to 100644
File size: 11.0 KB
Line 
1/* Copyright (c) 2004, Theodore A. Roth
2   All rights reserved.
3
4   Redistribution and use in source and binary forms, with or without
5   modification, are permitted provided that the following conditions are met:
6
7   * Redistributions of source code must retain the above copyright
8     notice, this list of conditions and the following disclaimer.
9
10   * Redistributions in binary form must reproduce the above copyright
11     notice, this list of conditions and the following disclaimer in
12     the documentation and/or other materials provided with the
13     distribution.
14
15   * Neither the name of the copyright holders nor the names of
16     contributors may be used to endorse or promote products derived
17     from this software without specific prior written permission.
18
19  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  POSSIBILITY OF SUCH DAMAGE. */
30
31/* $Id$ */
32
33/* avr/iotn13.h - definitions for ATtiny13 */
34
35/* Verified 5/20/04 by Bruce Graham */
36
37#ifndef _AVR_IOTN13_H_
38#define _AVR_IOTN13_H_ 1
39
40/* This file should only be included from <avr/io.h>, never directly. */
41
42#ifndef _AVR_IO_H_
43#  error "Include <avr/io.h> instead of this file."
44#endif
45
46#ifndef _AVR_IOXXX_H_
47#  define _AVR_IOXXX_H_ "iotn13.h"
48#else
49#  error "Attempt to include more than one <avr/ioXXX.h> file."
50#endif
51
52/* I/O registers and bit names */
53
54/* ADC Control and Status Register B */
55#define ADCSRB               _SFR_IO8(0x03)
56#  define ACME                 6
57#  define ADTS2                2
58#  define ADTS1                1
59#  define ADTS0                0
60
61/* ADC Data Register */
62#ifndef __ASSEMBLER__
63#define ADC                  _SFR_IO16 (0x04)
64#endif
65#define ADCW                 _SFR_IO16 (0x04)
66#define ADCL                 _SFR_IO8(0x04)
67#define ADCH                 _SFR_IO8(0x05)
68
69/* ADC Control and Status Register A */
70#define ADCSRA               _SFR_IO8(0x06)
71#  define ADEN                 7
72#  define ADSC                 6
73#  define ADATE                5
74#  define ADIF                 4
75#  define ADIE                 3
76#  define ADPS2                2
77#  define ADPS1                1
78#  define ADPS0                0
79
80/* ADC Multiplex Selection Register */
81#define ADMUX                _SFR_IO8(0x07)
82#  define REFS0                6
83#  define ADLAR                5
84#  define MUX1                 1
85#  define MUX0                 0
86
87/* Analog Comparator Control and Status Register */
88#define ACSR                 _SFR_IO8(0x08)
89#  define ACD                  7
90#  define ACBG                 6
91#  define ACO                  5
92#  define ACI                  4
93#  define ACIE                 3
94#  define ACIS1                1
95#  define ACIS0                0
96
97/* Digital Input Disable Register 0 */
98#define DIDR0                _SFR_IO8(0x14)
99#  define ADC0D                5
100#  define ADC2D                4
101#  define ADC3D                3
102#  define ADC1D                2
103#  define AIN1D                1
104#  define AIN0D                0
105
106/* PIN Change Mask Register */
107#define PCMSK                _SFR_IO8(0x15)
108#  define PCINT5               5
109#  define PCINT4               4
110#  define PCINT3               3
111#  define PCINT2               2
112#  define PCINT1               1
113#  define PCINT0               0
114
115/* Port B Pin Utilization [2535D-AVR-04/04]
116   - PORTB5 = PCINT5/RESET#/ADC0/dW
117   - PORTB4 = PCINT4/ADC2
118   - PORTB3 = PCINT3/CLKI/ADC3
119   - PORTB2 = SCK/ADC1/T0/PCINT2
120   - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1
121   - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */
122
123/* Input Pins, Port B */
124#define PINB                 _SFR_IO8(0x16)
125#  define PINB5                5
126#  define PINB4                4
127#  define PINB3                3
128#  define PINB2                2
129#  define PINB1                1
130#  define PINB0                0
131
132/* Data Direction Register, Port B */
133#define DDRB                 _SFR_IO8(0x17)
134#  define DDB5                 5
135#  define DDB4                 4
136#  define DDB3                 3
137#  define DDB2                 2
138#  define DDB1                 1
139#  define DDB0                 0
140
141/* Data Register, Port B */
142#define PORTB                _SFR_IO8(0x18)
143#  define PB5                  5
144#  define PB4                  4
145#  define PB3                  3
146#  define PB2                  2
147#  define PB1                  1
148#  define PB0                  0
149
150/* ATtiny EEPROM Control Register EECR */
151#define EECR                 _SFR_IO8(0x1C)
152#define EEPM1                  5
153#define EEPM0                  4
154#define EERIE                  3
155#define EEMPE                  2
156#define EEPE                   1
157#define EERE                   0
158
159/* EEPROM Data Register */
160#define EEDR                 _SFR_IO8(0x1D)
161
162/* The EEPROM Address Register EEAR[6:0] */
163#define EEAR                 _SFR_IO8(0x1E)
164#define EEARL                _SFR_IO8(0x1E)
165
166/* Watchdog Timer Control Register */
167#define WDTCR                _SFR_IO8(0x21)
168#  define WDTIF                7
169#  define WDTIE                6
170#  define WDP3                 5
171#  define WDCE                 4
172#  define WDE                  3
173#  define WDP2                 2
174#  define WDP1                 1
175#  define WDP0                 0
176
177/* Clock Prescale Register */
178#define CLKPR                _SFR_IO8(0x26)
179#  define CLKPCE               7
180#  define CLKPS3               3
181#  define CLKPS2               2
182#  define CLKPS1               1
183#  define CLKPS0               0
184
185/* General Timer/Counter Control Register */
186#define GTCCR                _SFR_IO8(0x28)
187#  define TSM                  7
188#  define PSR10                0
189
190/* Output Compare 0 Register B */
191#define OCR0B                _SFR_IO8(0x29)
192
193/* debugWIRE Data Register */
194#define DWDR                 _SFR_IO8(0x2e)
195
196/* Timer/Counter 0 Control Register A */
197#define TCCR0A               _SFR_IO8(0x2f)
198#  define COM0A1               7
199#  define COM0A0               6
200#  define COM0B1               5
201#  define COM0B0               4
202#  define WGM01                1
203#  define WGM00                0
204
205/* Oscillator Calibration Register */
206#define OSCCAL               _SFR_IO8(0x31)
207
208/* Timer/Counter0 (8-bit) */
209#define TCNT0                _SFR_IO8(0x32)
210
211/* Timer/Counter 0 Control Register B */
212#define TCCR0B               _SFR_IO8(0x33)
213#  define FOC0A                7
214#  define FOC0B                6
215#  define WGM02                3
216#  define CS02                 2
217#  define CS01                 1
218#  define CS00                 0
219
220/* MCU General Status Register */
221#define MCUSR                _SFR_IO8(0x34)
222#  define WDRF                 3
223#  define BORF                 2
224#  define EXTRF                1
225#  define PORF                 0
226
227/* MCU General Control Register */
228#define MCUCR                _SFR_IO8(0x35)
229#  define PUD                  6
230#  define SE                   5
231#  define SM1                  4
232#  define SM0                  3
233#  define ISC01                1
234#  define ISC00                0
235
236/* Output Compare 0 REgister A */
237#define OCR0A                _SFR_IO8(0x36)
238
239/* Store Program Memory Control and Status Register */
240#define SPMCSR               _SFR_IO8(0x37)
241#  define CTPB                 4
242#  define RFLB                 3
243#  define PGWRT                2
244#  define PGERS                1
245#  define SPMEN                0
246#  define SELFPRGEN            0
247
248/* Timer/Counter 0 Interrupt Flag Register */
249#define TIFR0                _SFR_IO8(0x38)
250#  define OCF0B                3
251#  define OCF0A                2
252#  define TOV0                 1
253
254/* Timer/Counter 0 Interrupt MaSK Register */
255#define TIMSK0               _SFR_IO8(0x39)
256#  define OCIE0B               3
257#  define OCIE0A               2
258#  define TOIE0                1
259
260/* General Interrupt Flag Register */
261#define GIFR                 _SFR_IO8(0x3a)
262#  define INTF0                6
263#  define PCIF                 5
264
265/* General Interrupt MaSK register */
266#define GIMSK                _SFR_IO8(0x3b)
267#  define INT0                 6
268#  define PCIE                 5
269
270/* SPL and SREG are defined in <avr/io.h> */
271
272/* From the datasheet:
273   1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset
274   2 0x0001 INT0 External Interrupt Request 0
275   3 0x0002 PCINT0 Pin Change Interrupt Request 0
276   4 0x0003 TIM0_OVF Timer/Counter Overflow
277   5 0x0004 EE_RDY EEPROM Ready
278   6 0x0005 ANA_COMP Analog Comparator
279   7 0x0006 TIM0_COMPA Timer/Counter Compare Match A
280   8 0x0007 TIM0_COMPB Timer/Counter Compare Match B
281   9 0x0008 WDT Watchdog Time-out
282   10 0x0009 ADC ADC Conversion Complete */
283
284/* External Interrupt 0 */
285#define INT0_vect                       _VECTOR(1)
286#define SIG_INTERRUPT0                  _VECTOR(1)
287
288/* External Interrupt Request 0 */
289#define PCINT0_vect                     _VECTOR(2)
290#define SIG_PIN_CHANGE0                 _VECTOR(2)
291
292/* Timer/Counter0 Overflow */
293#define TIM0_OVF_vect                   _VECTOR(3)
294#define SIG_OVERFLOW0                   _VECTOR(3)
295
296/* EEPROM Ready */
297#define EE_RDY_vect                     _VECTOR(4)
298#define SIG_EEPROM_READY                _VECTOR(4)
299
300/* Analog Comparator */
301#define ANA_COMP_vect                   _VECTOR(5)
302#define SIG_COMPARATOR                  _VECTOR(5)
303
304/* Timer/Counter Compare Match A */
305#define TIM0_COMPA_vect                 _VECTOR(6)
306#define SIG_OUTPUT_COMPARE0A            _VECTOR(6)
307
308/* Timer/Counter Compare Match B */
309#define TIM0_COMPB_vect                 _VECTOR(7)
310#define SIG_OUTPUT_COMPARE0B            _VECTOR(7)
311
312/* Watchdog Time-out */
313#define WDT_vect                        _VECTOR(8)
314#define SIG_WATCHDOG_TIMEOUT            _VECTOR(8)
315
316/* ADC Conversion Complete */
317#define ADC_vect                        _VECTOR(9)
318#define SIG_ADC                         _VECTOR(9)
319
320#define _VECTORS_SIZE 20
321
322#define SPM_PAGESIZE 32
323#define RAMEND      0x9F
324#define XRAMEND     RAMEND
325#define E2END       0x3F
326#define E2PAGESIZE  4
327#define FLASHEND    0x3FF
328
329
330/* Fuses */
331
332#define FUSE_MEMORY_SIZE 2
333
334/* Low Fuse Byte */
335#define FUSE_CKSEL0      (unsigned char)~_BV(0)
336#define FUSE_CKSEL1      (unsigned char)~_BV(1)
337#define FUSE_SUT0        (unsigned char)~_BV(2)
338#define FUSE_SUT1        (unsigned char)~_BV(3)
339#define FUSE_CKDIV8      (unsigned char)~_BV(4)
340#define FUSE_WDTON       (unsigned char)~_BV(5)
341#define FUSE_EESAVE      (unsigned char)~_BV(6)
342#define FUSE_SPIEN       (unsigned char)~_BV(7)
343#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN)
344
345/* High Fuse Byte */
346#define FUSE_RSTDISBL    (unsigned char)~_BV(0)
347#define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
348#define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
349#define FUSE_DWEN        (unsigned char)~_BV(3)
350#define FUSE_SPMEN       (unsigned char)~_BV(4)
351#define HFUSE_DEFAULT (0xFF)
352
353
354/* Lock Bits */
355#define __LOCK_BITS_EXIST
356
357
358/* Signature */
359#define SIGNATURE_0 0x1E
360#define SIGNATURE_1 0x90
361#define SIGNATURE_2 0x07
362
363
364#endif /* _AVR_IOTN13_H_*/
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